Datasheet tda8351 DATASHEETS (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

TDA8351

DC-coupled vertical deflection circuit

Preliminary speciﬁcation Supersedes data of June 1992 File under Integrated Circuits, IC02

Philips Semiconductors

January 1995

Page 2

Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

FEATURES

• Few external components

• Highly efficient fully DC-coupled vertical output bridge

circuit

• Vertical flyback switch

GENERAL DESCRIPTION

The TDA8351 is a power circuit for use in 90° and 110° colour deflection systems for field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system.

• Guard circuit

• Protection against:

– short-circuit of the output pins (7 and 4) – short-circuit of the output pins to V

• Temperature (thermal) protection

• High EMC immunity because of common mode inputs

• A guard signal in zoom mode.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC supply

supply voltage 9 − 25 V quiescent supply current − 30 − mA

Vertical circuit

O(p-p)

output current

−−3A

(peak-to-peak value)

diff(p-p)

differential input current

− 600 −µA

(peak-to-peak value)

diff(p-p)

differential input voltage

− 1.5 1.8 V

(peak-to-peak value)

Flyback switch

peak output current −−±1.5 A ﬂyback supply voltage −−50 V

note 1 −−60 V

Thermal data (in accordance with IEC 747-1)

stg

amb

storage temperature −55 − +150 °C operating ambient temperature −25 − +75 °C virtual junction temperature −−150 °C

Note

1. A flyback supply voltage of>50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 Ω resistor (dependent on I

and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling

capacitor of VFB has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of 33 Ω (see application circuit Fig.6).

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

ORDERING INFORMATION

TYPE NUMBER

TDA8351 SIL9P plastic single-in-line power package; 9 leads SOT131-2

BLOCK DIAGRAM

handbook, full pagewidth

NAME DESCRIPTION VERSION

TDA8351

drive(pos)

drive(neg)

O(guard)

CURRENT

SOURCE

PACKAGE

O(A)

I(fb)

5 GND

Fig.1 Block diagram.

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O(B)

MBC988- 1

O(B)

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

PINNING

SYMBOL PIN DESCRIPTION

drive(pos)

drive(neg)

O(B)

1 input power-stage (positive);

includes I

signal bias

I(sb)

2 input power-stage (negative);

includes I

signal bias

I(sb)

3 operating supply voltage

4 output voltage B GND 5 ground V

O(A)

O(guard)

I(fb)

handbook, 2 columns

drive(pos)

drive(neg)

6 input ﬂyback supply voltage

7 output voltage A

8 guard output voltage

9 input feedback voltage

1 2

O(B)

GND

TDA8351

O(guard)

O(A)

I(fb)

7 8 9

FUNCTIONAL DESCRIPTION

The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in phase opposition. An external resistor (RM) connected in series with the deflection coil provides internal feedback information. The differential input circuit is voltage driven. The input circuit has been adapted to enable it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and TDA8376 which deliver symmetrical current signals. An external resistor

) connected between the differential input

CON

determines the output current through the deflection coil. The relationship between the differential input current and the output current is defined by: I

diff

× R

CON=Icoil

× RM. The output current is adjustable from 0.5 A (p-p) to 3 A (p-p) by varying RM. The maximum input differential voltage is 1.8 V. In the application it is recommended that V

= 1.5 V (typ). This is recommended because of the

diff

spread of input current and the spread in the value of R

CON

The flyback voltage is determined by an additional supply voltage VFB. The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage VFB optimum for the flyback voltage. Using this method, very high efficiency is achieved.

The supply voltage VFB is almost totally available as flyback voltage across the coil, this being possible due to the absence of a decoupling capacitor (not necessary, due to the bridge configuration). The output circuit is fully protected against the following:

• thermal protection

• short-circuit protection of the output pins (pins 4 and 7)

• short-circuit of the output pins to VP.

Metal block connected to substrate pin 5. Metal on back.

Fig.2 Pin configuration.

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MBC989

A guard circuit V

is provided. The guard circuit is

O(guard)

activated at the following conditions:

• during flyback

• during short-circuit of the coil and during short-circuit of

the output pins (pins 4 and 7) to VP or ground

• during open loop

• when the thermal protection is activated.

This signal can be used for blanking the picture tube screen.

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

DC supply

Vertical circuit

O(p-p)

O(A)

Flyback switch

Thermal data (in accordance with IEC 747-1)

stg

amb

th vj-c

th vj-a

supply voltage non-operating − 40 V

− 25 V

ﬂyback supply voltage − 50 V

note 1 − 60 V

output current (peak-to-peak value) note 2 − 3A output voltage (pin 7) − 52 V

note 1 − 62 V

peak output current −±1.5 A

storage temperature −55 +150 °C operating ambient temperature −25 +75 °C virtual junction temperature − 150 °C resistance vj-case − 4 K/W resistance vj-ambient in free air − 40 K/W short-circuiting time note 3 − 1hr

Notes

1. A flyback supply voltage of>50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 Ω resistor (dependent on I

and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling

capacitor of VFB has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of 33 Ω (see application circuit Fig.6).

2. IO maximum determined by current protection.

3. Up to VP=18V.

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

CHARACTERISTICS

VP= 17.5 V; T speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC supply

Vertical circuit

LE linearity error I

| output offset current I

| offset voltage at the input of the

T output offset voltage as a function

∆V

O(A)

res

T current gain drift as a function of

∆G

I(sb)

PSRR power supply ripple rejection note 7 − 80 − dB V

I(DC)

I(CM)

bias

O(CM)

=25°C; VFB= 45 V; fi= 50 Hz; I

amb

= 400 µA; measured in test circuit of Fig.3; unless otherwise

I(sb)

operating supply voltage 9.0 − 25 V ﬂyback supply voltage V

note 1 V

P P

− 50 V

− 60 V

supply current no signal; no load − 30 55 mA

output voltage swing (scan) I

= 0.6 mA (p-p);

diff

= 1.8 V (p-p);

diff

19.8 −−V

IO= 3 A (p-p)

= 3 A (p-p); note 2 − 12%

= 50 mA (p-p); note 2 − 12%

output voltage swing (ﬂyback) V

O(A)-VO(B)

forward voltage of the internal efﬁciency diode (V

O(A)-VFB

feedback ampliﬁer (V

)

I(fb)-VO(B)

= 0.3 mA;

diff

IO= 1.5 A (M) IO= −1.5 A (M);

= 0.3 mA

diff

=0;

diff

=50to500µA

I(sb)

=0;

diff

)

=50to500µA

I(sb)

=0 −−72 µV/K

diff

− 39 − V

−−1.5 V

−−30 mA

−−18 mV

of temperature DC output voltage I open-loop voltage gain (V

7-4/V1-2

open loop voltage gain

; V

7-4/V9-4

voltage ratio V

1-2

=0)

1-2/V9-4

= 0; note 3 − 8.0 − V

diff

) notes 4 and 5 − 80 − dB

note 4 − 80 − dB

− 0 − dB frequency response (−3 dB) open loop; note 6 − 40 − Hz current gain (IO/I

) − 5000 −

diff

−−10

−4

temperature signal bias current 50 400 500 µA ﬂyback supply current during scan −−100 µA

DC input voltage − 2.7 − V common mode input voltage I input bias current I common mode output current ∆I

=0 0 − 1.6 V

I(sb)

=0 − 0.1 0.5 µA

I(sb)

= 300 µA (p-p);

I(sb)

fi= 50 Hz; I

diff

− 0.2 − mA

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Guard circuit

O(guard)

output current not active;

O(guard)

active; V

=0V

O(guard)

= 4.5 V 1 − 2.5 mA output voltage on pin 8 IO= 100 µA −−5.5 V allowable voltage on pin 8 maximum leakage

current = 10 µA;

Notes

1. A flyback supply voltage of>50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 Ω resistor (dependent on I

and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling

capacitor of VFB has to be connected between pin 6 and pin 3. This supply voltage line must have a resistance of 33 Ω (see application circuit Fig.6).

2. The linearity error is measured without S-correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal I

4-I7(VRM

) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and not adjacent blocks (NAB) are given below

–

kak1+()

LEAB

= NAB

----------------------------- a

3. Referenced to V

avg

;

maxamin

----------------------------- a

–

avg

4. V values within formulae, relate to voltages at or between relative pin numbers, i.e. V pins 7 and 4 divided by voltage value across pins 1 and 2.

5. V

6. Frequency response V

7. At V

AC short-circuited.

9-4

= 500 mV eff; measured across RM; fi= 50 Hz.

(ripple)

is equal to frequency response V

7-4/V9-4

7-4/V1-2

−−50 µA

−−40 V

7-4/V1-2

= voltage value across

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

handbook, full pagewidth

I(sb)

signal

bias

drive(pos)

drive(neg)

signal

bias

I(sb)

CON

3 kΩ

O(guard)

TDA8351

diff

2.2 kΩ

FEEDBACK

INPUT

GND

MBC987 - 1

Fig.3 Test diagram.

R = 6.0 Ω

R = 0.7 Ω

handbook, full pagewidth

diff

Fig.4 Input currents.

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diff

CON

TDA8351

MLA776

diff

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

APPLICATION INFORMATION

handbook, full pagewidth

VP= 14 V; I

O(p-p)

I(sb)

signal

bias

drive(pos)

drive(neg)

signal

bias

I(sb)

= 2.14 A; I

= 400 µA; I

I(sb)

CON 3 kΩ

diff(p-p)

O(guard)

TDA8351

diff

= 500 µA; VFB= 42 V; tFB= 0.6 ms.

Fig.5 Application diagram.

FEEDBACK

GND

INPUT

MBC986 - 1

O(A)

I(fb)

O(B)

100

(coil)

deflection coil AT6005/31 L = 8.63 mH R = 5.0 Ω

R = 0.7 Ω

January 1995 9

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

handbook, full pagewidth

signal

VP= 14 V; I

O(p-p)

= 2.14 A; I

I(sb)

bias

bias I

I(sb)

drive(pos)

drive(neg)

I(sb)

CON 3 kΩ

= 400 µA; I

O(guard)

TDA8351

diff

= 500 µA; VFB= 60 V; tFB= 0.4 ms.

diff(p-p)

FEEDBACK

GND

INPUT

MLA777

100 nF

O(A)

I(fb)

R = 0.7 Ω

O(B)

(coil)

220 nF

20 Ω

deflection coil AT6005/31 L = 8.63 mH R = 5.0 Ω

Fig.6 Application circuit; 50 V ≤ VFB≤ 60 V.

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

PACKAGE OUTLINE

24.4

handbook, full pagewidth

12.4

11.6

3.4

3.1

0.05 convex

987654321

23.6

20.0

19.6 10

mounting base

seating plane

4.7

4.1

17.2

16.5

Dimensions in mm.

2.20

1.45

0.75

0.60

0.25 M (9x)

2.54 (8x)

MBC360

Fig.7 Plastic single-in-line power package; 9 leads (SIL9P; SOT131-2).

0.55

0.35

2.1

1.8

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Philips Semiconductors Preliminary speciﬁcation

DC-coupled vertical deﬂection circuit TDA8351

SOLDERING Plastic single in-line packages

Y DIP OR WAVE

B The maximum permissible temperature of the solder is

260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

EPAIRING SOLDERED JOINTS

R Apply the soldering iron below the seating plane (or not

more than 2 mm above it. If its temperature is below 300 °C, it must not be in contact for more than 10 s; if between 300 and 400 °C, for not more than 5 s.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

January 1995 12