Datasheet TDA8304 Datasheet

Page 1

FEATURES

Gain controlled vision IF amplifier
Synchronous demodulator for negative and positive
AGC detector operating on peak sync amplitude for negative demodulation and on vision peak white level for positive demodulation
Tuner AGC
AFC circuit with on/off-switch
Video preamplifier
Video switch to select either the internal video signal or an external video signal
Horizontal oscillator and synchronization circuit with two control loops
Vertical synchronization (divider system), ramp generator and driver with automatic amplitude adjustment for 50 and 60 Hz
Transmitter identification (mute)
Sandcastle pulse generation
Auto VCR switch
50/60 Hz identification

GENERAL DESCRIPTION

The TDA8304 possesses the capability to demodulate IF signals having either positive or negative-going video information. It is housed within a 32-pin encapsulation. The device includes a three-stage video IF amplifier, AFC and AGC circuitry, integral three-level sandcastle pulse

ORDERING INFORMATION

EXTENDED		PACKAGE
TYPE NUMBER	PINS	PIN POSITION	MATERIAL	CODE
TDA8304	32	DIL	plastic	SOT201

generator, fully synchronized horizontal and vertical time bases with drive circuits, a video switch and a transmitter identification/mute circuit. A functional colour TV receiver can thus be realised with the addition of a tuner, audio demodulator and amplifier, chrominance decoder and respective line and field deflection circuitry.

FUNCTIONAL DESCRIPTION

Video IF amplifier, demodulator and video amplifier

Each of the three AC-coupled IF stages permits the omission of DC feedback and possesses a control range in excess of 20 dB.

The IF amplifier is followed by a passive synchronous demodulator providing a regenerated carrier signal. This is limited by a logarithmic limiter circuit prior to its application to the demodulator. Improved picture synchronization is provided by a wider bandwidth together with improved video amplifier linearity. The video amplifier contains also a white spot inverter and a noise clamp which limits interference pulses to a point below the peak sync level.

AFC-circuit

The reference signal for the AFC quadrature demodulator can also be acquired from the tuned circuit of the because an accurate 90° phase shift is realised internally. In this way only one tuned circuit needs to be applied and only one adjustment has to be carried out. The AFC output is affected by the asymmetrical frequency spectrum of the signal fed to the quadrature demodulator, which is determined by the SAW filter characteristic. To overcome this video frequency dependency of the AFC output, the demodulator output is followed by a sample-and-hold circuit For the reception of negative-going signals, the output is sampled only during peak sync (where a non-modulated carrier is present). When receiving signals with positive modulation the AFC is continuously active but extensively filtered Substantial noise will be present on the quadrature demodulator input signal during reception of very weak signals. This noise has an asymmetrical frequency spectrum ( with respect to the IF carrier) causing an offset in the AFC output voltage. This effect can be minimized by applying a notch in the demodulator tuned circuit. The sample-and-hold circuit is followed by an amplifier with high output impedance. The steepness of the of the AFC control voltage can be lowered by applying load resistors from the output to the supply and to ground. The AFC output is switched off when the AFC sample pin (22) is connected to around.

September 1991

Page 2

TDA8304

QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply	Supply
V _P	supply voltage (pin 8)		10	12	13.2	V
I _P	supply current (pin 8)		90	115	140	mA
\| _start	start current (pin 12)	note 1	-	6.5	9	mA
Video
V _9-10(rms)	IF sensitivity (RMS value)	note 2	25	40	65	μV
G _9-10	IF gain control range		-	74	-	dB
S/N	signal-to-noise ratio	input signal = 10 mV	52	58	-	dB
V ₂₁	AFC output voltage swing		10.5	-	11.5	٧
Video switch
V _16(p-p)	internal video input (peak-to-peak value)	V _o = 2.5 V(p-p)	-	2	-	V
V _13(p-p)	external video input (peak-to-peak value)	V _o = 2.5 V(p-p)	-	1	-	٧
V _15(p-p)	video output signal (peak-to-peak value)		2.3	2.5	2.7	٧
Sync
V ₂₈	required sync pulse amplitude	note 3	200	750	-	mV
1 ₃₀	required input current during flyback pulse		0.1	•	2	mA
V ₃₀	sandcastle output during burstkey horizontal blanking vertical blanking		8 4 2.1	- 4.4 2.5	- 5 2.9	>
V ₂₅	video transmitter identification output no signal condition signal condition		•	0.3 9.8	-	v v
V ₅	vertical feedback for DC voltage		2.9	3.3	3.7	V
V _5(p-p)	vertical feedback for AC voltage (peak-to-peak value)		-	1	•	v

Notes to the quick reference data

Supplying a current of 9 mA to pin 12 starts the horizontal oscillator. This current can be obtained via a bleed circuit from the mains rectifier whilst the main supply for the device (V_∞) is obtained from the horizontal output stage. The load current of the driver must be added to the value given.

2. On set AGC.

3. The minimum value is obtained by connecting a 1.8 kΩ resistor between pins 15 and 28. The slicing level can be varied by changing the value of this resistor (higher resistor value results in larger value of the minimum sync pulse amplitude). The slicing level is independent of the video information.

Page 3

Preliminary specification

TDA8304

Small signal combination IC for colour TV

September 1991

Page 4

PINNING

PIN	DESCRIPTION
1	black level clamp internal video
2	tuner take-over
3	vertical ramp generator
4	vertical drive
5	vertical feedback
6	tuner AGC
7	ground
8	supply voltage input
9	video IF input
10	video IF input
11	IF AGC
12	start horizontal oscillator/text-mode switch
13	external video input
14	50 - 60 Hz output
15	video switch output
16	internal video input
17	AGC detector
18	video switch input
19	ground for some critical parts
20	video amplifier output
21	AFC output
22	AFC S/H, AFC switch input
23	video demodulator tuned circuit
24	video demodulator tuned circuit
25	coincidence detector/transmitter identification
26	horizontal oscillator
27	phase 1 detector
28	sync separator input
29	horizontal drive output
30	sandcastle output/horizontal flyback input
31	phase 2 detector
32	system switch input

AGC circuit

For signals employing negative modulation the AGC detector operates on peak sync level and on peak white level with those having positive modulation. Selection is

facilitated by the system switch (pin 32), see Table 1.

The charge current at positive modulation (see Table 2) is only present during the vertical sync or when the level at pin 1 drops 200 mV below the level of pin 17 as a

mV belo

result of input signal variations. To obtain rapid AGC action when executing a search tuning operation when the circuit is set for peak white AGC, the charge current is increased to 55 µA until the detection of a transmitted signal. With an AGC capacitor of 6.8 µF the video tilt will be < 2% for positive and for negative modulated signals.

VCR switch

The TDA8304 has an auto VCR-switch facility. Due to the inherent instability of signals from a VCR, the horizontal time constant should be shorter to prevent loss of horizontal synchronization in the early part of the scan. Provision is therefore incorporated (in the internal video mode) to automatically switch the short time constant such that a strong signal instigates the 'VCR' mode and a weak signal triggers the TV' mode. The phase detector is gated during the 'TV mode' and operates with a long time constant. The phase detector is not gated in the VCR mode and operates with a short time constant. The TDA8304 is active in the 'VCB' mode only at reception of an external video signal.

Video-switch

Selection between internal video (pin 16) and external video (pin 13) is made by applying a switching potential to pin 18 (see Table 3). Video output (pin 20) from the device is filtered to remove the audio carrier and DC-coupled to pin 16. The TDA8304 provides the opportunity for a direct video connection (e.g. via a perite connector) to be made to the device at pin 13. The AGC detector is not gated during the external video mode, the first phase detector is also not gated and operates with a short time constant. The gain of the

Preliminary specification

Page 5

IF amplifier (in the external video mode) is reduced to prevent crosstalk of the video amplifier to the horizontal oscillator during the no-signal condition.

Horizontal synchronization

The horizontal synchronization circuit of the TDA8304 provides the drive pulse for a horizontal deflection stage.

The phase of the control loop will be adapted automatically to the level of the input signal in order to achieve an optimum performance
The control gradient of the control loop will be low at reception of weak signals to reduce the noise bandwidth.
The phase detector control current is increased during strong or no-signal reception to obtain a short catching time and a good performance during VCR playback.

Vertical synchronization

The TDA8304 embodies a synchronized divider system for generating the vertical sawtooth at pin 3 having several advantages and features such as:

The vertical frequency is alignment free. The divider automatically adapts to a vertical frequency of 50 Hz or 60 Hz including automatic amplitude correction and its operating modes offer maximum interference/disturbance protection.

A discriminator-window checks the accuracy of the vertical trigger pulse. Internally clockpulses are generated by doubling the line frequency. The divider operates in the 60 Hz mode when the trigger pulse appears before count 576, otherwise the 50 Hz mode will be active.
The divider system operates with a number of different reset windows. The windows are activated via an up/down counter. The counter increases its counter-value by 1 for each time the separated vertical sync pulse appears within the selected window, otherwise the counter value is lowered by 1.

Modes of operation

Large search window (divider ratio between 488 and 722). This mode is valid for the following conditions:

Divider is looking for a new transmitter
Divider ratio found does not comply with the narrow window specification limits
Up/down counter value of the divider system, operating in the narrow window mode, drops below count 10

Narrow window mode: divider ratio between 522 - 528 (60 Hz) or 622 -628 (50 Hz)

The divider system switches over to narrow window mode when the up/down counter has reached his maximum value of 15 vertical sync pulses.
When the divider operates in the narrow window mode and a vertical sync pulse is missing in the window, the divider is reset at the end of that window and the counter value is lowered by 1.

.

At a counter value below 10 the divider system switches over to the large window mode.
The divider system generate also the so-called anti-top-flutter pulse which inhibits the phase 1 detector during the vertical sync pulse. The width of this pulse depends on the divider mode. For the large window mode the start is generated at the reset of the divider. In the narrow window mode the anti-top-flutter pulse starts at the beginning of the first equalizing pulse. The anti-top-flutter pulse ends at count 10 for 50 Hz and at count 12 for 60 Hz.
The divider is switched to count 625 when out of sync is detected by the coincidence detector. This results in a stable amplitude when no input signal is available.
The divider is switched to the large window mode when enlarged vertical sync pulses are detected.

September 1991

Preliminary specification

Page 6

Preliminary specification

Small signal combination IC for colour TV

TDA8304

Table 1 AGC circuit operation

STATE	POSITIVE MODULATION	NEGATIVE MODULATION
input pin 32	HIGH/open	LOW

Table 2 AGC detector currents

STATE	POSITIVE	MODULATION	NEGATIVE	MODULATION
action	action current		current	condition
charge	10 µA	V-sync signal	55 µA	•
charge	55 μΑ	pin 25 = LOW	-	-
discharge	3 mA	VITS signal	1.5 mA	H-sync signal

Table 3 Video switch operation

STATE		EXTERNAL VIDEO
input pin 18	LOW	HIGH

QUALITY SPECIFICATION

Quality level according to UZW-BQ/FQ-601.

SYMBOL	PARAMETER	RANGE	RANGE B	UNIT
ESD	protection circuit specification (note 1)	2000	500	V
		100	200	pF
		1500	0	Ω

Note to the Quality specification

1. All pins of the IC are protected against ESD by means of the internal clamping diodes. Range A represents the human body model and range B represents the charge device model.

LIMITING VALUES

In accordance with the Absolute Maximum System (IEC 134)

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
V _P	supply voltage (pin 8)	-	13.2	V
Piot	total power dissipation	•	2.3	W
T _stg	storage temperature range	-55	+150	°C
Tamb	operating ambient temperature range	-25	+65	°C

THERMAL RESISTANCE

SYMBOL	PARAMETER		MAX.	UNIT
R _{th j∗a}	from junction to ambient in free air	30	35	K/W

Page 7

The transmitter

identification/coincidence detector

Pin 25 of the TDA8304 serves as the transmitter identification and/or coincidence detector (see Table 4). Pin 25 is HIGH (= 9.8 V) when a transmitter is present and LOW (= 0.3 V) when of no transmitter signal is detected. When the video switch is in the internal mode, the signal at the sync separator input (pin 28) is the demodulated IF signal, pin 25 will act as a coincidence detector. Pin 25 is HIGH when the horizontal

oscillator loop is synchronized with the video signal and LOW in case of no synchronization. In the external video mode and in the text mode, pin 25 will be active as transmitter identification. The system relies upon the detection of sync pulses on the incoming IF signal. Pin 25 is charged with a current of 125 µA by the separated horizontal sync pulse and discharged continuously with a current of 4 µA. The high impedance of pin 25 should be taken into account in the application concept.

Preliminary specification

TDA8304

The 50/60 Hz identification

The 50/60 Hz information (see Table 5) derived from the divider system is available at the open collector output pin 14.

Table 4 Transmitter identification/coincidence detector

STATE		INTERNAL VIDEO				EXTER	NAL VIDEO
input pin 18	LOW	W				HIGH
input pin 12	TV mode = HIGH		Text mo	ode = LOW
Input signal pins 9 and 10	yes	none	yes	none	none	yes	none
input pin 28	50/60 Hz	none	50/60 Hz	VCS text	none	don't care	don't care
output pin 25	9.8 V	0.3 V	9.8 V	0.3 V	0.3 V	9.8 V	0.3 V

Table 5 50/60 Hz identification

INPUT/OUTPUT	STATUS STATUS		STATUS
Input signal pins 9 and 10	don't care	don't care	don't care
input pin 28	50 Hz	60 Hz	none
output pin 14	0.3 V	12 V	0.3 V

Page 8

Preliminary specification

CHARACTERISTICS T_amb = 25 °C;V_p = 12 V; carrier 38.9 MHz negative modulation, unless otherwise specified

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supply (pin	Supply (pin 8)
V ₈	supply voltage range		10	12	13.2	V
l _a	supply current	no input	90	115	140	mA
I ₁₂	start current (pin 12)	note 1	-	6.5	9	mA
V ₁₂	start protection level	l ₁₂ = 12 mA	-	-	16.5	V
IF Amplifier	·
V _9-10(ms)	input sensitivity (RMS value)	note 2	25	40	65	μV
R _9-10	differential input resistance	note 3	-	1300	-	Ω
C _9-10	differential input capacitance	note 3	ŀ	5	-	pF
G _9-10	gain control range		-	74	-	dB
ΔV ₂₀	output signal expansion for 46 dB input signal variation	note 4	-	1	-	dB
V _9-10	maximum input signal		100	170	-	mV
V _9-10(ms)	input sensitivity in external mode (RMS value)	note 2	250	400	650	μV
Video Amp	lifier (notes 5 and 6)
V ₂₀	negative modulation, zero signal level		4.7	4.9	5.1	V
V ₂₀	positive modulation, zero signal level		2.5	2.7	2.9	V
V ₂₀	peak sync (negative modulation)	note 7	2.5	2.75	3.0	V
V ₂₀	white level (positive modulation)	note 7	4.7	4.9	5.1	V
V ₂₀	white spot threshold level		-	5.7	-	V
V ₂₀	white spot insertion level		-	4	•	V
Z ₂₀	video output impedance		•	25	-	Ω
1 ₂₀	internal bias current of npn emitter follower output transistor		1.4	1.8	-	mA
1 _source	maximum source current (pin 20)		10	-	-	mA
В	bandwidth of demodulated output signal		5	6	-	MHz
G ₂₀	differential gain	note 8	-	2	5	%
φ	differential phase	note 8	Ţ	2	5	deg
NL	video non-linearity	note 9	•	2	5	%
	intermodulation 1.1 MHz; blue 1.1 MHz; yellow 3.3 MHz; blue	note 10	50 50 55	60 60 65	•	dB dB dB
	3.3 MHz; yellow		55	65	\|.	L dB

Page 9

Preliminary specification

Small signal combination IC for colour TV

TDA8304

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
S/N	signal-to-noise ratio	10 mV input signal	52	58	-	dB
		end of gain control range; note 11; see Fig.5	57	62	•	dB
V ₂₀	residual carrier signal		•	2	10	mV
V ₂₀	residual 2nd harmonic of carrier signal		-	2	10	mV
System sw	vitch (note 12)
AGC ON PE	AK SYNC LEVEL FOR NEGATIVE MODULATION SIGNALS
V ₃₂	control voltage		0	-	0.8	V
1 ₃₂	input current		-100	ŀ	-500	μA
AGC ON WH	ITE LEVEL FOR POSITIVE MODULATION SIGNALS			•
V.32	control voltage		2	-	12	V
1 ₃₂	input current		0	•	1	mA
iF sync se	parator		•			•
l,	input current		0.4	0.6	0.8	mA
I ₀	output current (pin 1)		22	27	32	μA
V,	clamp level		-	3.3	-	V
Tuner AGC	;
V _9-10(rms)	minimum starting point for tuner take-over (RMS value)		-	-	0.2	mV
V _9-10(ms)	maximum starting point for tuner take-over (RMS value)		100	150	-	mV
1 ₆	maximum tuner AGC output swing	V ₆ = 3 V	4	-	-	mA
V ₆	output saturation voltage	l ₆ = 2 mA	-	1.	300	mV
l ₆	leakage current		-	•	1	μΑ
_	input signal variation complete tuner control	Δl ₆ = 2 mA	0.2	2	4	dB
V ₂	minimum voltage tuner take-over		-	•	1	V
AGC detec	tion level
I ₁₇	charge current		-	200	•	μA
I ₁₇	discharge current		-	20	-	μΑ
V ₁₇	clamp level		•	2.9	ŀ	V
Video swit	ching circuit (note 13)
EXTERNAL P
V _13(p-p)	input signal (peak-to-peak value)	V _o = 2.5 V(p-p)	-	1	-	V
1 ₁₃	input current		•	1.5	5	μA
V ₁₃	peak sync clamping level	I ₁₃ = 1 mA	1.65	1.85	2.05	V

Page 10

Preliminary specification

Philips Semiconductors

Small signal combination IC for colour TV

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
INTERNAL VID	EO INPUT					_
V _16(0-0)	Internal video input signal (peak-to-peak value	V _o = 2.5 V(p-p)	•	2	-	V
	input current		-	1.5	5	μА
V ₁₆	noise clamping level	l ₁₆ = 1 mA	2.2	2.4	2.6	V

V _15(0-0)	video output signal (peak-to-peak value)		2.3	2.5	2.7	V
V ₁₅	peak sync signal		•	3	-	V
lbiae	internal bias current (pin 15)		1	1.5	ŀ	mA
1 ₀	maximum output current (pin 15)		5	•	•	mA
α	crosstalk external to internal	notes 14 and 24	-	55	•	dB
α	crosstalk internal to external	notes 14 and 24	-	55	ŀ	dB
Video swite	ch
V.,,	input voltage for internal video		-	-	0.8	٧
V ₁₈	input voltage for external video		2	-	Vp	V
10 \|10	maximum current	V ₁₈ = 0 V	-	0.05	0.2	mA
		V ₁₈ = 12 V	-	0.25	1	mA
Text/TV sw	itch
V.,2	input voltage for text mode		-	•	0.8	V
V.,	input voltage for TV mode		2	-	Vp	V
\|'²	maximum current	V ₁₂ = 0 V	•	-	0.3	mA
		V ₁₂ = 11.5 V	-	-	1.5	mA
AFC-circui	it (note 15)
122	AFC sample and hold switch-off current		0.1	-	-	mA
1/2	output current (pin 22)	V ₂₂ = 0 V	0.2	0.4	0.8	mA
	leakage current (pin 22)		-	-	1	μΑ
Vai	AFC output voltage swing		10.5	-	11.5	V
101	available output current		±0.2	-	•	mA
	control slope		-	100	•	mV/kHz
Vo	output voltage (pin 21)	AFC off	5.5	6	6.5	V
Ro	AFC output resistance		-	40	-	kΩ
V _21(0-0 )	output voltage swing	notes 16 and 24	-	11	-	V
21(0-0)	control slope	notes 16 and 24	-	80	•	mV/kHz
V ₂₁	output voltage shift with respect to V ₁ = 10 mV(RMS)	notes 16 and 24	-	-2	•	v
Sync sepa	arator (see Fig.6)
V ₂₈	required sync pulse amplitude	note 17	200	750	·	mV
128	input current	V ₂₈ > 5 V	•	8	-	μΑ
		V ₂₈ = 0 V	-	-10	-	mA

Page 11

Preliminary specification

Small signal combination IC for colour TV

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
First contr	olloop					· ·
Δf	PLL holding range		1.	±1500	±2000	Hz
Δf	PLL catching range		±600	±1500	-	Hz
	control sensitivity to oscillator	note 18 see Fig.7
V _9-10(rms)	IF input signal for switching from fast to slow (RMS value)		•	2.2	-	mV
Second co	ntrol loop (positive edge)				_ I	1
$\frac{\delta t_d}{\delta t_o}$	control sensitivity, see Fig.6	note 19	•	100	ŀ
t,	control range	······································	-	25	-	us
Phase adju	istment (via second control loop)	- -			1
	control sensitivity		-	25	1-	uA/us
α	maximum allowed phase shift		-	±2	1-	us
Horizontal	oscillator		.l			100
	free running frequency	R = 34.3 kΩ; C = 2.7 nF	ŀ	15625	-	Hz
∆f	spread with fixed external components		-	-	4	%
Δf	frequency variations with supply voltage from 10 to 13.2 V		-	-	2	%
Δf _T	frequency variation with temperature	note 24	-	-1.6	-	Hz/°C
∆f _fr	maximum frequency deviation at start of horizontal output		-	-	10	%
Δf	frequency variation when only noise is received	note 24	•	ŀ	500	Hz
Horizontal	output (open collector; pin 29)		L.,	-1 , -	- 4	4
V ₂₉	output limiting voltage		-	•	16.5	V
Vol	output voltage LOW	I _sink = 10 mA	-	0.3	0.5	V
l _sink	maximum sink current		10	-	-	mA
	duty factor of output signal		-	46	1.	%
ţ,	rise time output pulse		•	260	1.	กร
ţ.	fall time output pulse	·	•	100	-	ns
Flyback inp	out and sandcastle output (note 20)	-L	I		,
I ₃₀	required input current during flyback pulse		0.1	-	2	mA
V ₃₀	output voltage during burstkey horizontal blanking vertical blanking		8 4 2 1	- 4.4 2.5	- 5 29	v v
tw	pulse width of burstkey at 60 Hz signals at 50 Hz signals		2.9	3.3 3.6	3.7	μs us

Page 12

Preliminary specification

Small signal combination IC for colour TV

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Flyback in	out and sandcastle output (note 20)
· ·	width of horizontal blanking pulse		flyback pulse width
	width of vertical blanking pulse				Ĭ
	divider in search window	50 Hz	-	21	-	lines
		60 Hz	-	17	•	lines
	divider in narrow window	50 Hz	-	25	-	lines
		60 Hz	•	21		lines
t _a	delay between the start of the sync pulse at	60 Hz
	the video output and the burstkey pulse			-	03
			47	54	6.1	us
			1		1	1
Vertical rar	mp generator (note 22)	-,
l ₃	input current during scan		-	-	2	μA
12	discharge current during retrace		-	0.8	-	mA
V ₂₍₀₀ )	sawtooth amplitude (peak-to-peak value)		-	1.9	-	V
t	interlace timing of the internal pulses	note 24	30	32	34	μs
Vertical ou	tput
14	available output current	V ₄ = 4 V	•	•	3	mA
V,	maximum available output voltage	l ₄ = 0.1 mA	4.4	5	-	V
Vertical fee	edback input		_
V ₅	DC input voltage		2.9	3.3	3.7	V
V _5/0-0 )	AC input voltage (peak-to-peak value)		-	1	-	V
	input current		-	-	12	μA
	internal pre-correction to sawtooth		•	3	-	%
	deviation amplitude 50/60 Hz		-	-	2	%
	temperature dependency of the amplitude	note 24 ΔT = 45 °C	-	-	2	%
Vertical gu	lard
ΔVε	active switch level at a deviation with respect	note 23;				1
	to the DC feedback level	V ₃₀ = 2.5 V		1
	guard level LOW		\|-	1.5	-	V
		1	1-	12	1.	IV

Page 13

Preliminary specification

Small signal combination IC for colour TV

TDA8304

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Coinciden	ce detector/transmitter identification (note 2	l)	1	- k		1
V ₂₅	voltage for in-sync condition		-	9.8	-	V
V ₂₅	voltage for no-sync condition	no signal	•	0.3	1.	V
V ₂₅	switching level to switch the phase detector from fast to slow		6.2	6.7	7.2	V
V ₂₅	hysteresis slow to fast		-	0.6	-	V
V ₂₅	switching level to activate the mute function (transmitter identification)		2.5	2.8	3.1	V
V ₂₅	hysteresis mute function		-	2.0	-	V
1 ₂₅	load (allowed) at pin 25		-2	-	2	μA
50/60 Hz id	entification (open collector output)			•	••	·····
V ₁₄	output voltage at 50 Hz (no signal)		-	0.3	0.5	V
V ₁₄	output voltage at 60 Hz		-	V.	•	v
I ₁₄	sink current active		-	1.	5	mA
I ₁₄	output current inactive (transmitter present)		1-	-	1	μA

Notes to the characteristics

1. Supplying a current of 9 mA to pin 12 starts the horizontal oscillator. This current can be obtained via a bleed circuit from the mains rectifier whilst the main supply for the device (V_w) is obtained from the horizontal output stage. The load current of the driver must be added to the value given.
2. On set AGC
3. The input impedance has been chosen such that a SAW filter can be employed.
4. Measured with 0 dB = 450 µV
5. Measured at 10 mV RMS 100% input signal.
6. Proiected zero point: i.e. with switched demodulator.
7. The output signal amplitude is determined by the AGC detector. For negative modulation the peak sync level is used as reference. With positive modulation the white level is stabilized.
8. Measured according to the test line given in Fig. 3. The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. The differential phase is defined as the difference in degrees between the largest and smallest phase angle. The differential gain and phase are measured with a DSB signal.
9. This figure is valid for the complete video signal amplitude (peak white-to-black). The non-linearity is expressed as a percentage of the maximum deviation of a luminance step from the mean step, with respect to the mean sten
10. The test set-up and input conditions are given in Fig. 5. The figures are measured at an input signal of 10 mV RMS
11. Measured with a source impedance of 75 Ω.

The signal-to-noise ratio = 20 log V_o black-to-white V_arme, at B = 5 MHz

12. By means of the system switch 2 conditions can be obtained. Negative modulation with peak sync level AGC. This is obtained with pin 32 connected to ground. Positive modulation with peak white AGC. This is obtained with pin 32 connected to the positive supply.

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TDA8304

13. When the video switch is in the external mode the first control loop in the synchronization circuit is not switched to a long time constant when weak signals are received.
14. Defined as 20 log V_o unwanted video black-to-white; V_o wanted video-black-to-white; measured at 4.4 MHz.
15. The indicated figures are measured at an input signal of 10 mV RMS. The unloaded Q-factor of the reference tuned circuit is 70. With very weak input signals the drive signal for the AFC circuit will have a high noise content. This noise input has a asymmetrical frequency spectrum which will cause an offset of the AFC output voltage. To avoid problems due to this effect a notch filter can be built into the demodulator tuned circuit. The characteristics given for weak signals are measured without a notch circuit, with a SAW filter connected in front of the IC input signal such that the input signal of the IC is 150 μV (RMS value).
16. Measured at an input signal amplitude of 150 µV(RMS) (pin 21).
17. The minimum value is obtained by connecting a 1.8 kΩ resistor between pins 15 and 28. The slicing level can be varied by changing the value of this resistor (higher resistor value results in larger value of the minimum sync pulse amplitude). The slicing level is independent of the video information.
18. Frequency control is obtained by supplying a correction current to the oscillator RC network via a resistor connected between the phase 1 detector output and the oscillator network. The oscillator can be adjusted to the correct frequency by short circuiting the sync separator bias network (pin 28) to +V_p. To avoid the need of a VCR switch the time constant of the phase detector at strong input signals is sufficiently short to get a stable picture during VCR playback. During the vertical retrace period the time constant is even shorter so that the head-errors of the VCR are compensated at the beginning of scan. During conditions of weak signal (information derived from the AGC circuit) the time constant is increased to obtain a better noise immunity.
19. This figure is valid for an external load impedance of 82 kΩ from pin 31 to the phase adjustment potentiometer (of H-shift).
20. The flyback input and sandcastle output have been combined on one pin. The flyback pulse is clamped to a level of 4.5 V. The minimum current to drive the second control loop is 0.1 mA.
21. The functions in-sync/out-of-sync and transmitter identification have been combined on this pin. The capacitor is charged during the sync pulse and discharged during the time difference between gating (6.5 μs) and the sync pulse in the internal video mode. When the circuit is in the external mode the capacitor is charged by the horizontal sync pulse and discharged continuously with a small current.
22. The vertical scan is synchronized by means of a divider system. Therefore no adjustment is required for the ramp generator. The divider detects whether the incoming signal has a vertical frequency of 50 or 60 Hz and corrects the vertical amplitude.
23. To avoid screen burn due to a collapse of the vertical deflection a continuous blanking level (V₃₀ = 2.5 V) is inserted in the sandcastle pulse when the feedback voltage of the vertical deflection is not within the specified limits.
24. These figures are based on test samples.

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Preliminary specification

Small signal combination IC for colour TV

TDA8304

Sentember 1991

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September 1991

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Preliminary specification

Small signal combination IC for colour TV

TDA8304

September 1991

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TDA8304

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TDA8304

CONDITION PIN 18	CONDITION
VIDEO SWITCH	V ₂₅	T2 - T1	T3 = SCAN
	V ₂₅ > 6.7 V
	and
	strong signal	11.3	7.6
	weak signal	1.3	1.3
Low internal video	V ₂₅ < 6.1 V
	and
	strong signal	11.3	7.6
	weak signal	11.3	7.6
HIGH or
floating	don't care	11.3	7.6
external video

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TDA8304

— 3.3 V 220 KQ 31 2.7 kΩ + zontal drive output 470 n 1.5 kΩ tuner AGC 2 25 41 24 1.2 nf ́ТЕ 10 23 6.8 µF ⊣0∓ 22 12 nal video input video output Fig.9 Application diagram.

September 1991