Datasheet TDA8044_8044A Datasheet

Page 1
INTEGRATED CIRCUITS
DATA SH EET
TDA8044; TDA8044A
Satellite demodulator and decoder
Preliminary specification Supersedes data of 1998 Apr 07 File under Integrated Circuits, IC02
1998 Nov 17
Page 2
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
FEATURES
• General features: – One chip DVB compliant QPSK/BPSK demodulator
and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer
(ETS 300 421) – 3.3 V supply voltage (input pads are 5 V tolerant) – Stand-by mode for low power dissipation – Internal clock PLL to allow low frequency crystal
application and selectable clock frequencies – Power-on reset module – Package: QFP100 – Boundary Scan Test.
• QPSK/BPSK demodulator: – Interpolator and anti-alias filter to handle a large
range of symbol rates without additional external filtering
– On-chip AGC of the analog input I&Q baseband
signals or tuner AGC control. – Two on-chip matched A-D converters (7 bits) – Half Nyquist (square-root raised-cosine) filter with
selectable roll-off factor – Large range of symbol frequencies:
0.5 to 45 Msymbols/s for TDA8044 and
0.5 to 30 Msymbols/s for TDA8044A, including
SCPC (Single Carrier Per Channel) function – Can be used at low channel Signal to Noise Ratio
(SNR) – Internal carrier recovery, clock recovery and AGC
loops with programmable loop filters – Two loop carrier recovery enabling phase tracking of
the incoming symbols – Software carrier sweep for low symbol rate
applications – SNR estimation – External indication of demodulator lock.
• Viterbi decoder: – Rate 1/2 convolutional code based – Constraint length K = 7 with G
G2= 133
Supported puncturing code rates: 1/2,
oct.
= 171
1
oct
and
2/3, 3/4, 4/5, 5/6, 6/7, 7/8, 8/9
– 4 bits input for ‘soft decision’ for both I and Q
– Truncation length: 144 – Automatic synchronisation – Channel BER estimation – External indication of Viterbi sync lock – Differential decoding optional.
• Reed-Solomon decoder: – (204, 188, T = 8) Reed-Solomon code
2
– Automatic (I
C configurable) synchronisation of
bytes, transport packets and frames
– Internal convolutional de-interleaving (I = 12; using
internal memory) – De-randomizer based on PRBS – External indication of RS decoder sync lock – External indication of uncorrectable error; (Transport
Error Indicator is set) – External indication of corrected byte – Indication of the number of lost blocks – Indication of the number of corrected blocks.
• Interface: –I2C-bus interface to initialize and monitor the
demodulator and FEC decoder. When no I2C usage,
default mode is defined – Programmable interrupt facility – Six bits I/O expander for flexible access to and from
the I2C-bus – Switchable I2C loop-through to suppress I2C
crosstalk in the tuner – DiSEqC level 1.X support for dish control applications – 3-state mode for transport stream outputs.
APPLICATIONS
• Digital satellite TV: demodulation and forward error correction (FEC).
Page 3
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
GENERAL DESCRIPTION
This document gives preliminary information about the TDA8044 and TDA8044A, which are the successors of the TDA8043. The TDA8044A is only specified where the product deviates from the TDA8044, all other references are the same. The TDA8044 is backwards compatible with the TDA8043, regarding pinning and I2C software. The TDA8044 is a DVB compliant demodulator and error correction decoder IC for reception of QPSK and BPSK modulated signals for satellite applications. It can handle variable symbol rates in the range of 0.5 to 45 Msymbols/s (0.5 to 30 Msymbols/s for TDA8044A) with a minimum number of low cost and non-critical external components. Typical applications for this device are MCPC (Multi Channel Per Carrier), SCPC (Single Channel Per Carrier) and Simulcast. In these applications one satellite transponder contains respectively one broad QPSK-carrier, several small QPSK-carriers and one small QPSK-carrier together with one or two FM-carriers.
The TDA8044 has minimal interfaces with the tuner, it only requires the demodulated analog I and Q baseband input signals. Analog to digital conversion is done internally by two matched 7-bit A-D converters. Since all the loops (AGC, clock and carrier recovery) are internal, no feedback to the tuner is needed. However for maximal tuner flexibility, there is the possibility to close the AGC and carrier recovery loop externally via the tuner.
The number of external components required for operation of the TDA8044 is very low. Moreover the external components are low cost and non-critical. This gives an easy and low cost application. The TDA8044 runs on a low frequency crystal which is upconverted to a clock frequency by means of an internal PLL. With the PLL different clock frequencies can be selected without changing the crystal. This allows for maximal flexibility concerning symbol rate range combined with minimal power consumption.
Furthermore the TDA8044 has internal anti-alias filters, which can cover a large range of symbol frequencies (approximately one decade) without the need to switch external (SAW) filters. To cover the whole range of
0.5 to 45 Msymbols/s switching of clock frequency
(internally) and filtering (externally) is necessary. The TDA8044 has a double carrier loop configuration
which has excellent capabilities of tracking phase noise. Synchronisation of the FEC-unit is done completely internally, thereby minimizing I The output of the TDA8044 is highly flexible, allowing different output modes to interface to a demultiplexer/descrambler/MPEG-2 decoder including a 3-state mode. For evaluation of the TDA8044, demodulator and Viterbi outputs can be made available externally.
The interfacing of the TDA8044 has been extended compared to the TDA8043. Separate resets are available for logic only, logic plus I2C and carrier loops. A power-on reset module has been implemented which gives a reset signal at power-up. This signal can be used to reset the SDD in order to guarantee correct starting of the IC. Two extra general purpose I/O pins (I/O expanders) have been added. A switchable I2C loop-through to the tuner is implemented to switch off the I2C connection to the tuner. This reduces phase noise in the tuner in case of I2C crosstalk. The transport stream outputs can be put in 3-state mode. Furthermore DiSEqC level 1.X support is integrated for dish control applications. The power consumption in stand-by mode has been decreased considerably.
2
C communication.
Page 4
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD
I
DD
f
clk
f
sym
P
tot
IL implementation loss note 5 − 0.3 − dB SNR SNR for locking the SDD note 5 2 −−dB
functional supply voltage 3.05 3.3 3.55 V total supply current VDD= 3.3 V
TDA8044 note 1 − 320 480 mA TDA8044A notes 1 and 2 −−350 mA
internal clock frequency CFS = 0 or CFS = 1; f
= 4 MHz
xtal
TDA8044 note 1 10.7 − 96 MHz TDA8044A notes 1 and 2 10.7 − 64 MHz
symbol frequency range note 3
TDA8044 0.5 − 45 Msymbols/s TDA8044A 0.5 − 30 Msymbols/s
total power dissipation T
=70°C; note 4
amb
TDA8044 − 1150 1700 mW TDA8044A −−1250 mW
Notes
1. Programmable internal frequencies possible: a) Values 10.7, 16, 32, 64 MHz for CFS = 0. b) Values 16, 24, 48, 96 MHz for CFS = 1.
2. CFS is set to logic 0.
3. Without switching internal clock frequencies, a range of 1 decade can be covered. To cover the full range of symbol frequencies, internal clock frequencies and external (SAW) filters must be switched. Details can be found in the application note.
4. Maximum value is specified for a symbol rate of 45 Msymbols/s, a puncturing rate of 7/8 and a clock frequency of 96 MHz and 3.55 V power supply. Typical value is specified for a symbol rate of 27.5 Msymbols/s, a puncture rate of 3/4 and a clock frequency of 64 MHz.
5. Implementation loss at the demodulator output and minimum SNR to lock the TDA8044 are measured including tuner in a laboratory environment at a symbol rate of 27.5 Msymbols/s and a clock frequency of 64 MHz.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
TDA8044H QFP100 plastic quad flat package; 100 leads (lead length 1.95 mm); TDA8044AH
body 14 × 20 × 2.8 mm
SOT317-2
Page 5
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
PINNING
SYMBOL PIN DESCRIPTION
I2 1 digital I-input bit 2 (ADC bypass) I3 2 digital I-input bit 3 (ADC bypass) V
SSD1
CFS 4 clock frequency selection (remains at logic 0 for TDA8044A) V
SSD2
I4 6 digital I-input bit 4 (ADC bypass) I5 7 digital I-input bit 5 (ADC bypass) I6 8 digital I-input bit 6 (ADC bypass - MSB) Q0 9 digital Q-input bit 0 (ADC bypass - LSB) V
DDD1
Q1 11 digital Q-input bit 1 (ADC bypass) Q2 12 digital Q-input bit2 (ADC bypass) Q3 13 digital Q-input bit3 (ADC bypass) Q4 14 digital Q-input bit4 (ADC bypass) V
SSD3
Q5 16 digital Q-input bit5 (ADC bypass) Q6 17 digital Q-input bit6 (ADC bypass - MSB) V
SSD4
V
DDD2
PRESET 20 set device into default mode P3 21 quasi-bidirectional I/O port (bit 3) P2 22 quasi-bidirectional I/O port (bit 2) P1 23 quasi-bidirectional I/O port (bit 1) P0 24 quasi-bidirectional I/O port (bit 0) V
DDD3
P5 26 quasi-bidirectional I/O port (bit 5) P4 27 quasi-bidirectional I/O port (bit 4) PDOCLK 28 output clock for transport stream bytes PDO0 29 parallel data output (bit 0) PDO1 30 parallel data output (bit 1) PDO2 31 parallel data output (bit 2) V
SSD5
PDO3 33 parallel data output (bit 3) PDO4 34 parallel data output (bit 4) PDO5 35 parallel data output (bit 5) V
SSD6
V
SSD7
PDO6 38 parallel data output (bit 6) POR 39 Power-On Reset (can be connected to PRESET (20)) V
DDD4
3 digital ground 1
5 digital ground 2
10 digital supply voltage 1
15 digital ground 3
18 digital ground 4 19 digital supply voltage 2
25 digital supply voltage 3
32 digital ground 5
36 digital ground 6 37 digital ground 7
40 digital supply voltage 4
Page 6
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
SYMBOL PIN DESCRIPTION
V
DDD5
V
SSD8
V
DDD6
V
DDD7
PDO7 45 parallel data output (bit 7) n.c 46 not connected V
SSD9
PDOERR 48 transport error indicator PDOVAL 49 data valid indicator PDOSYNC 50 transport packet synchronization signal V
SSD10
SCL 52 serial clock of I SDA 53 serial data of I INT 54 interrupt output (active LOW) A0 55 I RSLOCK 56 Reed-Solomon lock indicator VLOCK 57 Viterbi lock indicator DLOCK 58 Demodulator lock indicator V
DDD8
V
DDD9
TEST 61 test pin (normally connected to ground) TRST 62 BST optional asynchronous reset (normally connected to ground) TCK 63 BST dedicated test clock (normally connected to ground) SCLT 64 serial clock of I SDAT 65 serial data of I V
DDD10
V
SSD11
V
SSD12
TMS 69 BST input control signal (normally connected to ground) TDO 70 BST serial test data out TDI 71 BST serial test data in (normally connected to ground) V
DDD11
V
SSD13
V
SSD(AD)
V
DDD(AD)
V
) 76 bottom reference voltage for ADC
ref(B
V
SSA1
QA 78 analog input Q V
ref(Q)
IA 80 analog input I V
SSA2
41 digital supply voltage 5 42 digital ground 8 43 digital supply voltage 6 44 digital supply voltage 7
47 digital ground 9
51 digital ground 10
2
C-bus
2
C-bus
2
C hardware address
59 digital supply voltage 8 60 digital supply voltage 9
2
C-bus loop-through
2
C-bus loop-through 66 digital supply voltage 10 67 digital ground 11 68 digital ground 12
72 digital supply voltage 11 73 digital ground 13 74 digital ground A/D converter 75 digital supply A/D converter
77 analog ground 1
79 AGC decoupling - Q path
81 analog ground 2
Page 7
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
SYMBOL PIN DESCRIPTION
V
ref(I)
V
DDA
V
DDXTAL
XTALI 85 crystal oscillator input XTALO 86 crystal oscillator output V
SSXTAL
V
DDD12
V
DDD13
V
SSD14
D22 91 22 kHz output for dish control applications V
SSD15
V
SSD16
V
AGC
V
SSD(test)
V
DDD14
V
DDD15
OUSTD 98 general purpose sigma-delta output I0 99 digital I-input bit0 (ADC bypass - LSB) I1 100 digital I-input bit 1 (ADC bypass)
82 AGC decoupling - I path 83 analog supply voltage 84 supply voltage for crystal oscillator
87 ground for crystal oscillator 88 digital supply voltage 12 89 digital supply voltage 13 90 digital ground 14
92 digital ground 15 93 digital ground 16 94 AGC output voltage 95 Test pin, normally connected to ground 96 digital supply voltage 14 97 digital supply voltage 15
Page 8
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
handbook, full pagewidth
V
SSD1
CFS
V
SSD2
Q0
V
DDD1
Q1 Q2 Q3 Q4
V
SSD2
Q5 Q6
V
SSD3
V
DDD2
PRESET
P3 P2 P1 P0
V
DDD3
P5 P4
PDOCLK
PDO0 PDO1
I1I0OUTSD 100
1
I2
2
I3
3 4 5 6
I4
7
I5
8
I6
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DDD15VDDD14VSSD(test)VSSD16VSSD15
V
99989796959493929190898887868584838281
AGC
V
SSD10VDDD13VDDD12VSSXTAL
D22
V
TDA8044
TDA8044A
XTALO
XTALI
DDXTALVDDAVref(I)VSSA2
V
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
IA V
ref(Q) QA V
SSA1 V
ref(B) V
DDD(AD) V
SSD(AD) V
SSD9 V
DDD11 TDI
TDO TMS V
SSD8 V
SSD7 V
DDD10 SDAT
SCLT TCK TRST TEST V
DDD9 V
DDD8 DLOCK
VLOCK RSLOCK A0 INT SDA SCL V
SSD6
31323334353637383940414243444546474849
SSD4
PDO2
PDO3
V
For compatibility in respect to the TDA8043 see Section “Pin compatibility”.
PDO4
PDO5
V
SSD6VSSD7
PDO6
POR
Fig.1 Pin configuration.
DDD4VDDD5
V
SSD5
V
DDD6VDDD7
V
PDO7
n.c.
SSD9
V
PDOVAL
PDOERR
50
MGM606
PDOSYNC
Page 9
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
Pin compatibility
The TDA8044 is backwards pin compatible with the TDA8043, this means that the functional pins of the TDA8043 have been left unchanged on the TDA8044. However due to extra functionality of the TDA8044, some of the not connected pins of the TDA8043 will become functional pins on the TDA8044. The following table lists the modified pins of the TDA8044.
Table 1 Modified pins of the TDA8044
PIN TDA8043 FUNCTION TDA8043 SYMBOL TDA8044 FUNCTION
4 not connected CFS clock frequency selection 5 not connected V
SSD2
26 not connected P4 I/O expander bit 4 27 not connected P5 I/O expander bit 5 36 not connected V 37 not connected V
SSD6 SSD7
39 not connected POR power-on reset 47 not connected V
SSD9
64 not connected SCLT serial clock of I 65 not connected SDAT serial data of I 91 not connected D22 22 kHz generation output 92 not connected V 93 not connected V 95 not connected V
SSD15 SSD16 SSD(test)
digital ground
digital ground digital ground
digital ground
2
C-bus loop-through
2
C-bus loop-through
digital ground digital ground test pin, connect to ground
If you want to replace the TDA8043 with the TDA8044 and you do not want to use the pins with extra functionality, then the following measures on the PCB layout must be taken to avoid I/O conflicts in the TDA8044:
• pin numbers 4, 5, 26, 27, 36, 37, 47, 65, 92, 93 and 95 must be put to ground
• pin numbers 39, 64 and 91 must be left not connected.
With this measures it is possible to use the TDA8043 and the TDA8044 on the same PCB without any problems. In order to use pins with the extra functionality of the TDA8044, PCB-layout changes are necessary.
Page 10
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD
V
max
P
tot
T
stg
T
amb
T
j
Notes
Maximum power dissipation is specified for 96 MHz clock frequency, 45 Msymbols/s and puncture rate of 7/8.
1.
2. Maximum power dissipation is specified for 64 MHz clock frequency, 30 Msymbols/s and puncture rate of 7/8.
supply voltage pins −0.3 3.55 V voltage on all pins 0 V
DD
V
total power dissipation
TDA8044 T TDA8044A T
=70°C; note 1 − 1700 mW
amb
=70°C; note 2 − 1250 mW
amb
IC storage temperature −55 150 °C operating ambient temperature T
=70°C070°C
amb
operating junction temperature 0 125 °C
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air
TDA8044 34 K/W TDA8044A 45 K/W
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see
“Handling MOS devices”
).
1998 Nov 17 10
Page 11
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
APPLICATION INFORMATION
handbook, full pagewidth
RF-in
TDA8060
TSA5056
TUNER
smart card(s)
telco i/f
I
TDA8044
TDA8044A
Q
2
I
C-bus
MODEM
TDA8004
FRONT
PANEL
CONTROL
SDD
Vxx
2
C-bus
I
SAA7214
TMIPS
FLASH
AV
PES
16-Mbit
SDRAM
SAA7215
DRAM
(optional)
16-Mbit
SDRAM
(optional)
1394
L + PHY
BUFFERS
RGB CVBS/YC LR
ADAC
IEEE1394
IEEE1284 RS232
SWITCHING
SCART 1
SCART 2
SCART 3
MGM605
Fig.2 Satellite set-top decoder concept.
1998 Nov 17 11
Page 12
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
handbook, full pagewidth
+3.3 V
V
V
V
V
DDD
DDD1
100 nF
470 kΩ
DDD1
DDD1
packet data
and control
outputs
(1)
L
(1)
L
V
DDD2
(3)
C
(3)
C
(3)
C
PDOCLK
PDO0 PDO1
15 µF
15 µF
CFS
V
DDD1
V
DDD2
C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P3
21
P2
22
P1
23
P0
24 25
P5
26
P4
27 28 29
tuner AGC (optional)
470 Ω10 kΩ
+ 5 V
330 nF
(3)
V
SD
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100
V
DDD2
22 kHz
(3)
C
27 pF
27
pF
(2)
XTAL
V
DDA
C
TDA8044
TDA8044A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(3)
V
n.c.
PDOVAL
DDD1
POR
PDO5
PDO3PDO2
PDO4
PDO6 PDO7 PDOERR PDOSYNC
C
V
DDD1
packet data and control outputs
10 Ω
+3.3 V
10 nF
(3)
100 nF
100 nF
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 5130
+3.3 V
100 nF
100 nF
TDI
TMS
I2C-bus to tuner
lock signals
TDO
4.7 kΩ
I
100 nF
Q
V
DDD2
(3)
C
V
DDD2
(3)
C
V
DDD2
(3)
C
V
DDD1
(3)
C
+5 V
4.7
1.6
kΩ
kΩ
interrupt
2
I
C-bus
input
V
(1)
L
DDA
15 µF
MGM607
(1) B = SMD bead type C8D8.9/3/3 Grade 4S2. (2) f
= 4 MHz (fundamental).
xtal
(3) C = 6.8 nF, SMD.
Fig.3 Application diagram.
1998 Nov 17 12
Page 13
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
c
y
X
E
e
w M
p
A
A
H
E
E
2
A
A
1
80 51
81
pin 1 index
100
1
50
Z
b
31
30
detail X
SOT317-2
L
p
L
(A )
3
θ
w M
b
e
p
Z
D
D
H
D
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT A1A2A3b
max.
0.25
mm
3.20
0.05
2.90
2.65
0.25
cE
p
0.40
0.25
0.25
0.14
(1)
(1) (1)(1)
D
20.1
19.9
eH
14.1
13.9
0.65
24.2
23.6
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE VERSION
IEC JEDEC EIAJ
REFERENCES
SOT317-2
1998 Nov 17 13
v M
A
B
v M
B
E
18.2
17.6
LL
p
1.0
0.6
0.15 0.10.21.95
H
D
EUROPEAN
PROJECTION
Z
D
0.8
0.4
Zywv θ
E
o
1.0
7
o
0.6
0
ISSUE DATE
95-02-04 97-08-01
Page 14
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
SOLDERING Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used.
Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C.
• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Manual soldering
Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
If wave soldering is used the following conditions must be observed for optimal results:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
1998 Nov 17 14
Page 15
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
Suitability of surface mount IC packages for wave and reflow soldering methods
PACKAGE
WAVE REFLOW
HLQFP, HSQFP, HSOP, SMS not suitable
(3)
PLCC
, SO suitable suitable
(2)
LQFP, QFP, TQFP not recommended
(3)(4)
suitable
suitable
(1)
SQFP not suitable suitable
SOLDERING METHOD
SSOP, TSSOP, VSO not recommended
(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1998 Nov 17 15
Page 16
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
PURCHASE OF PHILIPS I
2
C COMPONENTS
Purchase of Philips I components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2
C components conveys a license under the Philips’ I2C patent to use the
1998 Nov 17 16
Page 17
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
NOTES
1998 Nov 17 17
Page 18
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
NOTES
1998 Nov 17 18
Page 19
Philips Semiconductors Preliminary specification
Satellite demodulator and decoder TDA8044; TDA8044A
NOTES
1998 Nov 17 19
Page 20
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© Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 545104/750/02/pp20 Date of release: 1998 Nov 17 Document order number: 9397 750 04777
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