Page 1
INTEGRATED CIRCUITS
DATA SH EET
TDA8041H
Quadrature demodulator controller
Preliminary specification
File under Integrated Circuits, IC03
Philips Semiconductors
November 1994
Page 2
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
FEATURES
• Generates all control signals for Quadrature Phase-Shift
Keying (QPSK) and Binary Phase-Shift Keying (BPSK)
APPLICATIONS
• Demodulation of BPSK and QPSK modulated signals in
satellite and telephone applications.
demodulation
• Can be used in applications with low Eb/No and high
symbol rate (up to 30 × 106 symbols/s)
• Digital I and Q outputs (3 bits) for soft decision within
error correction
• Two matched analog-to-digital converters to quantize
the I and Q signals
• A digital detector for each control loop to generate the
required control signals
• Digital-to-analog converters and operational amplifiers
to allow high flexibility for loop time constants
• Special input stage to interface with the voltage
controlled crystal oscillator
• Positive 5 V supply voltage.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
DD(A)
supply voltage for operational
4.75 5.0 5.25 V
amplifiers (pin 5)
V
DDA(C)
analog supply voltage for
4.75 5.0 5.25 V
converters (pin 20)
V
DD(I/O)
supply voltage for digital
4.75 5.0 5.25 V
inputs/outputs (pin 30)
V
DDD
supply voltage for digital
4.75 5.0 5.25 V
section (pin 35)
V
DD(C)
supply voltage for digital part
4.75 5.0 5.25 V
of ADC and DAC (pin 42)
I
DD(tot)
V
IQ
R
sym
I
O(DAC)
total supply current VDD=5 V − 30 − mA
I and Q input voltage − 1.0 − V
symbol rate −−30 × 106symbols/s
DAC output current −100 − +100 mA
ORDERING INFORMATION
TYPE NUMBER
TDA8041H QFP44
Note
1. When using reflow soldering it is recommended that the Drypack instructions in the
(order number 9398 510 63011) are followed.
November 1994 2
PACKAGE
NAME DESCRIPTION VERSION
plastic quad flat package; 44 leads (lead length 1.3 mm);
(1)
body 10 × 10 × 1.75 mm; high stand-off height
SOT307-2
“Quality Reference Handbook”
Page 3
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
BLOCK DIAGRAM
2
LCKO
44 1
LCKDAC LCKTC
handbook, full pagewidth
IDO0 to IDO2
31 to 33
ref(mid)
CLK1
3
ADC
CLKSR
25
2
CLK2
DAC
CLK1
OPAMP
MBE167
43
V
42
35
V
34
30
V
29
24
V
20
17
V
11
6
V
26 to 28 5
QDO0 to QDO2
SS(C)
DD(C)
V
DDD
SSD
V
DD(I/O)
SS(I/O)
V
SS1
DDA(C)
V
SSA(C)
SS2
V
SS(A)
DD(A)
V
Fig.1 Block diagram.
CLKIX
CLKRO
ref(mid)
V
CLK1
CLKRTC
21
CLK
I
5
CLK
data
CLOCK
4
22
23
V
DAC
CLK1
RECOVERY
Q (3..0)
LOGIC
AGCO
CLK1
AGCTC
12
AGC
I
13
DAC
2
AGC
data
AGC
AFC2O
SWPO
ref(mid)
V
CLK1
SWEEP
39
14
th
V
LOGIC
10
AFC2
I
5
AFC2
data
DAC
AFC2
CARO
CARTC
LCKTH
LCKIO
3
4
LCK
I
DAC
4
LCK
data
LOCK
I (3..0)
4
3
LOGIC
15
ref(mid)
V
CLK1
DETECTOR
16
CAR
I
DAC
4
CAR
data
CARRIER
RECOVERY
TDA8041H
4
A
4
A
I
bias
biasIbias
I
CLK2
November 1994 3
18
ADC
ana
I
V
DD
R4
7
ref(pos)
V
R3
8
ref(mid)
V
R2
9
ref(neg)
V
R1
SS
V
383637
BQN
AFC1
mode
40
AFC2
TEST
control
19
ADC
ana
Q
CLK2
BIAS
GENERATOR
41
bias
I
Page 4
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
PINNING
SYMBOL PIN DESCRIPTION
LCKTC 1 carrier lock time constant
LCKO 2 carrier lock output
LCKTH 3 carrier lock threshold voltage
LCKIO 4 carrier lock indicator output
V
DD(A)
5 supply voltage for operational
amplifiers
V
SS(A)
6 negative supply voltage for
operational amplifiers
V
ref(pos)
7 positive reference voltage for
converters
V
ref(mid)
8 middle reference voltage for
converters
V
ref(neg)
9 negative reference voltage for
converters
AFC2O 10 AFC 2 output
V
SS2
11 negative supply voltage 2
AGCTC 12 automatic gain control time
constant
AGCO 13 automatic gain control output
SWPO 14 sweep current output
CARTC 15 carrier recovery time constant
CARO 16 carrier recovery output
V
SSA(C)
17 analog negative supply voltage for
converters
I
ana
Q
ana
V
DDA(C)
18 analog input I
19 analog input Q
20 analog supply voltage for
converters
CLKRTC 21 clock recovery time constant
CLKRO 22 clock recovery output
CLKIX 23 clock input from crystal circuit
(at double symbol rate)
SYMBOL PIN DESCRIPTION
V
SS1
24 negative supply voltage 1
CLKSR 25 clock output at symbol rate
QDO2 26 Q digital output (bit 2)
QDO1 27 Q digital output (bit 1)
QDO0 28 Q digital output (bit 0)
V
SS(I/O)
29 negative supply voltage for digital
inputs/outputs
V
DD(I/O)
30 supply voltage for digital
inputs/outputs
IDO2 31 I digital output (bit 2)
IDO1 32 I digital output (bit 1)
IDO0 33 I digital output (bit 0)
V
SSD
34 negative supply voltage for digital
section
V
DDD
35 supply voltage for digital section
AFC1 36 AFC control switch 1 (1 = on;
0=off)
AFC2 37 AFC control switch 2 (1 = on;
0=off)
BQN 38 BPSK/QPSK control switch
(1 = BPSK; 0 = QPSK)
SWEEP 39 sweep control switch (1 = on;
0=off)
TEST 40 test control switch (1 = on; 0 = off)
I
bias
V
DD(C)
41 input bias current for analog blocks
42 supply voltage for digital part of
ADC and DAC
V
SS(C)
43 negative supply voltage for digital
part of ADC and DAC
LCKDAC 44 carrier lock DAC output
November 1994 4
Page 5
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
handbook, full pagewidth
LCKTC
LCKO
LCKTH
LCKIO
V
DD(A)
V
SS(A)
V
ref(pos)
V
ref(mid)
V
ref(neg)
AFC2O
V
SS2
DD(C)
SS(C)
bias
V
V
43
13
AGCO
I
42
14
SWPO
41
TDA8041H
15
CARTC
LCKDAC
44
1
2
3
4
5
6
7
8
9
10
11
12
AGCTC
TEST
40
16
CARO
BQN
SWEEP
39
38
17
18
ana
I
SSA(C)
V
Q
AFC2
37
19
ana
V
AFC1
36
20
DDA(C)
V
DDD
V
35
34
21
22
CLKRO
CLKRTC
33
32
31
30
29
28
27
26
25
24
23
IDO0
IDO1
IDO2
V
DD(I/O)
V
SS(I/O)
QDO0
QDO1
QDO2
CLKSR
V
SS1
CLKIX
MBE166
SSD
Fig.2 Pin configuration.
November 1994 5
Page 6
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
GENERAL DESCRIPTION
The quadrature demodulator controller TDA8041H,
generates all control signals required for demodulation of
BPSK and QPSK modulated signals. This device is
specially designed to be used in conjunction with the
quadrature demodulator IC, TDA8040T.
The quadrature demodulator controller generates the
following signals:
• Symbol clock recovery control signal; this signal locks
the VCXO to the received symbol clock. The clock
recovery algorithm used in this device operates
independently from the other loops.
• Carrier recovery control signal; depending on the
selected mode (BPSK or QPSK), this signal will adjust
the phase of the I and Q input signal. This adjustment
will be such that the constellation points are as defined
in Fig.4.
• Frequency control signals (AFC1 and AFC2); to serve a
broad range of applications, two different AFC detectors
and a sweep function are built-in:
– AFC1: this is a robust detector which forces the offset
frequency in the I and Q branch to zero. This detector
can handle frequency offset up to 1/8 × symbol rate.
– AFC2: this detector can handle frequency offsets
greater than 1/8 × symbol frequency. However this
AFC algorithm will bring the offset frequency only
close to zero.
– Sweep: this signal generates a triangular current
output which can tune a VCO over its complete
frequency range. Sweeping must be switched off as
soon as the logical output of the lock detect function
becomes positive. The value of the sweep current is
set by an external resistor.
• Amplitude control signals (AGC); this signal adjusts a
variable gain amplifier so that the amplitude of the I and
Q signals is in accordance with the specified
constellation points of Fig.4.
• Lock detect signal; this signal is related to the E
the incoming I and Q signals. This lock detect signal can
be used for two purposes:
– Lock detection by comparing the lock detect signal
with an external set reference voltage, one can obtain
a logical signal indicating lock detect.
– The relationship between Eb/No can be used to
display the Eb/No for antenna adjustment.
b/No
of
FUNCTIONAL DESCRIPTION
The TDA8041H has a 3-bit-wide digital I and Q output for
soft error correction. These 3-bit outputs represent the
main symbols only. The relationship between the 4-bits
ADC signals and the 3-bit output signals is illustrated in
Fig.3.
Fig.3 I and Q output levels for soft error
decision FEC.
November 1994 6
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Philips Semiconductors Preliminary specification
B
B
B
BB
BB
Quadrature demodulator controller TDA8041H
B
Fig.4 Constellation points.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DD(A)
V
DDA(C)
V
DD(I/O)
V
DDD
V
DD(C)
V
n(max)
P
tot
T
stg
T
j
T
amb
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-a
supply voltage for operational amplifiers (pin 5) −0.5 +6.5 V
analog supply voltage for converters (pin 20) −0.5 +6.5 V
supply voltage for digital inputs/outputs (pin 30) −0.5 +6.5 V
supply voltage for digital section (pin 35) −0.5 +6.5 V
supply voltage for digital part of ADC and DAC (pin 42) −0.5 +6.5 V
maximum voltage on all pins 0 V
total power dissipation T
storage temperature −55 +150 °C
junction temperature − +150 °C
operating ambient temperature 0 +70 °C
thermal resistance from junction to ambient in free air 75 K/W
=70°C − 500 mW
amb
DD
V
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
November 1994 7
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Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
CHARACTERISTICS
= 4.75 to 5.25 V; R
V
DD
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Digital outputs (pins 26 to 28 and 31 to 33)
V
OL
V
OH
t
d
t
h
LOW level output voltage 0 − 0.1V
HIGH level output voltage see Fig.6 0.9V
delay time see Fig.6 t
hold time 8 − t
Digital inputs
V
IL
V
IH
C
I
LOW level input voltage 0 − 0.3V
HIGH level input voltage 0.7V
input capacitance −−10 pF
Clock output (pins 22 and 25); see Fig.5
V
OL
V
OH
T
cy
t
W
t
r
t
f
LOW level output voltage 0 − 0.1V
HIGH level output voltage 0.9V
cycle time 33 −−ns
pulse width duty cycle 40/60 13.2 −−ns
rise time CL=30pF −−6ns
fall time CL=30pF −−6ns
Clock input (pin 23)
R
f
s
source
source resistance −−50 Ω
sampling frequency −−60 MHz
Analog inputs (pins 18 and 19)
R
sym
V
ref(pos)
V
ref(mid)
V
ref(neg)
I
L
V
i(I,Q)
V
I,Q(op)
R
I
C
I
I
bias
symbol rate −−30 × 106symbols/s
positive reference voltage IO=0 − 0.48V
middle reference voltage IO= 0 − 0.38V
negative reference voltage IO= 0 − 0.28V
load current at pin 8 note 1 −5 − +5 mA
I and Q input voltage 0 − V
I and Q operating voltage 0.28V
input resistance 50 −−kΩ
input capacitance −−20 pF
input bias current RL= 100 kΩ−−37 − mA
DAC outputs (pins 10, 12, 15 and 21)
I
o(av)
D
Io
average output current V
matching of positive and
negative output currents
I
o
zero output current −25 − +25 nA
=30×106 symbols/s; T
sym
=25°C; unless otherwise specified.
amb
DAC=Vref(mid)
V
DAC=Vref(mid)
V
DD
DD
h
DD
DD
− V
− 22 ns
− V
− V
DD
DD
DD
− 0.48V
DD
DD
d
DD
DD
− V
− V
− V
DD
DD
DD
DD
V
ns
V
V
V
V
V
V
; note 2 − 100 − mA
; note 2 −7 − +7 %
November 1994 8
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Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Sweep current (pin 14)
V
OH
V
OL
Z
O
V
CARO(min)
V
CARO(max)
Loop amplifiers
V
o
G
v
G
B
R
L
Notes
1. V
is usually open-circuit. However, this pin may also be used as a reference output for an external buffer.
ref(mid)
HIGH level output voltage − 2V
ref(mid)
LOW level output voltage − 0 − V
output impedance SWEEP = 1 − 2 − kΩ
SWEEP = 0 10 −−MΩ
LOW switching level 0.1V
HIGH switching level 0.8V
output voltage 0.1V
DD
DD
DD
− 0.2V
− 0.9V
− 0.9V
open loop gain −.60−dB
gain bandwidth − 1 − MHz
load resistance 5 −−kΩ
− V
DD
DD
DD
V
V
V
I
–()
2. ;
I
oav()
posIneg
= D
-------------------------------2
I
+()
100
lo
posIneg
×=
-------------------------------- I
–()
posIneg
November 1994 9
Page 10
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
Fig.5 Timing of CLKO.
November 1994 10
Fig.6 Timing definition of digital outputs.
Page 11
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
APPLICATION INFORMATION
10
560
56
nF
Ω
pF
5 V
5 V
10
nF
BFS17A
10
56
kΩ
100 pF
0 Ω
pF
390 nH
Ω
50
10 Ω
kΩ
4.7
5 V
book, full pagewidth
5 V
100 nF
kΩ
100
100 nF
44 43 42 41 40 39 38 37 36 35 34
22
33
SSD
V
LCKDAC
1
kΩ
I0
32
IDO0
DDD
V
AF C1
AF C2
BQN
SWEEP
TEST
bias
I
DD(C)
V
SS(C)
V
LCKTC
2
I1
IDO1
LCKO
I2
31
IDO2
LCKTH
3
30
DD(I/O)
V
LCKIO
4
100 nF
29
SS(I/O)
V
DD(A)
V
5
Q0
Q1
27
28
QDO1
QDO0
TDA8041H
SS(A)
ref(pos)
V
V
6
7
Q2
26
QDO2
ref(mid)
V
8
clock output
24
25
SS1
CLKSR
V
ref(neg)
V
AFC2O
9
10
23
CLKIX
SS2
V
11
CLKRO
CLKRTC
DDA(C)
V
ana
Q
ana
I
SSA(C)
V
CARO
CARTC
SWPO
AGCO
AGCTC
49.7 MHz
BB620
27
kΩ
pF
100
10
nF
82
kΩ
5 V
nF
100
pF
330
pF
330
Q from TDA8040
I from TDA8040
1
10
nF
kΩ
MBE168
Fig.7 Application diagram.
820
kΩ
12 13 14 15 16 17 18 19 20 21 22
100 Ω
100 nF
270
pF
22
56
5 V
33
kΩ
5 V
10
November 1994 11
100 nF
100 nF
AFC2 current
AGC voltage
carrier voltage
kΩ
nF
8.2
100 nF
kΩ
lock indicator
nF
33
nF
kΩ
100
10
kΩ
100 nF
5 V
Page 12
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
PACKAGE OUTLINE
seating
plane
0.15 S
12.9
12.3
44
1
pin 1 index
11
12
34
22
S
1.2
(4x)
0.8
33
0.8
0.40
0.20
23
B
10.1
9.9
12.9
12.3
B
0.15 M
1.2
0.50
0.20
0.8
(4x)
A
detail X
0.95
0.55
0.85
0.75
X
0.25
0.14
0 to 10
2.35
1.85
o
Dimensions in mm.
0.8
0.40
0.20
10.1
9.9
0.15 M A
1.85
1.65
MBC864 - 2
Fig.8 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm; high stand-off height
(QFP44; SOT307-1).
November 1994 12
Page 13
Philips Semiconductors Preliminary specification
Quadrature demodulator controller TDA8041H
SOLDERING
Plastic quad flat-packs
YWAVE
B
During placement and before soldering, the component
must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.
A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.
Y SOLDER PASTE REFLOW
B
Reflow soldering requires the solder paste (a suspension
of fine solder particles, flux and binding agent) to be
applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.
EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
R
IRON OR PULSE
-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)
For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
November 1994 13
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