Page 1
Features
■ Input multiplexer
– Two stereo and one mono inputs
– One quasi differential input
– Selectable input gain for optimal adaptation
to different sources
■ Fully programmable loudness function
■ Volume control in 0.3dB steps including gain
up to 20dB
■ Zero crossing mute, soft mute and direct mute
■ Bass and treble control
■ Four speaker attenuators
– Four independent speakers control in
1.25dB steps for balance and fader facilities
– Independent mute function
■ All functions programmable via serial I
2
C bus
Description
The audioprocessor TDA7342EQ2N is an
upgrade of the TDA731X audioprocessor family.
TDA7342EQ2N
Digitally controlled audio processor
TQFP32
Due to a highly linear signal processing, using
CMOS-switching techniques instead of standard
bipolar multipliers, very low distortion and very
low noise are obtained. Several new features like
softmute, and zero-crossing mute are
implemented. The soft Mute function can be
activated in two ways:
1. Via serial bus (Mute byte, bit D0)
2. Directly on pin 21 through an I/O line of the
microcontroller
Very low DC stepping is obtained by use of a
BICMOS technology.
Order codes
Part number Package Packing
TDA7342EQ2N TQFP32 Tray
TDA7342EQ2NTR TQFP32 Tape and reel
August 2006 Rev 1 1/21
www.st.com
1
Page 2
Contents TDA7342EQ2N
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Pns description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Data Validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Start and Stop Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5 Transmission without Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Auto increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Transmitted data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
Page 3
TDA7342EQ2N List of tables
List of tables
Table 1. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. SUBADDRESS (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Send mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Input selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 9. Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 10. Speaker attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. Bass/Treble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3/21
Page 4
List of figures TDA7342EQ2N
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connection (Top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Data Validity on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Timing Diagram of I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Acknowledge on the I2C BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. TQFP32 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4/21
Page 5
TDA7342EQ2N Block diagram
1 Block diagram
Figure 1. Block diagram
BUS
+Vcc
R2
C17 2.7nF
4.7K
100nF 100nF
C9
C14 C15
C11
TREBLE(L)
47nF
BOUT(L) BIN(L)
LOUD(L)
OUT(L) IN(L)
32
18 17
9
16 15
ATT
SPKR
OUT
LEFT FRONT
24
MUTE
TREBLE
BASS
VOL
LOUD+
ZERO
CROSS +
ATT
SPKR
MUTE
OUT
22
SCL
LEFT REAR
SDA
DIGGND
ADDR
292726
25
MUTE
SPKR
SERIAL BUS DECODER + LATCHES
SOFT
MUTE
ATT
OUT
RIGHT FRONT
23
MUTE
LOUD+
ZERO
CROSS +
TREBLE
BASS
VOL
MUTE
ATT
SPKR
OUT
RIGHT REAR
21
D93AU043B
MUTE
C16
TREBLE(R)
C12 C13
BOUT(R) BIN(R)
20 19 1
SM
C
CSMOUT(R)CREF
C10
LOUD(R)
2 4
IN(R)
314
2.7nF
100nF100nF
R1 4.7K
47nF
47nF
C8
INPUT
+ GAIN
SELECTOR
L1
13
L1
C1
LEFT
L2
12
L2
INPUTS
L3
M
11
L3
C2
C6
10
SGND
CD
R3
5
R3
C3
C7
M
R2
8
6
M
R2
MONO INPUT
R1
7
R1
C4
RIGHT
INPUTS
C5
SUPPLY
10µF
30 31 28
S
V
5/21
Page 6
Pns description TDA7342EQ2N
2 Pns description
Figure 2. Pin connection (Top view)
S
TR L
GND
ADDR
CREF
SCL
SDA
DIG GND
24
23
22
21
20
19
18
17
OUT LF
OUT RF
OUT LR
OUT RR
BOUT R
BIN R
BOUT L
BIN L
TR R
IN R
OUT R
LOUD R
IN R3
IN R2
IN R1
MONO
V
323031 29 28 27 26 25
1
2
3
4
5
6
7
8
910
11 12 13 14 15 16
LOUD L
CD GND
IN L3
IN L2
IN L1
CSM
IN L
OUT L
D94AU060A
6/21
Page 7
TDA7342EQ2N Electrical specifications
3 Electrical specifications
3.1 Absolute maximum ratings
Table 1. Absolute Maximum Ratings
Symbol Parameter Value Unit
V
Operating Supply Voltage 10.5 V
S
T
amb
T
3.2 Quick reference data
Table 2. Quick reference data
Symbol Parameter Min. Typ. Max. Unit
V
V
THD Total Harmonic Distortion V = 1Vrms f = 1KHz 0.01 0.08 %
S/N Signal to Noise Ratio 106 dB
Operating Ambient Temperature -40 to 85 °C
Storage Temperature Range -55 to 150 °C
stg
Supply Voltage 6 9 10.2 V
S
Max. input signal handling 2.1 2.6 Vrms
CL
Channel Separation 100 dB
S
C
Volume Control 0.3dB step -59.7 20 dB
Treble Control 2dB step -14 +14 dB
Bass Control 2dB step -10 +18 dB
Fader and Balance Control 1.25dB step -38.75 0 dB
Input Gain 3.75dB step 0 11.25 dB
Mute Attenuation 100 dB
3.3 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
th j-amb
Thermal Resistance Junction-pins 150 °C/W
7/21
Page 8
Electrical specifications TDA7342EQ2N
3.4 Electrical characteristics
Table 4. Electrical characteristics
(V
= 9V; RL = 10KΩ; Rg = 50Ω; T
S
= 25°C; all gains = 0dB; f = 1KHz. Refer to the test
amb
circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
INPUT SELECTOR
R
Input Resistance 70 100 130 KΩ
I
Clipping Level d ≤ 0.3% 2.1 2.6 V
V
CL
S
Input Separation 80 100 dB
I
Output Load Resistance 2 KΩ
R
L
Minimum Input Gain -0.75 0 0.75 dB
G
I MIN
G
Maximum Input Gain 10.25 11.25 12.25 dB
I MAX
Step Resolution 2.75 3.75 4.75 dB
G
step
e
Input Noise 20Hz to 20 KHz unweighted 2.3 µV
N
V
DC
DC Steps
DIFFERENTIAL INPUT ( IN 3)
R
Input Resistance
I
CMRR Common Mode Rejection Ratio
d Distortion VI= 1V
e
Input Noise 20Hz to 20KHz; Flat; D6 = 0 5 µV
IN
G
Differential Gain
DIFF
Adiacent Gain Steps 1.5 10 mV
G
IIN
to G
3 mV
IMAX
Input selector BIT D6 = 0 (0dB) 10 15 20 KΩ
Input selector BIT D6 = 1(-6dB) 14 20 30 KΩ
V
CM
= 1V
; f =1KHz 48 75 dB
RMS
f = 10KHz 45 70 dB
RMS
0.01 0.08 %
D6 = 0 -1 0 1 dB
D6 = 1 -7 -6 -5 dB
RMS
VOLUME CONTROL
Input Resistance 35 50 KΩ
R
I
G
Maximum Gain 18.75 20 21.25 dB
MAX
A
A
STEPC
A
STEPF
Maximum Attenuation 57.7 59.7 62.7 dB
MAX
Step Resolution Coarse Atten. 0.5 1.25 2.0 dB
Step Resolution Fine Attenuation 0.11 0.31 0.51 dB
G = 20 to -20dB -1.25 0 1.25 dB
E
Attenuation Set Error
A
E
Tracking Error 2 dB
t
G = -20 to -58dB -3 2 dB
Adiacent Attenuation Steps -3 0 3 mV
V
DC Steps
DC
From 0dB to A
0.5 5 mV
MAX
8/21
Page 9
TDA7342EQ2N Electrical specifications
Table 4. Electrical characteristics (continued)
(V
= 9V; RL = 10KΩ; Rg = 50Ω; T
S
= 25°C; all gains = 0dB; f = 1KHz. Refer to the test
amb
circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
LOUDNESS CONTROL
RI Internal Resistor Loud = On 35 50 65 KΩ
A
A
Maximum Attenuation 17.5 18.75 20.0 dB
MAX
Step Resolution 0.5 1.25 2.0 dB
step
ZERO CROSSING MUTE
WIN = 11 20 mV
V
Zero Crossing Threshold
TH
(1)
WIN = 10 40 mV
WIN = 01 80 mV
WIN = 00 160 mV
A
MUTE
V
Mute Attenuation 80 100 dB
DC Step 0dB to Mute 0 3 mV
DC
SOFT MUTE
A
Mute Attenuation 45 60 dB
MUTE
C
T
ON Delay Time
DON
I
OFF Current
DOFF
V
THSM
Soft Mute Threshold (pin 14) 1.5 2.5 3.5 V
= 22nF; 0 to -20dB; I = I
CSM
= 22nF; 0 to -20dB; I = I
C
CSM
V
= 0V; I = I
V
CSM
CSM
= 0V; I = I
MAX
MIN
0.7 1 1.7 ms
MAX
20 35 55 ms
MIN
25 50 75 µA
1 µA
BASS CONTROL
B
BOOST
B
A
Max Bass Boost 15 18 20 dB
Max Bass Cut -8.5 -10 -11.5 dB
CUT
Step Resolution 1 2 3 dB
step
R
Internal Feedback Resistance 45 65 85 KΩ
g
TREBLE CONTROL
C
RANGE
A
Control Range ±13 ±14 ±15 dB
Step Resolution 1 2 3 dB
step
SPEAKER ATTENUATORS
C
RANGE
A
A
MUTE
V
Control Range 35 37.5 40 dB
Step Resolution 0.5 1.25 2.00 dB
step
Output Mute Attenuation Data Word = XXX11111 80 100 dB
E
Attenuation Set Error 1.25 dB
A
DC Steps Adjacent Attenuation Steps 0 3 mV
DC
9/21
Page 10
Electrical specifications TDA7342EQ2N
Table 4. Electrical characteristics (continued)
(V
= 9V; RL = 10KΩ; Rg = 50Ω; T
S
= 25°C; all gains = 0dB; f = 1KHz. Refer to the test
amb
circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
AUDIO OUTPUT
V
R
V
Clipping Level d = 0.3% 2.1 2.6 Vrms
clip
R
Output Load Resistance 2 KΩ
L
Output Impedance 30 100 Ω
O
DC Voltage Level 3.5 3.8 4.1 V
DC
GENERAL
V
I
Supply Voltage 6 9 10.2 V
CC
Supply Current 5 10 15 mA
CC
f = 1KHz 60 80 dB
PSRR Power Supply Rejection Ratio
B = 20 to 20kHz "A" weighted 65 dB
e
Output Noise
NO
Output Muted (B = 20 to 20kHz
flat)
All Gains 0dB (B = 20 to 20kHz
flat)
2.5 µV
5 15 µV
AV= 0 to -20dB 0 1 dB
Et Total Tracking Error
= -20 to -60dB 0 2 dB
A
V
S/N Signal to Noise Ratio All Gains = 0dB; V
S
Channel Separation 80 100 dB
C
d Distortion V
=1V 0.01 0.08 %
IN
= 1Vrms 106 dB
O
BUS INPUTS
V
V
V
1. WIN represents the MUTE programming bit pair D6, D5 for the zero crossing window threshold.
Input Low Voltage 1 V
IL
Input High Voltage 3 V
lN
Input Current VIN = 0.4V -5 5 µA
I
lN
Output Voltage SDA
O
Acknowledge
IO= 1.6mA 0.4 0.8 V
10/21
Page 11
TDA7342EQ2N I2C bus interface
4 I2C bus interface
Data transmission from microprocessor to the TDA7342EQ2N and viceversa takes place
thru the 2 wires I
resistors to positive supply voltage must be externally connected).
2
C BUS interface, consisting of the two lines SDA and SCL (pull-up
4.1 Data Validity
As shown in Figure 3, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
4.2 Start and Stop Conditions
As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH.
A STOP conditions must be sent before each START condition.
4.3 Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
4.4 Acknowledge
The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 5). The peripheral (audioprocessor) that acknowledges has to pull-down
(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW
during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
4.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier
transmission: simply it waits one clock without checking the slave acknowledging, and sends
the new data. This approach of course is less protected from misworking and decreases the
noise immunity.
11/21
Page 12
I2C bus interface TDA7342EQ2N
Figure 3. Data Validity on the I2C BUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
Figure 4. Timing Diagram of I
SCL
SDA
START
2
Figure 5. Acknowledge on the I
SCL
SDA
START
1
MSB
C BUS
2
I
CBUS
D99AU1032
2
C BUS
23789
D99AU1033
STOP
ACKNOWLEDGMENT
FROM RECEIVER
Patent note: Purchase of I2C Components of STMicrolectronics,
conveys a license under the Philips I
use these components in an I
system conforms to the I
defined by Philips.
12/21
2
2
C system, provided that the
2
C Standard Specifications as
C Patent Rights to
Page 13
TDA7342EQ2N Software specification
5 Software specification
5.1 Interface Protocol
The interface protocol comprises:
● A start condition (s)
● A chip address byte, (the LSB bit determines read/write transmission)
● A subaddress byte.
● A sequence of data (N-bytes + acknowledge)
● A stop condition (P)
CHIP ADDRESS
SUBADDRESS DATA 1 ... DATA n
MSB
S 1 0 0 0 1 0 A R/W
D06AU1650
ACK = Acknowledge
S = Start
P = Stop
I = Auto Increment
X = Not used
A= I
2
C address value selectable according to ADDR pin status
ADDR = Open/Gnd A = O
ADDR = V
A = I
CC
MAX CLOCK SPEED 500kbits/s
5.2 Auto increment
If bit I in the subaddress byte is set to "1", the autoincrement of the subaddress is enabled
Table 5. SUBADDRESS (receive mode)
MSB LSB Function
X X X I A3 A2 A1 A0
LSB
MSB LSB MSB LSB
ACK
XXX A3A2A1A
I ACK DATA ACK P
0
0 0 0 0 Input Selector
0 0 0 1 Loudness
0 0 1 0 Volume
0 0 1 1 Bass, Treble
0 1 0 0 Speaker Attenuator LF
0 1 0 1 Speaker Attenuator LR
0 1 1 0 Speaker Attenuator RF
0 1 1 1 Speaker Attenuator RR
1 0 0 0 Mute
13/21
Page 14
Software specification TDA7342EQ2N
5.3 Transmitted data
Table 6. Send mode
MSB LSB
X X X X X SM ZM X
ZM = Zero crossing muted (HIGH active)
SM = Soft mute activated (HIGH active)
X = Not used
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chip address.
5.4 Data byte specification
X = not relevant; set to "1" during testing
Table 7. Input selector
MSB LSB
D7 D6
0 1 0 0 0 not used
0 1 0 0 1 IN 2
0 1 0 1 0 IN 1
0 1 0 1 1 AM mono
0 1 1 0 0 not used
0 1 1 0 1 not used
0 1 1 1 0 not allowed
0 1 1 1 1 not allowed
0 1 0 0 11.25dB gain
0 1 0 1 7.5dB gain
0 1 1 0 3.75dB gain
0 1 1 1 0dB gain
D5 D4 D3 D2 D1 D0
0 0dB differential input gain (IN3)
1 -6dB differential input gain (IN3)
FUNCTION
For example to select the IN 2 input with a gain of 7.5dB the Data Byte is: X X 1 0 1 0 0 1
14/21
Page 15
TDA7342EQ2N Software specification
Table 8. Loudness
MSB LSB
FUNCTION
D7 D6
D5 D4 D3 D2 D1 D0
X X X 0 0 0 0 0 0dB
X X X 0 0 0 0 1 -1.25dB
X X X 0 0 0 1 0 -2.5dB
X X X 0 0 0 1 1 -3.75dB
X X X 0 0 1 0 0 -5dB
X X X 0 0 1 0 1 -6.25dB
X X X 0 0 1 1 0 -7.5dB
X X X 0 0 1 1 1 -8.75dB
X X X 0 1 0 0 0 -10dB
X X X 0 1 0 0 1 -11.25dB
X X X 0 1 0 1 0 -12.5dB
X X X 0 1 0 1 1 -13.75dB
X X X 0 1 1 0 0 -15dB
X X X 0 1 1 0 1 -16.25dB
X X X 0 1 1 1 0 -17.5dB
X X X 0 1 1 1 1 -18.75dB
(1)
X X X 1 D3 D2 D1 D0 Loudness OFF
1. If the loudness is switched OFF, the loudness stage is acting like a volume attenuator with flat frequency
response. D0 to D3 determine the attenuation level.
For example to select -17.5dB attenuation, loudness OFF, the Data Byte is: X X X1 1 1 1 0
Table 9. Mute
MSB LSB
D7 D6
D5 D4 D3 D2 D1 D0
1 Soft Mute On
0 1 Soft Mute with fast slope (I = I
1 1 Soft Mute with slow slope (I = I
1 Direct Mute
0 1 Zero Crossing Mute On
0 0
1
0 0
15/21
Zero Crossing Mute Off
(delayed until next zerocrossing)
Zero Crossing Mute and Pause Detector
Reset
160mV ZC Window Threshold (WIN =
00)
FUNCTION
MAX
MIN
)
)
Page 16
Software specification TDA7342EQ2N
Table 9. Mute
MSB LSB
FUNCTION
D7 D6
D5 D4 D3 D2 D1 D0
0 1 80mV ZC Window Threshold (WIN = 01)
1 0 40mV ZC Window Threshold (WIN = 10)
1 1 20mV ZC Window Threshold (WIN = 11)
0 Nonsymmetrical Bass Cut
(1)
1 Symmetrical Bass Cut
1. Bass cut for very low frequencies; should not be used at +16 and +18dB bass boost (DC gain)
An additional direct mute function is included in the Speaker Attenuators.
Table 10. Speaker attenuators
MSB LSB
D7 D6
D5 D4 D3 D2 D1 D0
X X X 0 0 0 0dB
X X X 0 0 1 -1.25dB
X X X 0 1 0 -2.5dB
X X X 0 1 1 -3.75dB
X X X 1 0 0 -5dB
SPEAKER ATTENUATOR LF, LR, RF, RR
1.25dB step
X X X 1 0 1 -6.25dB
X X X 1 1 0 -7.5dB
X X X 1 1 1 -8.75dB
10dB step
X X X 0 0 0dB
X X X 0 1 -10dB
X X X 1 0 -20dB
X X X 1 1 -30dB
X X X 1 1 1 1 1 Speaker Mute
For example an attenuation of 25dB on a selected output is given by: X X X1 0 1 0 0
Table 11. Bass/Treble
MSB LSB
D7 D6
D5 D4 D3 D2 D1 D0
Treble step
0 0 0 0 -14dB
0 0 0 1 -12dB
FUNCTION
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Page 17
TDA7342EQ2N Software specification
Table 11. Bass/Treble (continued)
MSB LSB
D7 D6
0 0 1 0 -10dB
0 0 1 1 -8dB
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 0dB
1 1 1 1 0dB
1 1 1 0 2dB
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB
Bass steps
0 0 1 0 -10dB
0 0 1 1 -8dB
D5 D4 D3 D2 D1 D0
FUNCTION
0 1 0 0 -6dB
0 1 0 1 -4dB
0 1 1 0 -2dB
0 1 1 1 -0dB
1 1 1 1 -0dB
1 1 1 0 2dB
1 1 0 1 4dB
1 1 0 0 6dB
1 0 1 1 8dB
1 0 1 0 10dB
1 0 0 1 12dB
1 0 0 0 14dB
0 0 0 1 146B
0 0 0 0 18dB
For example 12dB Treble and -8dB Bass give the following DATA BYTE: 0 0 1 1 1 0 0 1
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Page 18
Software specification TDA7342EQ2N
Table 12. Volume
MSB LSB
FUNCTION
D7 D6
D5 D4 D3 D2 D1 D0
0.31dB Fine Attenuation Steps
0 0 0dB
0 1 -0.31dB
1 0 -0.62dB
1 1 -0.94dB
1.25dB Coarse Attenuation Steps
0 0 0 0dB
0 0 1 -1.25dB
0 1 0 -2.5dB
0 1 1 -3.75dB
1 0 0 -5dB
1 0 1 -6.25dB
1 1 0 -7.5dB
1 1 1 -8.75dB
10dB Gain / Attenuation Steps
0 0 0 20dB
0 0 1 10dB
0 1 0 0dB
0 1 1 -10dB
1 0 0 -20dB
1 0 1 -30dB
1 1 0 -40dB
1 1 1 -50dB
For example to select -47.81dB Volume the Data Byte is: 1 1 0 1 1 0 0 1
Power on RESET: All Bytes Set to 1 1 1 1 1 1 1 0
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Page 19
TDA7342EQ2N Package information
6 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 6. TQFP32 Mechanical Data & Package Dimensions
DIM.
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.30 0.37 0.45 0.012 0.015 0.018
C 0.09 0.20 0.004 0.008
D 9.00 0.354
D1 7.00 0.276
D3 5.60 0.220
e 0.80 0.031
E 9.00 0.354
E1 7.0 0 0.276
E3 5.6 0 0.220
L 0.45 0.60 0.75 0.018 0.024 0.0 30
L1 1.00 0.039
K 0˚(min.), 3. 5°(typ.), 7°(max.)
mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
D
D1
OUTLINE AND
MECHANICAL DATA
Weight: 0.20gr
TQFP32 (7 x 7 x 1.40mm)
A1
A
A2
1724
25
B
32
1
e
8
TQFP32
16
E3D3E1
9
E
L1
L
Seating Plane
K
0.10mm
.004
B
C
0060661 C
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Page 20
Revision history TDA7342EQ2N
7 Revision history
Table 13. Document revision history
Date Revision Changes
03-Aug-2006 1 Initial release.
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Page 21
TDA7342EQ2N
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