Datasheet TDA4851 Datasheet (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

TDA4851

Horizontal and vertical deflection controller for VGA/XGA and autosync monitors

Preliminary speciﬁcation File under Integrated Circuits, IC02

November 1992

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

TDA4851

for VGA/XGA and autosync monitors

FEATURES

• VGA operation fully implemented including alignment-free vertical and E/W amplitude presettings

• 4th VGA mode easy applicable (XGA, Super VGA)

• Autosync operation externally selectable

• Low jitter

• All adjustments DC-controllable

• Alignment-free oscillators

• Sync separators for video or horizontal and vertical TTL

sync levels regardless of polarity

• Horizontal oscillator with PLL1 for sync and PLL2 for flyback

• Constant vertical and E/W amplitude in autosync operation

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V I

i sync

positive supply voltage (pin 1) 9.2 12 16 V supply current − 40 − mA AC-coupled composite video signal with negative-going sync

(peak-to-peak value, pin 9) sync slicing level − 120 − mV DC-coupled TTL-compatible horizontal sync signal (peak-to-peak value,

pin 9) slicing level 1.2 1.4 1.6 V DC-coupled TTL-compatible vertical sync signal (peak-to-peak value,

pin 10)

slicing level 1.2 1.4 1.6 V I I T

o V o H

amb

vertical differential output current (peak-to-peak value, pins 5 and 6) − 1 − mA

horizontal sink output current on pin 3 −−60 mA

operating ambient temperature range 0 −+70 °C

• DC-coupling to vertical power amplifier

• Internal supply voltage stabilization with excellent ripple

rejection to ensure stable geometrical adjustments

GENERAL DESCRIPTION

The TDA4851 is a monolithic integrated circuit for economical solutions in VGA/XGA and autosync monitors. The IC incorporates the complete horizontal and vertical small signal processing. VGA-dependent mode detection and settings are performed on chip. In conjunction with TDA4860/61/65, or TDA8351 (vertical output circuits) the ICs offer an extremely advanced system solution.

− 1 − V

1.7 −− V

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

PINS

PIN POSITION

TDA4851 20 DIL plastic SOT146

Note

1. SOT146-1; 1996 November 26.

November 1992 2

PACKAGE

MATERIAL CODE

(1)

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November 1992 3

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and autosync monitors

Fig.1 Block diagram.

TDA4851

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

PINNING

SYMBOL PIN DESCRIPTION

FLB 2 horizontal ﬂyback input HOR 3 horizontal output GND 4 ground (0 V) VERT1 5 vertical output 1; negative-going sawtooth VERT2 6 vertical output 2; positive-going sawtooth MODE 7 4th mode output and autosync input CLBL 8 clamping/blanking pulse output HVS 9 horizontal sync/video input VS 10 vertical sync input EW 11 E/W output (parabola to driver stage) C

VOS

PLL1 17 PLL1 phase R

HOS

PLL2 20 PLL2 phase

1 positive supply voltage

12 capacitor for amplitude control 13 vertical amplitude adjustment input 14 E/W amplitude adjustment input (parabola) 15 vertical oscillator resistor 16 vertical oscillator capacitor

18 horizontal oscillator resistor 19 horizontal oscillator capacitor

TDA4851

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction

An AC-coupled video signal or a DC-coupled TTL sync signal (H only or composite sync) is input on pin 9. Video signals are clamped with top sync on 1.28 V, and are sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync. DC-coupled TTL sync signals are also sliced at 1.4 V, however with the clamping circuit in current limitation. The polarity of the separated sync is detected by internal integration of the signal, then the polarity is corrected. The polarity information is fed to the VGA mode detector. The corrected sync is input signal for the vertical sync integrator and the PLL1 stage.

Vertical sync separator, polarity correction and vertical sync integrator

DC-coupled vertical TTL sync signals may be applied to pin 10. They are sliced at 1.4 V. The polarity of the separated sync is detected by internal integration, then the polarity is corrected. The polarity information is fed to the

VGA mode detector. If pin 10 is not used, it must be connected to ground. The separated V

signal from

i sync

pin10, or the integrated composite sync signal from pin 9 (TTL or video) triggers directly the vertical oscillator.

VGA mode detector and mode output

The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizontal and the vertical sync input signals. An external resistor (from V

pin 7) is necessary to match this function. In all three VGA modes the correct amplitudes are activated. The presence of the 4th mode is indicated by a HIGH on pin 7. This signal can be used externally to switch any horizontal or vertical parameters.

VGA mode detector input

For autosync operation the voltage on pin 7 must be externally forced to a level of < 50 mV. Vertical amplitude pre-settings for VGA are then inhibited. The delay time between vertical trigger pulse and the start of vertical deflection changes from 575 µs to 300 µs (575 µs is

November 1992 4

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

needed for VGA). The vertical amplitude then remains constant in a frequency range from 50 Hz up to 110 Hz.

Clamping and V-blanking generator

A combined clamping and V-blanking pulse is available on pin 8 (suitable for the video pre-amplifier TDA4881). The lower level of 1.9 V is the blanking signal derived from the vertical blanking pulse from the internal vertical oscillator. Vertical blanking equals the delay between vertical sync and start of vertical scan. By this, an optimum blanking is achieved for VGA/XGA and autosync operation (selectable via pin 7). The upper level of 5.4 V is the horizontal clamping pulse with an internally fixed pulse width of 0.8 µs. A monoflop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse. If composite sync is applied, one clamping pulse per H-period is generated during V-sync. The phase of the clamping pulse may change during V-sync (see Fig.8).

PLL1 phase detector

The phase detector is a standard type using switched current sources. The middle of the sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to pin 17. If composite sync is applied, the disturbed control voltage is corrected during V-sync (see Fig.8).

Horizontal oscillator

TDA4851

A certain amount of phase adjustment is possible by injecting a DC current from an external source into the PLL2 filter capacitor at pin 20.

Horizontal driver

This open-collector output stage (pin 3) can directly drive an external driver transistor. The saturation voltage is less than 300 mV at 20 mA. To protect the line deflection transistor, the horizontal output stage does not conduct for V

Vertical oscillator and amplitude control

This stage is designed for fast stabilization of the vertical amplitude after changes in sync conditions. The free-running frequency f R

VOS

and C

. The recommended values should be

VOS

is determined by the values of

altered marginally only to preserve the excellent linearity and noise performance. The vertical drive currents I I

are in relation to the value of R

Therefore, the oscillator frequency must be determined only by C

on pin 16.

VOS

-----------------------------------------------------

10.8 R

× C

VOS

To achieve a stabilized amplitude the free-running frequency f

(without adjustment) must be lower than the

lowest occurring sync frequency. The following contributions can be assumed:

VOS

< 6.4 V (pin 1).

VOS

and

This oscillator is of the relaxation type and requires a fixed capacitor of 10 nF at pin 19. By changing the current into pin 18 the whole frequency range from 13 to 100 kHz can be covered. The current can be generated either by a frequency to voltage converter or by a resistor. A frequency adjustment may also be added if necessary. The PLL1 control voltage at pin 17 modulates via a buffer stage the oscillator thresholds. A high DC-loop gain ensures a stable phase relationship between horizontal sync and line flyback pulses.

PLL2 phase detector

This phase detector is similar to the PLL1 phase detector. Line flyback signals (pin 2) are compared with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are compensated by adjusting the phase relationship between horizontal sync and horizontal output pulses.

November 1992 5

minimum frequency offset between f

and the

lowest trigger frequency 10% spread of IC ±3% spread of R (22 kΩ) ±1% spread of C (0.1 µF) ±5%

19%

Result:f

Hz 42 Hz==

-----------

1.19

(for 50 to 110 Hz application)

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

TDA4851

for VGA/XGA and autosync monitors

Table 1 VGA modes

MODE

H / V SYNC

POLARITY

1 + / − 31.45 70 350 LOW 2 − / + 31.45 70 400 LOW 3 − / − 31.45 60 480 LOW 4 + / + ﬁxed by external circuitry −−HIGH autosync */* ﬁxed by external circuitry −−forced to GND

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134)

SYMBOL PARAMETER MIN. MAX. UNIT

3,7

stg

amb

supply voltage (pin 1) −0.5 16 V voltage on pins 3 and 7 −0.5 16 V voltage on pin 8 −0.5 7 V voltage on pins 5, 6, 9, 10, 13, 14 and 18 −0.5 6.5 V current on pin 2 −±10 mA current on pin 3 − 100 mA current on pin 7 − 20 mA current on pin 8 −−10 mA storage temperature range −55 +150 °C

operating ambient temperature range 0 70 °C Tj maximum junction temperature 0 +150 °C V

ESD

electrostatic handling for all pins (note 1) −±400 V

FREQUENCY H

(kHz)

FREQUENCY V

(Hz)

NUMBER OF

ACTIVE LINES

MODE OUTPUT

PIN 7

Note to the Limiting Values

1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

THERMAL RESISTANCE

SYMBOL PARAMETER THERMAL RESISTANCE

th j-a

from junction to ambient in free air 65 K/W

November 1992 6

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

TDA4851

for VGA/XGA and autosync monitors

CHARACTERISTICS

= 12 V; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Internal reference voltage

ref

TC temperature coefﬁcient T PSRR power supply ripple rejection f = 1 kHz sinewave 60 75 − dB

Composite sync input (AC-coupled)

i sync

int

= +25 °C; measurements taken in Fig.3 unless otherwise speciﬁed

amb

positive supply voltage (pin 1) 9.2 12 16 V supply current I18= −1.05 mA − 36 44 mA

= −3.388 mA − 40 49 mA

internal reference voltage 6.0 6.25 6.5 V

= +20 to +100 °C −− ±90 10-6/K

amb

f = 1 MHz sinewave 25 35 − dB

supply voltage (pin 1) to ensure all

9.2 − 16 V

internal reference voltages

=5V

sync amplitude of video input signal

sync on green − 300 − mV

(pin 9) top sync clamping level 1.1 1.28 1.5 V slicing level above top sync level R allowed source resistance for 7%

=50Ω 90 120 150 mV

> 200 mV −− 1.5 kΩ

i sync

duty factor differential input resistance during sync − 80 −Ω charging current of coupling capacitor V9> 1.5 V 1.3 2 3 µA vertical sync integration time to

generate vertical trigger pulse

fH= 31 kHz; I18= −1.050 mA

= 64 kHz;

710 13µs

3.5 5 6.5 µs

I18= −2.169 mA f

= 100 kHz;

2.5 3.4 4.5 µs

I18= −3.388 mA

Horizontal sync input (DC-coupled, TTL-compatible)

i sync

sync input signal (peak-to-peak value, pin 9)

slicing level 1.2 1.4 1.6 V

r,tf

minimum pulse width 700 −−ns rise time and fall time 10 − 500 ns input current V9= 0.8 V −− −200 µA

Automatic horizontal polarity switch

p H/tH

horizontal sync pulse width related to t

H-sync on pin 9

(duty factor for automatic polarity correction)

delay time for changing sync polarity 0.3 − 1.8 ms

November 1992 7

1.7 −−V

= 5.5 V −− 10 µA

−− 30 %

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

TDA4851

for VGA/XGA and autosync monitors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Vertical sync input (DC-coupled, TTL-compatible)

i sync

sync input signal (peak-to-peak value, pin 10)

slicing level 1.2 1.4 1.6 V I t

10 p V

input current 0 < V10< 5.5 V −− ±10 µA

maximum vertical sync pulse width for

automatic vertical polarity switch

Horizontal mode detector output

output saturation voltage LOW

(for Modes 1, 2 and 3)

output voltage HIGH mode 4 −− V I

load current range to force VGA

mode-dependent vertical and parabola

amplitudes

output current mode 4 − 0 − mA

VGA / autosync mode switch

input voltage LOW to force autosync

mode

Horizontal clamping / blanking generator output

output voltage LOW −− 0.9 V

blanking output voltage internal V blanking 1.6 1.9 2.2 V

clamping output voltage H-sync on pin 9 5.15 5.4 5.65 V I

internal sink current for all output levels H and V scanning 2.3 2.9 3.5 mA

external load current −− −3.0 mA t

clp

clamping pulse start with end of H-sync

clamping pulse width V8= 3 V 0.6 0.8 1.0 µs S steepness of rise and fall times − 60 75 ns/V

Vertical oscillator

vertical free-running frequency R15=22kΩ;

nominal vertical sync range no f0 adjustment 50 − 110 Hz

voltage on pin 15 R15=22kΩ 2.8 3.0 3.2 V

delay between sync pulse and start of

vertical scan

in VGA/XGA mode, activated by an

external resistor on pin 7

in autosync mode V I

control current for amplitude control −±200 −µA

capacitor for amplitude control −− 0.18 µF

V-sync on pin 10

1.7 −−V

−− 300 µs

VGA mode I7=6mA − 0.275 0.33 V

modes 1, 2 and 3 2 − 6mA

0 − 50 mV

Fig.6

= 6.25 V

ref

− 42 − Hz

C16= 0.1 µF

measured on pin 8

500 575 650 µs

< 50 mV 240 300 360 µs

November 1992 8

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

TDA4851

for VGA/XGA and autosync monitors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Vertical differential output

differential output current between

pins 5 and 6 (peak-to-peak value)

maximum offset-current error I

maximum linearity error −− ±1.5 % Vertical amplitude adjustment (in percentage of output signal) V

∆I

/∆t VGA mode-dependent pre-settings

input voltage − 5.0 − V

adjustment current I

activated by an external resistor on pin 7

Mode 1 116.2 116.8 117.4 %

Mode 2 101.6 102.2 102.8 %

Mode 3 − 100 − %

Mode 4 − 100 − %

autosync operation

(VGA operation disabled)

Fig.7 mode 3; I13>−135 µA;

0.9 1.0 1.1 mA

R15=22kΩ

=1mA −− ±2.5 %

(100%) −110 −120 −135 µA

o max

(typically 58%) − 0 −µA

o min

Table 1; note 1

< 50 mV − 100 − %

Horizontal comparator PLL1

upper control voltage limitation − 5.9 − V

lower control voltage limitation − 5.1 − V I

control current Fig.6 −±0.083I18− mA

Horizontal oscillator

osc

centre frequency R18= 2.4 kΩ (pin 18);

deviation of centre frequency −− ±3%

temperature coefﬁcient 0 +200 +300 10

I V

H/tH

relative holding/catching range ±6 ±6.5 ±7.3 %

external oscillator current −0.5 −−4.3 mA

voltage at reference current input

(pin 18)

Horizontal PLL2

upper clamping level of ﬂyback input I2=6mA − 5.5 − V

lower clamping level of ﬂyback input I

H-ﬂyback slicing level − 3.0 − V t

d/tH

delay between middle of sync and

middle of H-ﬂyback related to t V

upper control voltage limitation − 6.2 − V

lower control voltage limitation − 4.8 − V I

∆t/t

control current −±0.083I18−µA

PLL2 control range related to t

− 31.45 − kHz

C19= 10 nF (pin 19)

-6

2.35 2.5 2.65 V

Fig.6

= −1mA −−0.75 − V

− 3.0 − %

30 −−%

November 1992 9

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

TDA4851

for VGA/XGA and autosync monitors

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Horizontal output (open-collector)

p/tH

output voltage LOW I3=20mA −− 0.3 V

tH duty factor 42 45 48 %

threshold to activate under voltage

protection ∆t

jitter of horizontal output f = 31 kHz −− 3.5 ns

E/W output

bottom output signal during mid-scan

(pin 11)

top output signal during ﬂyback 4.2 4.5 4.8 V

temperature coefﬁcient of output signal −− 250 10-6/K

E/W amplitude adjustment (parabola)

input voltage (pin 14) − 5.0 − V

adjustment current 100% parabola −110 −120 −135 µA

Fig.6

=60mA −− 0.8 V

horizontal output off − 5.6 − V horizontal output on − 5.8 − V

f = 64 kHz −− 1.9 ns f = 100 kHz −− 1.2 ns note 2

internally stabilized 1.05 1.2 1.35 V

Fig.7

typically 28% parabola − 0 −µA

Notes to the characteristics

1. ∆Io/∆t relative to value of Mode 3.

2. Parabola amplitude tracks with mode-dependent vertical amplitude but not with vertical amplitude adjustment. Tracking can be achieved by a resistor from vertical amplitude potentiometer to pin 14.

November 1992 10

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

APPLICATION INFORMATION

TDA4851

Fig.3 Application circuit for 3-mode VGA (31.45 kHz).

Fig.4 64 kHz application circuit.

November 1992 11

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

TDA4851

Fig.5 31 to 64 kHz application including 4-mode VGA.

Fig.6 Horizontal timing diagram.

November 1992 12

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

TDA4851

Fig.7 Vertical and E/W timing diagram.

November 1992 13

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November 1992 14

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and autosync monitors

(1) clamp pulses triggered by H-sync (2) clamp pulses triggered by leading edge of V-trigger pulse (3) clamp pulses triggered by horizontal oscillator (4) during V-trigger pulse clamp pulses are generated internally (5) control voltage of PLL1 is corrected during V-trigger pulse

Fig.8 Pulse diagram for composite sync applications (showing reduced influence of V-sync on H-phase and drive pulses for F/V converters).

TDA4851

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November 1992 15

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller

for VGA/XGA and autosync monitors

Fig.9 Internal circuits.

TDA4851

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

PACKAGE OUTLINE

DIP20: plastic dual in-line package; 20 leads (300 mil)

seating plane

TDA4851

SOT146-1

w M

(e )

pin 1 index

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

OUTLINE

VERSION

SOT146-1

1 2

min.

max.

1.73

1.30

0.068

0.051

IEC JEDEC EIAJ

0.53

0.38

0.021

0.015

0.36

0.23

0.014

0.009

REFERENCES

cD E e M

(1) (1)

26.92

26.54

1.060

1.045

SC603

6.40

6.22

0.25

0.24

(1)

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

10.0

0.2542.54 7.62

8.3

0.39

0.010.10 0.30

0.33

ISSUE DATE

92-11-17 95-05-24

max.

2.04.2 0.51 3.2

0.0780.17 0.020 0.13

November 1992 16

Philips Semiconductors Preliminary speciﬁcation

Horizontal and vertical deﬂection controller for VGA/XGA and autosync monitors

SOLDERING Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“IC Package Databook”

Soldering by dipping or by wave

The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.

(order code 9398 652 90011).

TDA4851

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

stg max

). If the

DEFINITIONS

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

November 1992 17

Datasheet TDA4851 Datasheet (Philips)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

QUICK REFERENCE DATA

GENERAL DESCRIPTION

ORDERING INFORMATION

PINNING

Vertical sync separator, polarity correction and vertical sync integrator

VGA mode detector and mode output

VGA mode detector input

Clamping and V-blanking generator

PLL1 phase detector

Horizontal oscillator

Horizontal driver

Vertical oscillator and amplitude control

PLL2 phase detector

LIMITING VALUES

THERMAL RESISTANCE

CHARACTERISTICS

APPLICATION INFORMATION

PACKAGE OUTLINE

SOT146-1

DEFINITIONS

LIFE SUPPORT APPLICATIONS