Datasheet TDA4691T, TDA4691 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA4691

Sync Processor with Clock (SPC)

Preliminary specification
File under Integrated Circuits, IC02

September 1993

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

FEATURES

• Sync processor for horizontal (H)
and vertical (V) sync pulses
generated by internal 13.5 MHz
oscillator

• Stable ‘On Screen Display (OSD)’,
if no input signal is present with free
running internal oscillator;
automatic turn over to locked
oscillator, if input signal is available

• External clock oscillator can be
used

• Standard 50/60 Hz signals are
identified automatically

• Additional outputs for 13.5 MHz,
composite sync, 50//60 Hz
identification, signal identification
(mute), super-sandcastle 12 V

• TTL compatible outputs (H, V,
composite sync and 13.5 MHz)

• 3 different time constants for the
PHI1 PLL: fast, normal and slow

and T3). Fast and normal

(T

1,T2

time constant are set independent
from each other

• Start of H-pulse definable by
application

• Digital interference reduction for H
and V signals

• Digital noise detector

• Time correction of non-standard

H-pulses and equalizing pulses for
optimum PLL control.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

P2

I

P2

V

P1

I

P1

P

tot

supply voltage 4.5 5.0 5.5 V
supply current −−30 mA
supply voltage 7.2 8.0 8.8 V
supply current −−30 mA
total power

− 260 430 mW

dissipation

Inputs

V

20

input voltage RG=1kΩ− 12 V

Outputs

V

4

signal
identification
voltage

no signal;

−−0.3 V

1mA
signal open

− V

P1

V

collector

V

7

50/60 Hz
voltage

50 Hz; 1 mA −−0.3 V
60 Hz open

− V

P1

V

collector

V

10

vertical output
voltage

HIGH;

−1to0mA

2.7 − V

P2

V

LOW; 2 mA −−0.8 V

V

11

horizontal
output voltage

HIGH;

−1to0mA

2.7 − V

P2

V

LOW; 2 mA −−0.8 V

V

13

clock output
voltage

HIGH;

−1to0mA

2.7 − V

P2

V

LOW; 2 mA −−0.8 V

ORDERING INFORMATION

GENERAL DESCRIPTION

The TDA4691 is a bipolar integrated

EXTENDED

TYPE NUMBER

circuit for sync processing in 50/100
and 60/120 Hz TV sets, preferably in
conjunction with the programmable
deflection controller TDA9150. A line
locked 13.5 MHz clock with several
dividers and logic circuitry is available
generating the horizontal and vertical
sync outputs. The device can be

TDA4691 20 DIL plastic SOT146

TDA4691T 20 SO plastic SOT163

Note

1. SOT146-1; 1996 December 9.

2. SOT4163-1; 1996 December 9.

assembled in a DIL20 or SO20
package.

September 1993 2

PINS

PIN

POSITION

PACKAGE

MATERIAL CODE

(1)
(2)

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September 1993 3

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.1 Block diagram.

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

PINNING

SYMBOL PIN DESCRIPTION

BL 1 black level storage of sync separator
INT1 2 integration for time constant switching
GND1 3 ground for 8 V supply
SI 4 signal identification output
INT2 5 integration for signal identification
SSC 6 sandcastle output
50/60 Hz 7 50/60 Hz output
GND2 8 ground for 5 V supply
CS 9 sync output
V

out

H

out

V

P2

CL

out

SH 14 start of H-pulse
VCOF 15 current defining VCO frequency
Fi

1

Fi

2

V

REF

V

P1

(C)VBS 20 input sync separator

10 V-output buffer
11 H-output buffer
12 supply 5 V
13 clock-output buffer

16 phase detector filtering
17 phase detector filtering
18 reference voltage
19 supply 8 V

Fig.2 Pin configuration.

September 1993 4

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

FUNCTIONAL DESCRIPTION

(See block diagram Fig.1 and timing
Figs 12 to 16)

Sync separator

Top-sync and blacklevel are stored
and H and V sync pulses are sliced in
the middle of both levels (50%).

Sync-output buffer

This circuit turns the current pulse
from the sync separator into a TTL
signal.

Sync processing

This circuit assures that phase
comparison can operate correctly
during V-pulses. Phase jumps
initiated by alternating headpulses of
VCR recorders are quickly recovered.
The sync processing contains the
functions H/2 suppression, sync
extension and sync interruption.
These three functions are only active
if successive pulses have a minimum
distance of 1.6 µs.
The H/2 suppression operates with a
gate −15 µs up to +14 µs around the
PHI1-reference and is necessary for
suppression of the equalizing pulses.
For sync interruption this gate is
closed earlier if the detected sync is
longer than 4.8 µs.
Only during V-pulses will the duration
of the applied pulses be tested. If they
are longer than 1.6 µs they will be
recognized as sync pulses and
enlarged up to 4.6 µs.

Phase detector (PHI1)

The phase detector has separate
filters for the fast time constant T

(pin

1

17) and normal time constant T2 (pins

17 and 16). The slow time constant T
uses the normal time constant T2 with
reduced control current. For reduction
of H-pulse modulation the filter at pin
16 is switched off during sync time if
normal time constant T2 is on. Thus

no frequency shifting of the oscillator
is possible during sync.

Time-constant switching

This block contains a switch and an
impedance converter (buffer). The
switch connects the filters at pin 16
and 17 in parallel (normal time
constant T

or slow time constant T3).

2

The buffer transfers the control
voltage at pin 17 to pin 16 (fast time
constant T

). Which of the 2 functions

1

is active is determined by the blocks
noise detector, V-logic or signal
identification.

VCO 13.5 MHz

The adjustment of the nominal
frequency (13.5 MHz) is achieved at
pin 15. The VCO control voltage is
applied (from the phase detector) at
pin 16.
The control range can be adjusted by
the current at pin 18.
Pin 15 can be used to feed in an
external frequency. Under these
circumstances the internal VCO is
switched off by application.
The control voltage at pin 16 can be
used to control the external VCO.

VCO-buffer

The VCO-buffer delivers a TTL
compatible signal of 13.5 MHz to pin

13.

ECL-prescaler

This block consists of a :16
asynchronous prescaler.

H-divider

This is a divider by 54. It is split into a
prescaler :2 and a divider by 27. Out
of this block several signals are taken

3

for generation of H-frequently pulses
in the H-logic block. These signals
must have good timing. This is
achieved by special synchronization.

H-logic

This block creates all pulses
necessary for the SSC generator, the
signal identification, the phase
detector, the sync preparation and the
V-divider.

V-divider

The V-divider consists of an
asynchronous 10-bit divider and a
decoder logic. The divider is clocked
with twice the line frequency. The
decoder circuit delivers the pulses
necessary for the V-logic.

V-logic

In the V-logic the V-syncs from the
sync separator are evaluated and
noise reduced. Also certain operation
states are switched ON and OFF.
Additionally the reset pulse for the
V-divider and the 50/60 Hz
information is generated.

H-pulse former

The H-pulse starting point can be
shifted in this stage, also the gate
pulse of ∼2.4 µs is generated for use
in the digital noise identification block.

H-pulse buffer

In this circuit the line signal will be
pre-synchronized by output signal of
the :16 divider and synchronized by
the 13.5 MHz clock. The buffer
delivers TTL output signals.

V-pulse buffer

The signal out of the V-divider is
synchronized with 13.5 MHz clock
and converted to a TTL output level.

Gap reference

This circuit operates with the
gap-principle and is stable with regard
to temperature and supply voltage
changes.

September 1993 5

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

50/60 Hz output

This is an open-collector output,
which is LOW if more than 287
lines/field are detected.

SSC generator

The SSC generator generates a 3
stage super-sandcastle pulse on an
open-collector output, which is able to
operate up to 12 volts. The blanking
thresholds 2.5 V and 4.5 V are
derived from the gap reference (point

16).

Signal identification with Digital
PLL (DPLL)

The analog signal identification with
output signal at pin 4 is completed
with a DPLL. This PLL is able to lock
on the separated sync although the

13.5 MHz VCO is not locked on the

input signal. The ratio of the lock
condition to the unlock condition
influences the voltage at pin 5. The
detector circuit of the analog signal
identification block evaluates the
voltages at pins 2 and 5. If the voltage
at pin 5 reaches 4 V (most of the time
the PLL is locked) pin 4 will be HIGH.
The voltages at pins 2 and 5 together
with the state of the V-logic set the
operation state of the TDA4691. The
TDA4691 is able to accommodate to
different input conditions
automatically.

Some operation conditions can be
set externally by influencing the
voltages at pins 2 and 5:

1. Time constant T
voltage at pin 2 is limited to
5 V (0 to 5 V).

2. Time constant T3(slow) on:
voltage at pin 5 is limited to

6.2 V (0 to 6.2 V).

3. Time constant T3(slow)
inoperative:
voltage at pin 2 is limited
between 4 V and 6.5 V.

4. Time constant T3 (slow)
inoperative with input signal:
voltage at pin 2 is limited to

6.5 V (0 to 6.5 V).

5. VCO frequency fixed to f0:
pin 2 is set to ground
(V2< 1 V).

Noise detector

This block switches the time
constant to ‘slow’ if on standard
signal a certain noise level is
reached. This noise level is
measured in a small window
inside the sync pulse.

(fast) on:

1

September 1993 6

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V
I
V
I
P
T
T
V
I
V
V
V
V
V
V
V

P1

P1

P2

P2

tot
stg
amb
ESD

I/O

I
I
6
15
16
17
18

supply voltage 0 9.0 V
supply current − 40 mA
supply voltage 0 5.7 V
supply current − 50 mA
total power dissipation − 650 mW
storage temperature −25 +150 °C
operating ambient temperature 0 +70 °C
ESD-protection on all pins; note 1 300 − V
currents on all pins except supply pins 3, 8, 12 and 19 −10 +10 mA
voltage applied to pins 1, 2, 4, 5, 7, 14 and 20 0 V
voltage applied to pins 9, 10, 11 and 13 0 V

P1
P2

V

V
voltage applied to pin 6 0 13.2 V
voltage applied to pin 15 0 5 V
voltage applied to pin 16 0 5 V
voltage applied to pin 17 0 5 V
voltage applied to pin 18 0 5 V

Note to the limiting values

1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.

THERMAL RESISTANCE

SYMBOL PARAMETER THERMAL RESISTANCE

R

th j-a

from junction to ambient in free air

SOT146 (without heat spreader) 65 K/W
SOT163 85 K/W

September 1993 7

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

CHARACTERISTICS

V

=8V; VP2= 5 V; measured at T

P1

input signal referenced to CCIR standard.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pins 19 and 12; all voltages are measured with regard to ground (pins 3 and 8))

V

19

I

P1

V

12

I

P2

P

tot

supply voltage 7.2 8.0 8.8 V
supply current − 20 30 mA
supply voltage same rise time as V194.5 5.0 5.5 V
supply current − 15 30 mA

total power dissipation − 260 430 mW
Sync separator (pin 20)
V

20(p-p)

V

20(p-p)

R

G

I

20

I

20

input voltage (peak-to-peak value) AC coupled − 12V

sync amplitude (peak-to-peak value) 0.1 − 0.6 V

source resistor of generator −−1kΩ

current during sync −−30 −µA

current during remaining time − 1 −µA
Black level (pin 1)
SLH slicing level H − 50 − %

SLV slicing level V − 50 − %

= +25 °C; unless otherwise specified; application see Figs 10 and 11; video

amb

Sync output (pin 9)
V

9

V

9

C

L

t

1

t

2

no sync I9= +1mA − 0.3 − V

positive sync I9= −1 mA 2.7 − V

load capacitance −−40 pF

time delay between pin 20 and pin 9 see Fig.3 100 200 500 ns

time delay between pin 20 and pin 9 see Fig.3 100 300 500 ns
Phase detector (pins 16 and 17)
f

0

’f

f

0

I

17

nominal sync frequency − 15.625 − kHz

: 864 = phiref − 15.625 − kHz

osc

current at sync time

(fast and normal time constant)
I

17

I

16

V

17

V

16

∆f

/∆V

0

current at sync time (slow time constant) −±80 −µA

current at sync time time constant T

filter 2 voltage 1.5 3 4.5 V

filter 1 voltage 1.5 3 4.5 V

VCO sensitivity see VCO − 360 − kHz/V

16

13.5 MHz VCO (pin 15)
R

V
I

15

g

15

15

VCO

f0 defining resistor see Fig.4(a) − 3.75 − kΩ

pin voltage (V19 dependent) see Fig.4(a) 2.9 3 3.1 V

current for 13.5 MHz −720 −800 −880 µA

transconductance at f

V

12

−±240 −µA

1

0

−±2−mA

15.2 − 18.6 kHz/µA

September 1993 8

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆f0/∆V

Input of external oscillator (pin 15)
V

15

V

15

R

int

C

int

13.5 MHz buffer (pin 13)
V

13

V

13

V

13

t

r

t

f

D

13

C

L

∆T

13

VCO sensitivity 4% control range;

16

− 360 − kHz/V
depending on current
at pin 18

pin voltage AC see Fig.4(b) 1 − 3V
pin voltage DC dependent on V

19

− 5 − V

internal resistance see Fig.4(b) − 7 − kΩ
internal capacitance see Fig.4(b) − 4 − pF

clock HIGH level output voltage I13= −1 mA;

2.7 − V
V12= 4.5 V

clock HIGH level output voltage I13= 0 mA 2.7 − V
clock LOW level output voltage I13= 2 mA;

0 − 0.8 V

V12= 5.5 V

rise time see Fig.5 − 20 − ns
fall time see Fig.5 − 20 − ns
mark-to-space ratio V13= 1.5 V 45/55 − 55/45 %
load capacitance −−40 pF
jitter on clock output

(peak-to-peak value)

normal time constant
T

2;

−−2ns

measured between
lines 25 and 305

V

12

V

12

H-output buffer (pin 11)
V

11

V

11

V

11

t

r

t

f

t

3

t

4

t

5

C

L

H HIGH level output voltage I11= −1 mA;

H HIGH level output voltage I11= 0 mA 2.7 − V
H LOW level output voltage I11= 2 mA;

rise time see Fig.6 − 25 − ns
fall time see Fig.6 − 25 − ns
time relation pin 13 to 11 see Fig.6 − 25 55 ns
time relation pin 13 to 11 see Fig.6 3 −−ns
H-pulse width see Fig.6 3.0 3.6 4.2 µs

load capacitance see Fig.6 −−40 pF
Start of H-pulse (pin 14)
I

14

t

61

t

62

t

63

t

64

V

14(t61

current pin 14 −−±100 µA

time delay pulse between pin 20 and 11 see Fig.6 −1.1 −1.3 −1.5 µs

time delay pulse between pin 20 and 11 see Fig.6 −0.6 −0.8 −1.0 µs

time delay pulse between pin 20 and 11 see Fig.6 3.8 4.0 4.2 µs

time delay pulse between pin 20 and 11 see Fig.6 5.0 5.2 5.4 µs

) voltage pin 14 (proportional to V19)0−1V

V12= 4.5 V

V12= 5.5 V

2.7 − V

12

12

0 − 0.8 V

V

V

September 1993 9

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V14(t62) voltage pin 14 (proportional to V19) 2 2.4 2.8 V
V
V

V-output buffer (pin 10)
V

V
V

t
t
t
t
t
t
C

Reference (pin 18)
V

R
∆f control range VCO −±4−%
I
∆f
I
I

50/60 Hz output (pin 7; open collector; see Fig.8)
V

V

I
Sandcastle output (pin 6)
V

V

V

V
t
t
t

) voltage pin 14 (proportional to V19) 3.5 4 4.5 V

14(t63

) voltage pin 14 (proportional to V19) 5 5.5 6 V

14(t64

10

V HIGH level output voltage I10= −1 mA;

2.7 − V

V12= 4.5 V

10
10

r
f
3
4
5
6

L

REF

18

18/1

a
18/3
18/3

7

7

V HIGH level output voltage I10= 0 mA 2.7 − V
V LOW level output voltage I10= 2 mA;

= 5.5 V

V

12

0 − 0.8 V

rise time see Fig.6 − 25 − ns
fall time see Fig.6 − 25 − ns
time relation pin 13 to 10 see Fig.6 − 25 55 ns
time relation pin 13 to 10 see Fig.6 3 −−ns
V-pulse width see Fig.7 280 320 350 µs
time delay between pin 20 and pin 10 see Fig.7 12 16 20 µs
load capacitance see Fig.7 −−40 pF

reference voltage 1.1 1.2 1.3 V
control current defining resistor 8 − 30 kΩ

current pin 18 (±4%) − 105 −µA
adjustable control range ±3 −±5%
current pin 18 (±3%) − 80 −µA
current pin 18 (±5%) − 120 −µA

output voltage pin 7; 50 Hz
≥ 287.5 lines/field = LOW

output voltage pin 7; 60 Hz

I7= 1 mA 0 − 0.3 V

= 2 mA 0 0.3 0.8 V

I

7

2.7 − V

≤ 287 lines/field = HIGH

7

6
6

6

6
w
w
2

output leakage current −−50 µA

burstkey pulse see Fig.9 9.5 10 12 V
H-blanking pulse

independent from V
V-blanking pulse

independent from V

supply

supply

4.3 4.5 4.7 V

2.3 2.5 2.7 V

voltage pin 6 LOW 0 0.2 0.8 V
pulse width burstkey; 50 Hz at 6.5 V; see Fig.9 4.0 4.3 4.7 µs
pulse width burstkey; 60 Hz at 6.5 V; see Fig.9 3.3 3.8 4.1 µs
time relation between pin 20 and

see Fig.9 2.2 2.5 2.8 µs

burstkey

V

12

V

12

V

19

September 1993 10

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

3

t

4

t

5

t

5

t

6

t

6

Integration (pin 5)
V

5

V

5

Signal identification (pin 4; open collector via R
V

4

V

4

I

4

Integration (pin 2; see Fig.15)
V

2

V

2

V

2

V

2

V

2

V

2

V

2

time relation between pin 20 and

see Fig.9 3.5 4.0 4.5 µs

blanking
H-blanking time see Fig.9 − 11.8 −µs
start time H-pulse pin 20 to stop time

burstkey pin 6; 50 Hz
start time H-pulse pin 20 to stop time

H-sync = 4.7 µs;

8.0 9.0 9.7 µs

see Fig.9
see Fig.9 7.5 8.6 9.2 µs

burstkey pin 6; 60 Hz
V-blanking pulse; 50 Hz −−2.5 to

− lines

+22.5

V-blanking pulse; 60 Hz −−3.0 to

− lines

+17

no TV signal see Fig.16 0 − 2V
TV signal see Fig.16 4 −−V
slow time constant on 5 − 6.2 V

to V19 or V12)

4

voltage pin 4, if no signal is identified I4= 1 mA 0 − 0.3 V

I

= 5 mA 0 0.2 0.8 V

4

voltage pin 4, if signal is identified −−V19V
leakage current −−50 µA

no signal at pin 20 − 1.5 − V
noise at input pin 20 − 3 − V
switching T3to T1 (delay 7 fields) − 2.5 − V
switching T3 to T

1

− 2.5 − V

(noise and signal at input pin 20)
release V-divider − 4 − V
hysteresis −−0.2 − V
release time constant normal (T2)

− 5 − V

signal identification at pin 4
hysteresis −−0.2 − V
release noise detector − 6.5 − V

September 1993 11

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.3 Sync output.

Fig.4 Pin 15 circuit for (a) internal VCO; (b) external VCO.

Fig.5 Clock output.

September 1993 12

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.6 Time relationship of pin 10/11 to pin 13/20.

September 1993 13

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.7 Time relationship pin 10 to pin 20.

Fig.8 50/60 Hz output.

Fig.9 Sandcastle output.

September 1993 14

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September 1993 15

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

VP(V) R2 (kΩ)

5 5.1
8 8.2

(1) control range VCO 4%; see CHARACTERISTICS.
(2) depending on H output shift; see CHARACTERISTICS.

Fig.10 Application diagram.

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September 1993 16

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

VP(V) R2 (kΩ)

5 5.1
8 8.2

(1) control range VCO 4%; see CHARACTERISTICS.
(2) depending on H output shift; see CHARACTERISTICS.

Fig.11 TDA4691 with external VCO and prescaler.

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.12 H-timing overview.

September 1993 17

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September 1993 18

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.13 V-timing at 50 Hz operation.

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September 1993 19

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.14 V-timing at 60 Hz operation.

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.15 Control of operation states by voltage at pin 2.

September 1993 20

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.16 Control of signal identification (pin 4) and time constants by voltage at pin 5.

September 1993 21

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

Fig.17 V-timing.

September 1993 22

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

PACKAGE OUTLINES

DIP20: plastic dual in-line package; 20 leads (300 mil)

D

seating plane

L

Z

20

pin 1 index

e

b

SOT146-1

M

E

A

2

A

A

1

w M

b

1

11

E

c

(e )

1

M

H

1

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE
VERSION

SOT146-1

1 2

min.

max.

1.73

1.30

0.068

0.051

IEC JEDEC EIAJ

b

b

1

0.53

0.38

0.021

0.015

0.36

0.23

0.014

0.009

REFERENCES

cD E e M

(1) (1)

26.92

26.54

1.060

1.045

SC603

September 1993 23

6.40

6.22

0.25

0.24

10

(1)

M

e

L

1

3.60

8.25

3.05

7.80

0.14

0.32

0.12

0.31

EUROPEAN

PROJECTION

H

E

10.0

0.2542.54 7.62

8.3

0.39

0.010.10 0.30

0.33

ISSUE DATE

w

92-11-17
95-05-24

Z

max.

2.04.2 0.51 3.2

0.0780.17 0.020 0.13

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

SO20: plastic small outline package; 20 leads; body width 7.5 mm

D

c

y

Z

20

pin 1 index

1

e

11

A

2

10

w M

b

p

SOT163-1

E

H

E

Q

A

1

L

p

L

detail X

(A )

A

X

v M

A

A

3

θ

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

mm

OUTLINE

VERSION

SOT163-1

A

max.

2.65

0.10

A

1

0.30

0.10

0.012

0.004

A2A

2.45

2.25

0.096

0.089

IEC JEDEC EIAJ

075E04 MS-013AC

0.25

0.01

b

3

p

0.49

0.32

0.36

0.23

0.019

0.013

0.014

0.009

UNIT

inches

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

(1)E(1) (1)

cD

13.0

7.6

7.4

0.30

0.29

1.27

0.050

12.6

0.51

0.49

REFERENCES

September 1993 24

eHELLpQ

10.65

10.00

0.419

0.394

1.4

0.055

1.1

0.4

0.043

0.016

1.1

1.0

0.043

0.039

PROJECTION

0.25

0.25 0.1

0.01

0.01

EUROPEAN

ywv θ

Z

0.9

0.4

8

0.004

ISSUE DATE

0.035

0.016

95-01-24
97-05-22

0

o
o

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

DIP

SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

SO

REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO

packages.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

AVE SOLDERING

W
Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

R

EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

September 1993 25

Philips Semiconductors Preliminary specification

Sync Processor with Clock (SPC) TDA4691

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

September 1993 26