Datasheet TDA4686WP, TDA4686 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA4686

Video processor with automatic
cut-off control

Product specification
Supersedes data of May 1993
File under Integrated Circuits, IC02

1997 Jun 23

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

FEATURES

• Intended for double line frequency application
(100/120 Hz)

• Operates from an 8 V DC supply

• Black level clamping of the colour difference, luminance

and RGB input signals with coupling-capacitor DC level
storage

• Two analog RGB inputs, selected either by fast switch
signals or via I2C-bus; brightness and contrast control of
both RGB inputs

• Saturation, contrast, brightness and white adjustment

2

C-bus

via I

• Same RGB output black levels for Y/CD and RGB input
signals

• Timing pulse generation from either a 2 or 3-level
sandcastle pulse for clamping, vertical synchronization
and cut-off timing pulses

• Automatic cut-off control or clamped output selectable
via I2C-bus

• Automatic cut-off control with picture tube leakage
current compensation

• Cut-off measurement pulses after end of the vertical
blanking pulse or end of an extra vertical flyback pulse

• Increased RGB signal bandwidths

• Two switch-on delays to prevent discolouration before

steady-state operation

• Average beam current and peak drive limiting

• PAL/SECAM or NTSC matrix selection via I2C-bus

• Emitter-follower RGB output stages to drive the video

output stages

• I2C-bus controlled DC output e.g. for hue-adjust of
NTSC (multistandard) decoders

• No delay of clamping pulse

• Large luminance, colour difference and RGB bandwidth.

The required input signals are:

• Luminance and negative colour difference signals

• 2 or 3-level sandcastle pulse for internal timing pulse

generation

2

C-bus data and clock signals for microcontroller

• I
control.

Two sets of analog RGB colour signals can also be
inserted, e.g. one from a peritelevision connector and the
other from an on-screen display generator. The TDA4686
includes full I2C-bus control of all parameters and
functions with automatic cut-off control of the picture tube
cathode currents. It provides RGB output signals for the
video output stages.

The TDA4686 is a simplified, pin compatible (except for
pin 18) version of the TDA4680. The module address via
I2C-bus can be used for both ICs; where a function is not
included in the TDA4686 the I2C-bus command is not
executed. The differences with the TDA4680 are:

• No automatic white level control; the white levels are
determined directly by the I2C-bus data

• RGB reference levels for automatic cut-off control are
not adjustable via I2C-bus

• No clamping delay

• Only contrast and brightness adjust for the RGB input

signals

• The measurement lines are triggered either by the
trailing edge of the vertical component of the sandcastle
pulse or by the trailing edge of an optional external
vertical flyback pulse (on pin 18), according to which
occurs first.

GENERAL DESCRIPTION

The TDA4686 is a monolithic integrated circuit with a
luminance and a colour difference interface for video
processing in TV receivers. Its primary function is to
process the luminance and colour difference signals from
a colour decoder which is equipped e.g. with the
multistandard decoder TDA4655 or TDA9160 plus delay
line TDA4661 and the Picture Signal Improvement (PSI)
IC, TDA467X, or from a feature module.

1997 Jun 23 2

The TDA4685 is like TDA4686 but intended for normal line
frequency application.

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V

P

I

P

V

8(p-p)

V

6(p-p)

V

7(p-p)

V

14

V

i(p-p)

V

o(b-w)

T

amb

supply voltage (pin 5) 7.2 8.0 8.8 V
supply current (pin 5) − 60 − mA
luminance input (peak-to-peak value) − 0.45 − V

−(B − Y) input (peak-to-peak value) − 1.33 − V

−(R − Y) input (peak-to-peak value) − 1.05 − V

3-level sandcastle pulse

H+V − 2.5 − V
H − 4.5 − V
BK − 8.0 − V

2-level sandcastle pulse

H+V − 2.5 − V
BK − 4.5 − V

RGB input signals at pins 2, 3, 4, 10, 11and12

− 0.7 − V

(peak-to-peak value)
RGB outputs at pins 24, 22 and 20 (black-to-white value) − 2.0 − V
operating ambient temperature 0 − 70 °C

ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

TDA4686 DIP28 plastic dual in-line package; 28 leads (600 mil) SOT117-1
TDA4686WP PLCC28 plastic leaded chip carrier; 28 leads SOT261-2

1997 Jun 23 3

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

BLOCK DIAGRAM

RGB

outputs

O

O

R

G

242220

OUTPUT

ADJUST,

CUT-OFF

R

G

O

B

STAGES

B

MED715

21 23 25

R

GB

cut-off storage

leakage

and cut-off

current input

cut-off

control

19

C

R

CUT-OFF

COMPARATORS

leakage

storage

17

peak drive

limiting

storage

16

average

beam

15

current

BCOF

6-BIT D/A

hue control voltage

26

A45 to A40, A55 to A50, A65 to A60

AA5 to AA0

C-BUS

2

I

RECEIVER

27

28

SDA

SCL

C-bus

2

I

AND

AVERAGE

TIMING

GENERATOR

(H)

H + V

PULSE

DETECTOR

SC5

PEAK DRIVE

timing

pulses

BCOF

FSDIS2, FSON2,

2 x 8-BIT

CONTROL

CONVERTER

DELAYS

SWITCH-ON

1ST AND 2ND

BK

TDA4686

A05 to A00, A15 to A10, A25 to A20, A35 to A30

BREN

18

VFB

14

sandcastle

SANDCASTLE

pulse

3 x 6-BIT

LIMITING

BEAM CURRENT

4 x 6-BIT

FSDIS1, FSON1

NMEN

REGISTERS

101112

13

1

1

R

FSW

D/A

CONVERTERS

D/A

CONVERTERS

1

1

B

G

POINT

WHITE

ADJUST

B

R

G

ADJUST,

BLANKING 2,

BRIGHTNESS

MEASUREMENT
B

R

G

ADJUST

CONTRAST

B

R

G

BLANKING 1

FAST SIGNAL

SOURCE SWITCH,

B

R

G

NTSC

MATRIX

PAL/SECAM,

SATURATION

8

7

6

Y

−(R − Y)

−(B − Y)

PULSES

ADJUST

1
2

FSW

9

5

= 8 V

P

SUPPLY

V

handbook, full pagewidth

Fig.1 Block diagram.

C-bus data and

2

control signals

I

2

3

4

2

2

2

B

R

G

1997 Jun 23 4

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

PINNING

SYMBOL PIN DESCRIPTION

FSW
R

2

G

2

B

2

V

P

2

1 fast switch 2 input
2 red input 2
3 green input 2
4 blue input 2
5 supply voltage

−(B − Y) 6 colour difference input −(B − Y)

−(R − Y) 7 colour difference input −(R − Y)

Y 8 luminance input
GND 9 ground
R

1

G

1

B

1

FSW

1

10 red input 1
11 green input 1
12 blue input 1

13 fast switch 1 input
SC 14 sandcastle pulse input
BCL 15 average beam current limiting input

SYMBOL PIN DESCRIPTION

C

PDL

16 storage capacitor for peak drive

limiting

C

L

17 storage capacitor for leakage current
VFB 18 vertical flyback pulse input
CI 19 cut-off measurement input
B

O

C

B

G

O

C

G

R

O

C

R

20 blue output

21 blue cut-off storage capacitor

22 green output

23 green cut-off storage capacitor

24 red output

25 red cut-off storage capacitor
HUE 26 hue control output
SDA 27 I

2

C-bus serial data input;

acknowledge output

SCL 28 I

2

C-bus serial clock input

handbook, halfpage

Fig.2 Pin configuration (DIP-version).

FSW

R
G
B
V

−(B − Y)

−(R − Y)

GND

R
G
B

FSW

SC

2
2
2
2

P

Y

1
1
1
1

1
2
3
4
5
6
7
8

9
10
11
12
13
14

TDA4686

MED716

SCL

28

SDA

27

HUE

26

C

25

R

R

24

O

C

23

G

G

22

O

C

21

B

B

20

O

CI

19

VFB

18

C

17

L

C

16

PDL

BCL

15

V

−(B − Y)

−(R − Y)

GND

R
G

5

P

6
7

Y

8
9

10

1

11

1

B2G2R2FSW2SCL
4

3

2

1

28

TDA4686WP

12

13

14

15

1

1

B

SC

FSW

16

BCLCPDL

SDA
27

17

L

C

HUE
26

18

VFB

25
24
23
22
21
20
19

MED717

C

R

R

O

C

G

G

O

C

B

B

O

CI

Fig.3 Pin configuration (PLCC-version).

1997 Jun 23 5

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

2

I2C-BUS PROTOCOL

I

C-BUS RECEIVER (MICROCONTROLLER WRITE MODE)

Control

2

C-bus transmitter provides the data bytes to select

The I
and adjust the following functions and parameters:

• Brightness adjust

• Saturation adjust

• Contrast adjust

• DC output e.g. for hue control

• RGB gain adjust

• Peak drive limiting level adjust

• Selects either 3-level or 2-level (5 V) sandcastle pulse

• Enables cut-off control; enables output clamping

• Selects either PAL/SECAM or NTSC matrix

• Enables/disables synchronization of the execution of

I2C-bus commands with the vertical blanking interval

• Enables Y/CD, RGB1 or RGB2 input.

2

C-bus transmitter and data transfer

I

2

I

C-BUS SPECIFICATION

The I2C-bus is a bidirectional, two-wire, serial data bus for
intercommunication between ICs in an equipment.
The microcontroller transmits data to the I2C-bus receiver
in the TDA4686 over the serial data line SDA (pin 27)
synchronized by the serial clock line SCL (pin 28). Both
lines are normally connected to a positive voltage supply
through pull-up resistors. Data is transferred when the
SCL line is LOW. When SCL is HIGH the serial data line
SDA must be stable. A HIGH-to-LOW transition of the SDA
line when SCL is HIGH is defined as a START bit.
A LOW-to-HIGH transition of the SDA line when SCL is
HIGH is defined as a STOP bit.

Each transmission to the I2C-bus receiver consists of at
least three bytes following the START bit. Each byte is
acknowledged by an acknowledge bit immediately
following each byte. The first byte is the Module Address
(MAD) byte, also called slave address byte. This includes
the module address, 1000100 for the TDA4686.
The TDA4686 is a slave receiver (R/W = 0), therefore the
module address byte is 10001000 (88H; see also Fig.4).

The length of a data transmission is unrestricted, but the
module address and the correct subaddress must be
transmitted before the data byte(s). The order of data
transmission is shown in Figs 5 and 6.
Without auto-increment (BREN = 0 or 1) the module
address (MAD) byte is followed by a SubAddress (SAD)
byte and one data byte only (see Fig.5).

Each transmission must start with a START bit and end
with a STOP bit. The bus is busy after a START bit and is
only free again after a STOP bit has been transmitted.

1997 Jun 23 6

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

handbook, full pagewidth

handbook, full pagewidth

MSB LSB

01

module address

00100

Fig.4 The module address byte.

STOSAD

STOP

condition

START

condition

MADSTA

data byte

ACK0

R/W

MED710

MED697

Fig.5 Data transmission without auto-increment (BREN = 0 or 1).

handbook, full pagewidth

START

condition

MADSTA

SAD

data byte

Fig.6 Data transmission with auto-increment (BREN = 0).

1997 Jun 23 7

data bytes

STO

STOP

condition

MED698

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

AUTO-INCREMENT
The auto-increment format enables quick slave receiver

initialization by one transmission, when the I2C-bus control
bit BREN = 0 (see control register bits of Table 1).
If BREN = 1 auto-increment is not possible.

If the auto-increment format is selected, the MAD byte is
followed by a SAD byte and by the data bytes of
consecutive subaddresses (see Fig.6).

All subaddresses from 00H to 0FH are automatically
incremented, the subaddress counter wraps round from
0FH to 00H. Reserved subaddresses 07H, 08H, 09H,
0BH, 0EH and 0FH are treated as legal but have no effect.
Subaddresses outside the range 00H and 0FH are not
acknowledged by the device.

Subaddresses are stored in the TDA4686 to address the
following parameters and functions (see Table 1):

• Brightness adjust

• Saturation adjust

• Contrast adjust

• Hue control voltage

• RGB gain adjust

• Peak drive limiting adjust

• Control register functions.

ONTROL REGISTER 2

C
FSON2 (Fast Switch 2 ON).
FSDIS2 (Fast Switch 2 Disable).
FSON1 (Fast Switch 1 ON).
FSDIS1 (Fast Switch 1 Disable).
The RGB input signals are selected by FSON2 and

FSON1 or FSW2 and FSW1:

• FSON2 has priority over FSON1

• FSW2 has priority over FSW

• FSDIS1 and FSDIS2 disable FSW1 and FSW

1

2

(see Table 2).

BCOF (Black level Control Off):

0 = automatic cut-off control enabled
1 = automatic cut-off control disabled; RGB outputs are

clamped to fixed DC levels.

When the supply voltage has dropped below
approximately 6.0 V (usually occurs when the TV receiver
is switched on or the supply voltage is interrupted) all data
and function bits are set to 01H.

The data bytes D7 to D0 (see Table 1) provide the data of
the parameters and functions for video processing.

C

ONTROL REGISTER 1

NMEN (NTSC Matrix Enable):

0 = PAL/SECAM matrix
1 = NTSC matrix.

BREN (Buffer Register Enable):

0 = new data is executed as soon as it is received
1 = data is stored in buffer registers and is transferred to

the data registers during the next vertical blanking
interval.

The I2C-bus receiver does not accept any new data until
this data is transferred into the data registers.

SC5 (SandCastle 5 V):

0 = 3-level sandcastle pulse
1 = 2-level (5 V) sandcastle pulse.

1997 Jun 23 8

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

Table 1 Subaddress (SAD) and data bytes; note 1

FUNCTION

Brightness 00 0 0 A05 A04 A03 A02 A01 A00
Saturation 01 0 0 A15 A14 A13 A12 A11 A10
Contrast 02 0 0 A25 A24 A23 A22 A21 A20
Hue control voltage 03 0 0 A35 A34 A33 A32 A31 A30
Red gain 04 0 0 A45 A44 A43 A42 A41 A40
Green gain 05 0 0 A55 A54 A53 A52 A51 A50
Blue gain 06 0 0 A65 A64 A63 A62 A61 A60
Reserved 07 0 0 X X X X X X
Reserved 08 0 0 X X X X X X
Reserved 09 0 0 X X X X X X
Peak drive limit 0A 0 0 AA5 AA4 AA3 AA2 AA1 AA0
Reserved 0B X X X X X X X X
Control register 1 0C SC5 X BREN X NMEN X X X
Control register 2 0D X X X BCOF FSDIS2 FSON2 FSDIS1 FSON1
Reserved 0E X X X X X X X X
Reserved 0F X X X X X X X X

Note

1. X = don’t care, but for software compatibility with other or future video ICs it is recommended to set all X to logic 0.

SAD

(HEX)

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

1997 Jun 23 9

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

Table 2 Signal input selection by the fast source switches; notes 1 to 4

2

C-BUS CONTROL BITS ANALOG SWITCH SIGNALS INPUT SELECTED

I

FSON2 FSDIS2 FSON1 FSDIS1

FSW

(PIN 1)

2

FSW

1

(PIN 13)

RGB

2

RGB

1

Y/CD

LLLL L L ON

LH ON
HXON

LLLH L X ON

HXON

LLHX L X ON

HXON

LHLL X L ON

XH ON
LHLH X X ON
LHHX X X ON

HXXX X X ON

Notes

1. H: logic HIGH implies that the voltage >0.9 V.

2. L: logic LOW implies that the voltage <0.4 V.

3. X = don’t care.

4. ON indicates the selected input signal.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

P

V

i

supply voltage (pin 5) − 8.8 V
input voltage (pins 1 to 8, 10 to 13, 16, 21, 23 and 25) −0.1 +V
input voltage (pins 15, 18 and 19) −0.7 V

P

+ 0.7 V

P

input voltage (pins 27 and 28) −0.1 +8.8 V

V

14

I

av

I

M

I

26

T

stg

T

amb

P

tot

sandcastle pulse voltage −0.7 VP+ 5.8 V
average current (pins 20, 22 and 24) −10 +4 mA
peak current (pins 20, 22 and 24) −20 +4 mA
output current −8 +0.6 mA
storage temperature −20 +150 °C
operating ambient temperature 0 70 °C
total power dissipation

SOT117-1 − 1.2 W
SOT261-2 − 1.0 W

V

1997 Jun 23 10

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

CHARACTERISTICS

All voltages are measured in test circuit of Fig.10 with respect to GND (pin 9); VP= 8.0 V; T
amplitudes (black-to-white) at output pins 24, 22 and 20; nominal settings of brightness, contrast, saturation and white
level control; without beam current or peak drive limiting; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pin 5)

V

P

I

P

supply voltage 7.2 8.0 8.8 V
supply current − 60 − mA

Colour difference inputs [−(B − Y): pin 6; −(R − Y): pin 7]

V

6(p-p)

V

7(p-p)

V

6,7

I

 input current during line scan −− 0.1 µA

6,7

−(B − Y) input (peak-to-peak value) notes 1 and 2 − 1.33 − V

−(R − Y) input (peak-to-peak value) notes 1 and 2 − 1.05 − V

internal DC bias voltage at black level clamping − 4.1 − V

at black level clamping 100 −−µA

R

6,7

input resistance 10 −−MΩ

Luminance/sync (VBS; Y: pin 8)

V

i(p-p)

luminance input voltage at pin 8

note 2 − 0.45 − V

(peak-to-peak value)

V

8(bias)

I

 input current during line scan −− 0.1 µA

8

internal DC bias voltage at black level clamping − 4.1 − V

at black level clamping 100 −−µA

R

8

RGB input 1 (R

V

i(p-p)

input resistance 10 −−MΩ

: pin 10; G1: pin 11; B1: pin 12)

1

input voltage at pins 10, 11and12

note 2 − 0.7 − V

(peak-to-peak value)

V

10/11/12(bias)

I

10/11/12

internal DC bias voltage at black level clamping − 5.7 − V

 input current during line scan −− 0.1 µA

at black level clamping 100 −−µA

R

10/11/12

RGB input 2 (R

V

i(p-p)

input resistance 10 −−MΩ

: pin 2, G2: pin 3, B2: pin 4)

2

input voltage at pins 2, 3 and 4

note 2 − 0.7 − V

(peak-to-peak value)

V

2/3/4

I

 input current during line scan −− 0.1 µA

2/3/4

internal DC bias voltage at black level clamping − 5.7 − V

at black level clamping 100 −−µA

R

2/3/4

input resistance 10 −−MΩ

=25°C; nominal signal

amb

1997 Jun 23 11

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Fast signal switch FSW1 (pin 13) to select Y, CD or R1, G1, B1 inputs (control bits: see Table 2)

V

13

R

13

∆t difference between transit times for

voltage to select Y and CD −− 0.4 V
voltage to select R

, G1, B

1

1

0.9 − 5.0 V

internal resistance to ground − 4.0 − kΩ

−− 10 ns

signal switching and signal insertion

Fast signal switch FSW

V

1

voltage to select Y, CD/R1, G1, B
voltage to select R

R

1

internal resistance to ground − 4.0 − kΩ

∆t difference between transit times for

(pin 1) to select Y, CD/R1, G1, B1 or R2, G2, B2 inputs (control bits: see Table 2)

2

−− 0.4 V

0.9 − 5.0 V

, G2, B

2

1

2

−− 10 ns

signal switching and signal insertion

Saturation adjust [acts on −(R − Y) and −(B − Y) signals under I

2

C-bus control; subaddress 01H (bit resolution

1.5% of maximum saturation); data byte 3FH for maximum saturation, data byte 23H for nominal saturation
and data byte 00H for minimum saturation]

d

s

saturation below maximum at 23H − 5 − dB

at 00H; f = 100 kHz − 50 − dB

Contrast adjust [acts on internal RGB signals under I

2

C-bus control; subaddress 02H (bit resolution 1.5% of
maximum contrast); data byte 3FH for maximum contrast, data byte 22H for nominal contrast and data byte
00H for minimum contrast]

d

c

contrast below maximum at 22H − 5 − dB

at 00H − 22 − dB

Brightness adjust [acts on internal RGB signals under I

2

C-bus control; subaddress 00H (bit resolution 1.5%
of maximum brightness); data byte 3FH for maximum brightness, data byte 26H for nominal brightness and
data byte 00H for minimum brightness]

d

br

black level shift of nominal signal
amplitude referred to cut-off

at 3FH − 30 − %
at 00H −−50 − %

measurement level

2

White potentiometers [under I

C-bus control; subaddresses 04H (red), 05H (green) and 06H (blue); data byte

3FH for maximum gain; data byte 19H for nominal gain and data byte 00H for minimum gain]; note 3

∆G

v

relative to nominal gain

increase of gain at 3FH − 50 − %
decrease of gain at 00H − 50 − %

1997 Jun 23 12

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

RGB outputs (pins 24, 22 and 20; positive going output signals; peak drive limiter set = 3FH); note 4

V

o(b-w)

nominal output signals
(black-to-white value)

maximum output signals
(black-to-white value)

∆V

o

V

o

spread between RGB output signals −− 10 %
minimum output voltages −− 0.8 V
maximum output voltages 6.8 −−V

V

24,22,20

voltage of cut-off measurement line
equivalent to voltage during

output clamping;
BCOF = 1

ultra-black

I

int

R

o

internal current sources − 5.0 − mA
output resistance − 20 −Ω

Frequency response (measured with 10 MΩ, 30 pF external load)

f

res

frequency response of Y path

f = 14 MHz −− 3dB

(from pin 8 to pins 24, 22 and 20)
frequency response of CD path

f = 12 MHz −− 3dB

(from pins 7 to 24 and 6 to 20)
frequency response of RGB1 path

f = 22 MHz −− 3dB
(from pins 10 to 24, 11to22 and
12 to 20)

frequency response of RGB

path

2

f = 22 MHz −− 3dB
(from pins 2 to 24, 3 to 22 and
4 to 20)

− 2.0 − V

3.0 −−V

2.3 2.5 2.7 V

Sandcastle pulse detector (pin 14)

C

ONTROL BIT SC5 = 0; 3-LEVEL; notes 5 and 6

V

14

sandcastle pulse voltage

for horizontal and vertical blanking
pulses

for horizontal pulses (line count) 4.0 4.5 5.0 V

for burst key pulses (clamping) 7.6 − V
CONTROL BIT SC5 = 1; 2-LEVEL; notes 5 and 6
V

14

sandcastle pulse voltage

for horizontal and vertical blanking

pulses

for burst key pulses 4.0 4.5 VP+ 5.8 V
GENERAL
I

14

t

d

output current V14=0V −− −100 µA
leading edge delay of the clamping

pulse

1997 Jun 23 13

2.0 2.5 3.0 V

+ 5.8 V

P

2.0 2.5 3.0 V

− 0 −µs

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Vertical flyback (pin 18); note 6

V

18

I

18

Average beam current limiting (pin 15); note 8
V

c(15)

∆V

c(15)

V

br(15)

∆V

br(15)

vertical flyback pulse for LOW −− 2.5 V

for HIGH 4.5 −−V

internal voltage pin 18 open-circuit;

− 5.0 − V

note 7

input current −− 5µA

contrast reduction starting voltage − 4.0 − V
voltage difference for full contrast

−−2.0 − V

reduction
brightness reduction starting voltage − 2.5 − V
voltage difference for full brightness

−−1.6 − V

reduction

Peak drive limiting voltage [pin 16; internal peak drive limiting level (V
control; subaddress 0AH]; note 9

V

20,22,24

minimum RGB output voltages at 00H −− 3.0 V
maximum RGB output voltages at 3FH 7.0 −−V

I

16

charge current −−1−µA
discharge current during peak white − 5 − mA

V

16

V

c(16)

∆V

c(16)

internal voltage limitation 4.5 −−V
contrast reduction starting voltage − 4.0 − V
voltage difference for full contrast

reduction
V
∆V

br(16)

br(16)

brightness reduction starting voltage − 2.5 − V

voltage difference for full brightness

reduction
Automatic cut-off control (pin 19); notes 6 and 10 to 12; see Fig.8
V

19

I

19

external voltage −− V

output current −− −60 µA

input current 150 −−µA

additional input current switch-on delay 1 − 0.5 − mA
V

24,22,20

V

19(th)

monitor pulse amplitude (under

I2C-bus control; subaddress 0AH)

voltage threshold for picture tube

switch-on delay 1;
note 11

switch-on delay 1 − 4.5 − V

cathode warming up
V

ref

internally controlled voltage during leakage

measurement period

∆V

19

difference between V

MEAS

(cut-off

measurement voltage) and V

ref

) acts on RGB outputs under I2C-bus

pdl

−−2.0 − V

−−1.6 − V

−1.4 V

P

− V

− 1.0 − V

pdl

− 2.7 − V

− 1.0 − V

1997 Jun 23 14

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Cut-off storage (pins 25, 23 and 21)

I

 charge and discharge currents during cut-off

21,23,25

measurement lines

input currents of storage inputs outside measurement

time

Storage of leakage information (pin 17)

I

 charge and discharge currents during leakage

17

measurement period

leakage current outside measurement

time

V

17

threshold voltage for reset to

switch-on state

2

Hue control (under I

C-bus control; subaddress 03H; data byte 3FH for maximum voltage; data byte 20H for

nominal voltage and data byte 00H for minimum voltage); note 13

V

26

output voltage at 3FH 4.8 −−V

at 20H − 3.0 − V
at 00H −− 1.2 V

I

int

current of the internal current source

at pin 26

2

I

C-bus receiver clock SCL (pin 28)

f

SCL

V

IL

V

IH

I

IL

I

IH

t

L

t

H

t

r

t

f

2

C-bus receiver data input/output SDA (pin 27)

I

V

IL

V

IH

I

IL

I

IH

I

OL

t

r

t

f

t

SU;DAT

input frequency range 0 − 100 kHz

LOW-level input voltage −− 1.5 V

HIGH-level input voltage 3.0 − 6.0 V

LOW-level input current −− −10 µA

HIGH-level input current −− 10 µA

clock pulse LOW 4.7 −−µs

clock pulse HIGH 4.0 −−µs

rise time −− 1.0 µs

fall time −− 0.3 µs

LOW-level input voltage −− 1.5 V

HIGH-level input voltage 3.0 − 6.0 V

LOW-level input current −− −10 µA

HIGH-level input current −− 10 µA

LOW-level output current 3.0 −−mA

rise time −− 1.0 µs

fall time −− 0.3 µs

data set-up time 0.25 −−µs

− 0.3 − mA

−− 0.1 µA

− 0.4 − mA

−− 0.1 µA

− 2.5 − V

500 −−µA

1997 Jun 23 15

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

Notes to the characteristics

1. The values of the −(B − Y) and −(R − Y) colour difference input signals are for a 75% colour-bar signal.

2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600 Ω.

3. The white potentiometers affect the amplitudes of the RGB output signals.

4. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources.

5. Sandcastle pulses are compared with internal threshold voltages independent of V
separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14
exceeds the defined internal threshold voltage.
The internal threshold voltages (control bit SC5 = 0) are:

1.5 V for horizontal and vertical blanking pulses

3.5 V for horizontal pulses

6.5 V for the burst key pulse.

The internal threshold voltages (control bit SC5 = 1) are:

1.5 V for horizontal and vertical blanking pulses

3.5 V for the burst key pulse.

6. Vertical signal blanking is determined by the vertical component of the sandcastle pulse. The leakage and the RGB
cut-off measurement lines are positioned in the first four complete lines after the end of the vertical component.
In this case, the RGB output signals are blanked until the end of the last measurement line; see Fig.8a. If an extra
vertical flyback pulse VFB is applied to pin 18, the four measurement lines start in the first complete line after the end
of the VFB pulse; see Fig.8b. In this case, the output signals are blanked either until the end of the last measurement
line or until the end of the vertical component of the sandcastle pulse, according to which occurs last.

7. If no VFB pulse is applied, pin 18 can be left open-circuit or connected to V
automatic cut-off control nor output clamping can happen.

8. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness.

9. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness.
The maximum RGB outputs are determined via the I2C-bus under subaddress 0AH. When an RGB output exceeds
the maximum voltage, peak drive limiting is delayed by one horizontal line.

10. During leakage current measurement, the RGB channels are blanked to ultra-black level. During cut-off
measurement one channel is set to the measurement pulse level, the other channels are blanked to ultra-black.
Since the brightness adjust shifts the colour signal relative to the black level, the brightness adjust is disabled during
the vertical blanking interval (see Figs 7 and 8).

11. During picture cathode warming up (first switch-on delay) the RGB outputs (pins 24, 22 and 20) are blanked to the
ultra-black level during line scan. During the vertical blanking interval a white-level monitor pulse is fed out on the
RGB outputs and the cathode currents are measured. When the voltage threshold on pin 19 is greater than 4.5 V,
the monitor pulse is switched off and cut-off control is activated (second switch-on delay). As soon as cut-off control
stabilizes, RGB output blanking is removed.

12. Range of cut-off measurement level at the RGB outputs is 1 to 5 V. The recommended value is 3 V.

13. The hue control output at pin 26 is an emitter follower with current source.

. If pin 18 is always LOW neither

P

. The threshold voltages

P

1997 Jun 23 16

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

Table 3 Demodulator axes and amplification factors

PARAMETER NTSC PAL

(B − Y)* demodulator axis 0° 0°
(R − Y)* demodulator axis 115° 90°
(R − Y)* amplification factor 1.97 1.14
(B − Y)* amplification factor 2.03 2.03

Table 4 PAL/SECAM and NTSC matrix; note 1

MATRIX NMEN

PAL/SECAM 0

NTSC 1

Note

1. PAL/SECAM signals are matrixed by the equation: V
NTSC signals are matrixed by the equations (hue phase shift of −5 degrees):
V

= 1.57V

R − Y*

In the matrix equations: V
the NTSC demodulator. V

R − Y

− 0.41V

B − Y
R − Y
G − Y*

; V

G − Y*

and V

, V

R − Y*

= −0.43V

are conventional PAL demodulation axes and amplitudes at the output of

B − Y

and V

R − Y

are the NTSC modified colour difference signals; this is equivalent

B − Y*

to the demodulator axes and amplification factors shown in Table 3. V

G −Y

− 0.11V

= −0.51V

B − Y

− 0.19V

R − Y

; V

B − Y*=VB−Y

G − Y*

B − Y

= −0.27V

R − Y*

− 0.22V

B − Y*

.

handbook, full pagewidth

cut-off measurement line

for red signal

(1) Maximum brightness. (2) Nominal brightness.

MHA697

(1)

(2)

ultra-black

Fig.7 Cut-off measurement pulse.

1997 Jun 23 17

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

handbook, full pagewidth

sandcastle pulse

with vertical

component

R channel

LM

MR

G channel

B channel

vertical flyback

handbook, full pagewidth

pulse (VFB)

R channel

G channel

LM

LM

a. Timing controlled by sandcastle pulse.

MR

MG

LM

LM

MG

MB

MHA698

B channel

LM

MB

b. Timing controlled by additional vertical flyback pulse (VFB).

LM = leakage current measurement time.
MR, MG, MB = R, G, B cut-off measurement pulses.

Fig.8 Leakage and cut-off current measurement timing diagram.

1997 Jun 23 18

MHA699

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

INTERNAL PIN CONFIGURATION

+

17

MED718

8765 12 13 141110943

TDA4686

23 22 21 20 19 1825 24262728 1516

1997 Jun 23 19

Fig.9 Internal circuits.

handbook, full pagewidth

+

+

2

CL CL CL CLCLCLCLCLCL

1

diode protection

on all pins except

pins 5, 14, 27 and 28

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

TEST AND APPLICATION INFORMATION

SCL SDA hue

100 Ω

SCL

1

2

FSW

200 V

1

100 Ω

SDA

272826

2

2

R

10 nF

+12 V

2

HUE

3

2

G

10 nF

3

220 nF

R

C

25

4

2

B

10 nF

GND

4

O

R

24

5

P

V

10 nF

5

220 nF

G

C

23

6

−(B − Y)

10 nF

O

R

6

O

G

22

7

−(R − Y)

10 nF

GOBOCI

8

7

220 nF

B

O

C

B

21

20

TDA4686

8

9

Y

GND

47 nF

9

CI

19

10

1

R

10 nF

10

VFB

18

11

1

G

10 nF

CON2

82

kΩ

330 nF

L

C

17

12

1

B

10 nF

BZX79

C6V2

1 µF

PDL

C

16

13

1

FSW

VFB

(optional)

BCL

15

14

SC

MED719

1N4148

1N4148

3.9 kΩ

22 µF

10

kΩ

(1)

BR1

3.9 kΩ

Fig.10 Test and application circuit.

Ω

75

Ω

75

Ω

75

Ω

75

2

FSW

handbook, full pagewidth

2

2

R

2

B

G

−(B − Y)

Y

−(R − Y)

1997 Jun 23 20

1G1B1

R

1

FSW

SC

Ω

75

Ω

75

Ω

75

22 µH

Ω

75

= 8 V

P

V

220 µF

beam

current

information

(1) Insert link BR1 if average beam current is not required.

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

PACKAGE OUTLINES

handbook, full pagewidth

DIP28: plastic dual in-line package; 28 leads (600 mil)

SOT117-1

seating plane

L

Z

28

1

pin 1 index

D

A

2

A

A

1

e

b

w M

b

1

15

E

14

c

M

(e )

M

E

1

H

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

A

A

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

mm

OUTLINE

VERSION

SOT117-1

1 2

min.

max.

1.7

1.3

0.066

0.051

IEC JEDEC EIAJ

051G05 MO-015AH

b

b

1

0.53

0.38

0.020

0.014

0.32

0.23

0.013

0.009

REFERENCES

cD E weM

(1) (1)

36.0

35.0

1.41

1.34

1997 Jun 23 21

14.1

13.7

0.56

0.54

(1)

92-11-17
95-01-14

Z

max.

1.75.1 0.51 4.0

0.0670.20 0.020 0.16

L

3.9

3.4

EUROPEAN

PROJECTION

M

E

15.80

15.24

0.62

0.60

H

17.15

15.90

0.68

0.63

0.252.54 15.24

0.010.10 0.60

ISSUE DATE

e

1

0.15

0.13

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

PLCC28: plastic leaded chip carrier; 28 leads

e

y

25

26

28

1

pin 1 index

4

β

k

511

E

X

19

e

Z

D

H

D

SOT261-2

e

E

A

Z

E

18

H

E

E

e

12

k

1

v M

A

A

A

1

A

4

D

B

v M

B

w M

detail X

b

p

b

1

(A )

3

L

p

0 5 10 mm

scale

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

UNIT A

mm

inches

A

1

min. max. max. max. max.

4.57

0.51

4.19

0.180

0.020

0.165

A

0.25

0.01

A

4

3

3.05

0.12

b

p

0.53

0.33

0.021

0.013

b

0.81

0.66

0.032

0.026

1

D

11.58

11.43

0.456

0.450

(1)

(1)

E

eH

11.58

1.27

11.43

0.456

0.05

0.450

e

10.92

9.91

0.430

0.390

e

E

D

12.57

10.92

12.32

9.91

0.495

0.430

0.485

0.390

Note

1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT261-2

1997 Jun 23 22

H

E

D

12.57

12.32

0.495

0.485

k

1.22

1.07

0.048

0.042

k

0.51

0.020

1

0.057

0.040

L

p

1.44

1.02

EUROPEAN

PROJECTION

(1) (1)

Z

Z

E

D

ywv β

0.18 0.100.18

0.007 0.0040.007

2.16

0.085

2.16

0.085

o

45

ISSUE DATE

92-11-17
95-02-25

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“IC Package Databook”

(order code 9398 652 90011).

DIP

SOLDERING BY DIPPING OR BY WA VE
The maximum permissible temperature of the solder is

260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T

stg max

). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

R

EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

WAVE SOLDERING
Wave soldering techniques can be used for all PLCC

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

PLCC

REFLOW SOLDERING
Reflow soldering techniques are suitable for all PLCC

packages.
The choice of heating method may be influenced by larger

PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

(order code 9397 750 00192).

“Quality

1997 Jun 23 23

EPAIRING SOLDERED JOINTS

R
Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2

PURCHASE OF PHILIPS I

C COMPONENTS

2

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

C components conveys a license under the Philips’ I2C patent to use the

1997 Jun 23 24

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

NOTES

1997 Jun 23 25

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

NOTES

1997 Jun 23 26

Philips Semiconductors Product specification

Video processor with automatic cut-off control TDA4686

NOTES

1997 Jun 23 27

Philips Semiconductors – a worldwide company

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
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Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

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TEL AVIV 61180, Tel. [phone], Fax. [phone]
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20124 MILANO, Tel. [phone], Fax. [phone]
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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
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106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
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Portugal: see Spain
Romania: see Italy
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Tel. [phone], Fax. [phone]
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TAIPEI, Taiwan Tel. [phone], Fax. [phone]

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209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications,
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1997 SCA54
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Printed in The Netherlands 547047/25/03/pp28 Date of release: 1997 Jun 23 Document order number: 9397 750 02046