Datasheet tda4685 DATASHEETS (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

TDA4685

Video processor with automatic cut-off control

Preliminary speciﬁcation File under Integrated Circuits, IC02

May 1993

Page 2

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

FEATURES

• Operates from an 8 V DC supply

• Black level clamping of the colour difference, luminance

and RGB input signals with coupling-capacitor DC level storage

• Two analog RGB inputs, selected either by fast switch signals or the I2C-bus; brightness and contrast control of these RGB inputs

• Saturation, contrast, brightness and white adjustment via I2C-bus

• Same RGB output black levels for Y/CD and RGB input signals

• Timing pulse generation from either a 2- or 3-level sandcastle pulse for clamping, vertical synchronization and cut-off timing pulses

• Automatic cut-off control or clamped output selectable via I2C-bus

• Automatic cut-off control with picture tube leakage current compensation

• Cut-off measurement pulses after end of the vertical blanking pulse or end of an extra vertical flyback pulse

• Two switch-on delays to prevent discolouration before steady-state operation

• Average beam current and peak drive limiting

• PAL/SECAM or NTSC matrix selection via I2C-bus

• Emitter-follower RGB output stages to drive the video

output stages

• I2C-bus controlled DC output e. g. for hue-adjust of NTSC (multistandard) decoders

GENERAL DESCRIPTION

The TDA4685 is a monolithic, integrated circuit with a luminance and a colour difference interface for video processing in TV receivers.

Its primary function is to process the luminance and colour difference signals from a colour decoder which is equipped e. g. with the multistandard decoder TDA4655 or TDA9160 plus delayline TDA4661 and the Picture Signal

TDA4685

Improvement (PSI) IC TDA467X or from a Feature Module. The required input signals are:

• luminance and negative colour difference signals

• 2- or 3-level sandcastle pulse for internal timing pulse

generation

C-bus data and clock signals for microprocessor

• I control.

Two sets of analog RGB colour signals can also be inserted, e.g. one from a peritelevision connector and the other from an on-screen display generator. The TDA4685 has I2C-bus control of all parameters and functions with automatic cut-off control of the picture tube cathode currents. It provides RGB output signals for the video output stages.

The TDA4685 is a simplified, pin compatible (except pin

18) version of the TDA4680. The module address via the

I2C-bus can be used for both ICs; where a function is not included in the TDA4685 then the I2C-bus command is not executed. The differences with the TDA4680 are:

• no automatic white level control; the white levels are determined directly by the I2C-bus data

• RGB reference levels for automatic cut-off control are not adjustable via I2C-bus

• clamping delay is fixed

• only contrast and brightness adjust for the RGB input

signals

• the measurement lines are triggered either by the trailing edge of the vertical component of the sandcastle pulse or by the trailing edge of an optional external vertical flyback pulse (on pin 18), according to which occurs first.

The TDA4686 is like TDA4685 but intended for double line frequency application.

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V I

V V V V

V V T

8(p-p) 6(p-p) 7(p-p) 14

i o(p-p) amb

supply voltage (pin 5) 7.2 8.0 8.8 V supply current (pin 5) − 60 − mA luminance input (peak-to-peak value) − 0.45 − V

−(B−Y) input (peak-to-peak value) − 1.33 − V

−(R−Y) input (peak-to-peak value) − 1.05 − V

three-level sandcastle pulse

H+V − 2.5 − V H − 4.5 − V BK − 8.0 − V

two-level sandcastle pulse

H + V − 2.5 − V

BK − 4.5 − V RGB input signals at pins 2, 3, 4, 10, 11 and 12 (black-to-white value) − 0.7 − V RGB outputs at pins 24, 22 and 20 (peak-to-peak value) − 2.0 − V operating ambient temperature 0 − +70 °C

ORDERING INFORMATION

PACKAGE

EXTENDED

TYPE NUMBER

PINS

POSITION

MATERIAL CODE

TDA4685 28 DIL plastic SOT117

Note

1. SOT117-1; 1996 November 25.

(1)

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

leakage

and cut-off

current input

hue control voltage



6-BIT D/A

cut-off

control

CUT-OFF

CONVERTER

leakage

storage

COMPARATORS

peak drive

limiting

storage

PEAK DRIVE

average

beam

current

AND

LIMITING

AVERAGE

BEAM CURRENT

D/A

3 x 6-BIT

CONVERTERS

BCOF

RGB

outputs

242220

OUTPUT

ADJUST,

CUT-OFF

POINT

WHITE

ADJUST

ADJUST,

BLANKING 2,

BRIGHTNESS

MEASUREMENT B

STAGES

PULSES

SUPPLY

MED708

21 23 25

TDA4685

cut-off storage

= 8 V

DELAYS

SWITCH-ON

1ST AND 2ND

A45 to A40, A55 to A50, A65 to A60

AA5 to AA0

C-BUS

TRANSCEIVER

SDA

SCL

C-bus

TDA4685

A05 to A00, A15 to A10, A25 to A20, A35 to A30

BREN

VFB

sandcastle

TIMING

GENERATOR

(H)

H + V

PULSE

DETECTOR

SANDCASTLE

SC5

pulse

timing

BCOF

FSDIS2, FSON2,

2 x 8-BIT

CONTROL

pulses

FSDIS1, FSON1

NMEN

REGISTERS

FSW

D/A

4 x 6-BIT

CONVERTERS

101112

ADJUST

CONTRAST

handbook, full pagewidth

Fig.1 Block diagram.

BLANKING 1

FAST SIGNAL

SOURCE SWITCH,

NTSC

MATRIX

PAL/SECAM,

C-bus data and

control signals

ADJUST

SATURATION

−(R−Y)

−(B−Y)

1 2

FSW

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

PINNING

SYMBOL PIN DESCRIPTION

FSW

−(B−Y) 6 colour difference input −(B−Y)

−(R−Y) 7 colour difference input −(R−Y)

Y 8 luminance input GND 9 ground R

FSW

SC 14 sandcastle pulse input BCL 15 average beam current limiting input C

PDL

CI 19 cut-off measurement input B

HUE 26 hue control output SDA 27 I SCL 28 I

1 fast switch 2 input 2 red input 2 3 green input 2 4 blue input 2 5 supply voltage

10 red input 1 11 green input 1 12 blue input 1 13 fast switch 1 input

16 storage capacitor for peak drive limiting 17 storage capacitor for leakage current 18 vertical ﬂyback pulse input

20 blue output 21 blue cut-off storage capacitor 22 green output 23 green cut-off storage capacitor 24 red output 25 red cut-off storage capacitor

C-bus serial data input / acknowledge output

C-bus serial clock input

lfpage

FSW

−(B−Y)

−(R−Y)

GND

FSW

Fig.2 Pin configuration.

TDA4685

MED709

SCL

SDA

HUE

PDL

BCL

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

I2C-BUS CONTROL

The I2C-bus transmitter provides the data bytes to select and adjust the following functions and parameters:

• brightness adjust

• saturation adjust

• contrast adjust

• DC output e. g. for hue control

• RGB gain adjust

• peak drive limiting level adjust

• selects either 3-level or 2-level

(5 V) sandcastle pulse

• enables cut-off control / enables output clamping

• selects either PAL/SECAM or NTSC matrix

• enables/disables synchronization of the execution of I2C-bus commands with the vertical blanking interval

• enables Y-CD, RGB1 or RGB2 input.

I2C-BUS TRANSMITTER AND DATA TRANSFER

C-bus speciﬁcation

The I2C-bus is a bi-directional, two-wire, serial data bus for intercommunication between ICs in an equipment. The microcontroller transmits data to the I2C-bus receiver in the TDA4685 over the serial data line SDA (pin 27) synchronized by the serial clock line SCL (pin 28). Both lines are normally connected to a positive voltage supply through pull-up resistors. Data is transferred when the SCL line is LOW. When SCL is HIGH the serial data line SDA must be stable. A HIGH-to-LOW transition of the SDA line when SCL is HIGH is defined as a start bit. A LOW-to-HIGH transition of the SDA line when SCL is HIGH is defined as a stop bit. Each transmission must start with a start bit and end with a stop bit. The bus is busy after a start bit and is only free again after a stop bit has been transmitted.

TDA4685

C-bus receiver

(microcontroller write mode) Each transmission to the I2C-bus receiver consists of at least three bytes following the start bit. Each byte is acknowledged by an acknowledge bit immediately following each byte. The first byte is the Module ADdress (MAD) byte, also called slave address byte. This includes the module address, 10001002 for the TDA4685. The TDA4685 is a slave receiver (R/W = 0), therefore the module address byte is 100010002(88 Hex), see Fig.3. The length of a data transmission is unrestricted, but the module address and the correct sub-address must be transmitted before the data byte(s). The order of data transmission is shown in Fig.4 and Fig.5. Without auto-increment (BREN = 0 or 1) the Module ADdress (MAD) byte is followed by a Sub-ADdress (SAD) byte and one data byte only (Fig.4).

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

handbook, full pagewidth

MSB LSB

module address

Fig.3 The module address byte.

TDA4685

00100

ACK0

R/W

MED710

handbook, full pagewidth

STOSAD

STOP

condition

MED697

START

condition

MADSTA

data byte

Fig.4 Data transmission without auto-increment (BREN = 0 or 1).

SAD

START

condition

MADSTA

data byte

data bytes

STO

STOP

condition

MED698

May 1993 7

Fig.5 Data transmission with auto-increment (BREN = 0).

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Video processor with automatic cut-off control

Auto-increment

The auto-increment format enables quick slave receiver initialization by one transmission, when the I2C-bus control bit BREN = 0 (see control register bits of Table 1). If BREN = 1 auto-increment is not possible. If the auto-increment format is selected, the MAD byte is followed by an SAD byte and by the data bytes of consecutive sub-addresses (Fig.5). All sub-addresses from 00 to 0F are automatically incremented, the sub-address counter wraps round from 0F to 00. Reserved sub-addresses 07, 08, 09, 0B, 0E and 0F are treated as legal but have no effect. Sub-addresses outside the range 00 and 0F are not acknowledged by the device. The sub-addresses are stored in the TDA4685 to address the following parameters and functions, see Table 1:

• brightness adjust

• saturation adjust

• contrast adjust

• hue control voltage

• RGB gain adjust

• peak drive limiting adjust

• control register functions.

Control register 1

NMEN (NTSC-Matrix ENable):

0 = PAL/SECAM matrix 1 = NTSC matrix.

BREN (Buffer Register ENable):

0 = new data is executed as soon as it is received

1 = data is stored in buffer registers and is transferred to the data registers during the next vertical blanking interval. The I2C-bus receiver does not accept any new data until this data is transferred into the data registers.

SC5 (SandCastle 5 V):

0 = 3-level sandcastle pulse 1 = 2-level (5 V) sandcastle pulse.

TDA4685

Control register 2

FSON2 - Fast Switch 2 ON FSDIS2 - Fast Switch 2 DISable FSON1 - Fast Switch 1 ON FSDIS1 - Fast Switch 1 DISable The RGB input signals are selected by FSON2 and FSON1 or FSW2and FSW1:

• FSON2 has priority over FSON1;

• FSW2has priority over FSW1;

• FSDIS1 and FSDIS2 disable FSW

and FSW2(see Table 2).

BCOF - Black level Control OFf:

0 = automatic cut-off control enabled

1 = automatic cut-off control disabled; RGB outputs are clamped to fixed DC levels.

When the supply voltage has dropped below approximately 6.0 V (usually occurs when the TV receiver is switched on or the supply voltage is interrupted) all data and function bits are set to 01

Hex.

The data bytes (D7-D0 of Table 1) provide the data of the parameters and functions for video processing.

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

Table 1 Sub-address (SAD) and data bytes

SAD MSB DATA BYTE LSB

FUNCTION

(HED) 7 6 5 4 3210

Brightness 00 0 0 A05 A04 A03 A02 A01 A00 Saturation 01 0 0 A15 A14 A13 A12 A11 A10 Contrast 02 0 0 A25 A24 A23 A22 A21 A20 Hue control voltage 03 0 0 A35 A34 A33 A32 A31 A30 Red gain 04 0 0 A45 A44 A43 A42 A41 A40 Green gain 05 0 0 A55 A54 A53 A52 A51 A50 Blue gain 06 0 0 A65 A64 A63 A62 A61 A60 Reserved 07 0 0 x x x x x x Reserved 08 0 0 x x x x x x Reserved 09 0 0 x x x x x x Peak drive limit 0A 0 0 AA5 AA4 AA3 AA2 AA1 AA0 Reserved 0B x x x x x x x x Control register 1 0C SC5 x BREN x NMEN x x x Control register 2 0D x x x BCOF FSDIS2 FSON2 FSDIS1 FSON1 Reserved 0E x x x x x x x x Reserved 0F x x x x x x x x

(1)

Note to Table 1

1. X is ‘don’t care’, but for software compatibility with other or future video ICs it is recommended to set all ‘X’ to ‘0’.

FSW

(pin 1)

(1)

FSW

(pin 13)

RGB

Y/CD

Table 2 Signal input selection by the fast source switches

C-BUS CONTROL BITS ANALOG SWITCH SIGNALS INPUT SELECTED

FSON2 FSDIS2 FSON1 FSDIS1

L L LLL L ON

LH ON HX ON

LLLHL X ON

HX ON

LLHXL X ON

HX ON

L H LLX L ON

XH ON LHLHX X ON LHHXX X ON H X XXX X ON

Note to Table 2

1. Where L is a logic LOW (< 0.4 V), H is a logic HIGH (> 0.9 V), X is ‘don’t care’, and ON is the selected input signal.

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC134).

SYMBOL PARAMETER MIN. MAX. UNIT

stg

amb

tot

supply voltage (pin 5) − 8.8 V input voltage (pins 1 to 8, 10 to 13, 16, 21, 23 and 25) −0.1 V input voltage (pins 15, 18 and 19) −0.7 V

+ 0.7 V

input voltage (pins 27 and 28) −0.1 8.8 V sandcastle pulse voltage −0.7 VP+5.8 V average current (pins 20, 22 and 24) −10 4 mA peak current (pins 20, 22 and 24) −20 4 mA output current −8 0.6 mA storage temperature −20 +150 °C operating ambient temperature 0 +70 °C total power dissipation − 1.2 W

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

TDA4685

MED711

8765 12 13 141110943

TDA4685

Fig.6 Internal circuits.

23 22 21 20 19 1825 24262728 1516

CL CL CL CLCLCLCLCLCL

diode protection

on all pins except

pins 5, 14, 27 and 28

ndbook, full pagewidth

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

CHARACTERISTICS

All voltages are measured in test circuit of Fig.7 with respect to GND (pin 9); V

= 8.0 V; T

- at nominal signal amplitudes (black-to-white) at output pins 24, 22 and 20,

- at nominal settings of brightness, contrast, saturation and white level control,

- without beam current or peak drive limiting; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

supply voltage (pin 5) 7.2 8.0 8.8 V supply current (pin 5) − 60 − mA

Colour difference inputs

V V V I

6,7

6(p-p) 7(p-p) 6,7

−(B−Y) input (peak-to-peak value) notes 1 and 2 − 1.33 − V

−(R−Y) input (peak-to-peak value) notes 1 and 2 − 1.05 − V

internal DC bias voltage at black level clamping − 4.1 − V input current during line scan −− ±0.1 µA

at black level clamping ±100 −−µA

6,7

input resistance 10 −−MΩ

Luminance/sync (VBS)

i(p-p)

luminance input at pin 8

note 2 − 0.45 − V

(peak-to-peak value)

internal DC bias voltage at black level clamping − 4.1 − V input current during line scan −− ±0.1 µA

at black level clamping ±100 −−µA

,G1and B1inputs

i(p-p)

input resistance 10 −−MΩ

black-to-white input signals at pins 10, 11

note 2 − 0.7 − V

and 12 (peak-to-peak value)

10/11/12

internal DC bias voltage at black level clamping − 5.7 − V input current during line scan −− ±0.1 µA

at black level clamping ±100 −−µA

10/11/12

, G2and B2inputs

i(p-p)

input resistance 10 −−MΩ

black-to-white input signals at pins 2, 3

note 2 − 0.7 − V

and 4 (peak-to-peak value) V I

2/3/4

internal DC bias voltage at black level clamping − 5.7 − V

input current during line scan −− ±0.1 µA

at black level clamping ±100 −−µA

2/3/4

input resistance 10 −−MΩ PAL/SECAM and NTSC matrix (note 3)

PAL/SECAM matrix control bit NMEN = 0

NTSC matrix control bit NMEN = 1

amb

=+25 °C:

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Fast signal switch FSW1to select Y, CD or R1, G1,B1inputs

control bits FSDIS1, FSON1 (see Table 2) V

∆t difference between transit times for

Fast signal switch FSW2 to select Y, CD / R1, G1, B1or R2, G2, B2inputs

control bits FSDIS2, FSON2 (see Table 2) V

∆t difference between transit times for

Saturation adjust

acts on −(R−Y) and −(B−Y) signals under I sub-address 01 data byte 3F data byte 23 data byte 00

Contrast adjust

acts on internal RGB signals under I sub-address 02 data byte 3F data byte 22 data byte 00

Brightness adjust

acts on internal RGB signals under I sub-address 00 data byte 3F data byte 26 data byte 00

voltage to select Y and CD −− 0.4 V

voltage range to select R

, G1, B

0.9 − 5.0 V

internal resistance to ground − 4.0 − kΩ

−− 10 ns

signal switching and signal insertion

voltage to select Y, CD/R1,G1, B

voltage range to select R

, G2, B

1 2

−− 0.4 V

0.9 − 5.0 V

internal resistance to ground − 4.0 − kΩ

−− 10 ns

signal switching and signal insertion

C-bus control,

(bit resolution 1.5% of maximum saturation);

Hex

for maximum saturation

Hex

for nominal saturation

Hex

for minimum saturation

Hex

saturation below maximum at 23

at 00

C-bus control,

(bit resolution 1.5% of maximum contrast);

Hex

for maximum contrast

Hex

for nominal contrast

Hex

for minimum contrast

Hex

contrast below maximum at 22

at 00

C-bus control,

(bit resolution 1.5% of maximum brightness);

Hex

for maximum brightness

Hex

for nominal brightness

Hex

for minimum brightness

Hex

black level shift of nominal signal

amplitude referred to cut-off

at 3F at 00

measurement level

Hex

; f = 100 kHz − 50 − dB

Hex

Hex Hex

− 5 − dB

− 22 − dB

− 30 − %

−−50 − %

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

White potentiometers, under I2C-bus control,

sub-addresses 04 data byte 3F data byte 19 data byte 00

∆G

Hex Hex Hex

relative to nominal gain:

(red), 05

Hex

for maximum gain for nominal gain for minimum gain

increase of gain at 3F decrease of gain at 00

RGB outputs pins 24, 22 and 20 (positive going output signals; peak drive limiter set = 3F

o(b-w)

nominal output signal amplitudes

(black-to-white value)

maximum output signal amplitudes

(black-to-white value) ∆V

spread between RGB output signals −− 10 %

minimum output voltages −− 0.8 V

maximum output voltages 6.8 −−V V

24,22,20

voltage of cut-off measurement line

= voltage during ultra-black I

int

internal current sources − 5.0 − mA

output resistance − 20 −Ω

Frequency response

d frequency response of Y path

(from pin 8 to pins 24, 22, 20)

frequency response of CD path

(from pins 7 to 24 and 6 to 20)

frequency response of RGB

pins 10 to 24, 11 to 22 and 12 to 20)

frequency response of RGB

(from pins 2 to 24, 3 to 22 and 4 to 20)

(green) and 06

Hex

path (from

path

(blue); note 4.

Hex

BCOF = 1 (output clamping)

f = 10 MHz −− 3dB

f = 8 MHz −− 3dB

f = 10 MHz −− 3dB

Hex Hex

); note 5.

− 50 − %

− 2 − V

3.0 −−V

2.3 2.5 2.7 V

Sandcastle pulse detector (control bit SC5 = 0) three level; notes 6 and 7

required voltage range

for H and V blanking pulses 2.0 2.5 3.0 V for H pulses (line count) 4.0 4.5 5.0 V for burst key pulses (clamping) 7.6 − V

May 1993 14

+5.8 V

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Sandcastle pulse detector (control bit SC5 = 1)

two level; notes 6 and 7 V

Sandcastle pulse detector

VFB (note 7) V

Average beam current limiting (note 9) V

c(15)

∆V

c(15)

br(15)

∆V

br(15)

required voltage range

for H and V blanking pulses 2.0 2.5 3.0 V for burst key pulses 4.0 4.5 V

+5.8 V

output current V14= 0 V −− −100 µA

leading edge delay of the clamping pulse − 1.5 −µs

vertical ﬂyback pulse for LOW −− 2.5 V

for HIGH 4.5 −−V

internal voltage pin 18 open-circuit;

− 5.0 − V

note 8

input current −− 5 µA

contrast reduction starting voltage − 4.0 − V

voltage difference for full contrast

−−2.0 − V

reduction

brightness reduction starting voltage − 2.5 − V

voltage difference for full brightness

−−1.6 − V

reduction Peak drive limiting voltage (note 10) internal peak drive limiting level (V

C-bus control, sub-address 0A

I V

20/22/24

level for minimum RGB outputs at byte 00

pdl

Hex

level for maximum RGB outputs at byte 3F I

charge current −−1 −µA

discharge current during peak white − 5 − mA V

c(16)

∆V

c(16)

internal voltage limitation 4.5 −−V

contrast reduction starting voltage − 4.0 − V

voltage difference for full contrast

reduction V ∆V

br(16)

brightness reduction starting voltage − 2.5 − V

voltage difference for full brightness

reduction

) acts on RGB outputs

Hex Hex

−− 3.0 V

7.0 −−V

−−2.0 − V

−−1.6 − V

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Automatic cut-off control (notes 7, 11, 12 and 13)

see Fig.9 V

external voltage −− V

output current −− −60 µA

input current 150 −−µA

additional input current switch-on delay 1 − 0.5 − mA V

24,22,20

monitor pulse amplitude (under

I2C-bus control, sub-address 0A V

voltage threshold for picture tube

cathode warm-up

internally controlled voltage (V

∆V

voltage difference between V

(cut-off measurement voltage) and V

Cut-off storage

21/23/25

charge and discharge currents during cut-off

current outside measurement −− ±0.1 µA

switch-on delay 1;

Hex

)

note 12 switch-on delay 1 − 4.5 − V

) during leakage

REF

measurement period

MEAS

REF

measurement lines

− V

− 1.0 − V

pdl

− 2.7 − V

− 1.0 − V

−±0.3 − mA

- 1.4 V

Leakage storage

charge and discharge currents during leakage

current outside measurement −− ±0.1 µA V

threshold voltage for reset to switch-on

state Hue control (note 14)

under I data byte 3F data byte 20 data byte 00

int

C-bus control, sub-address 03

for maximum voltage

Hex

for nominal voltage

Hex

for minimum voltage

Hex

output voltage at byte 3F

current of the internal current source at

pin 26

Hex

measurement period

Hex

at byte 20 at byte 00

Hex Hex

−±0.4 − mA

− 2.5 − V

4.8 −−V

− 3.0 − V

−− 1.2 V

500 −−µA

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Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

C-bus receiver clock SCL (pin 28)

SCL

C-bus receiver data input/output SDA (pin 27)

SU;DAT

Notes to the characteristics

1. The values of the −(B−Y) and −(R−Y) colour difference input signals are for a 75% colour-bar signal.

2. The pins are capacitively coupled to a low ohmic source, with a recommended maximum output impedance of 600Ω.

3. PAL/SECAM signals are matrixed by the equation: V NTSC signals are matrixed by the equations (hue phase shift of −5 degrees): V

R−Y*

In the matrix equations: V NTSC demodulator. V the following demodulator axes and amplification factors:

input frequency range 0 − 100 kHz LOW level input voltage −− 1.5 V HIGH level input voltage 3.0 − 6.0 V LOW level input current −− −10 µA HIGH level input current −− 10 µA pulse delay time LOW 4.7 −−µs pulse delay time HIGH 4.0 −−µs rise time −− 1.0 µs fall time −− 0.3 µs

LOW level input voltage −− 1.5 V HIGH level input voltage 3.0 − 6.0 V LOW level input current −− −10 µA HIGH level input current −− 10 µA LOW level output current 3.0 −−mA rise time −− 1.0 µs fall time −− 0.3 µs data set-up time 0.25 −−µs

= 1.57V

R−Y

- 0.41V

G−Y

B−Y R−Y

*, V

; V

G−Y

and V

R−Y

=− 0.51V

G−Y

* = −0.43V

are conventional PAL demodulation axes and amplitudes at the output of the

B−Y

* and V

B−Y

R−Y

− 0.11V

B−Y

; V

* are the NTSC-modified colour difference signals; this is equivalent to

B−Y

R−Y

* = V

− 0.19V

B−Y

(B−Y)* demodulator axis 0° 0° (R−Y)* demodulator axis 115° 90° (R−Y)* ampliﬁcation factor 1.97 1.14 (B−Y)* ampliﬁcation factor 2.03 2.03

* = −0.27V

G−Y

R−Y

4. The white potentiometers affect the amplitudes of the RGB output signals.

5. The RGB outputs at pins 24, 22 and 20 are emitter followers with current sources.

May 1993 17

* − 0.22V

B−Y

NTSC PAL

Page 18

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off

TDA4685

control

6. Sandcastle pulses are compared with internal threshold voltages independent of VP. The threshold voltages separate the components of the sandcastle pulse. The particular component is generated when the voltage on pin 14 exceeds the defined internal threshold voltage. The internal threshold voltages (control bit SC5 = 0) are:

1.5 V for horizontal and vertical blanking pulses (H and V blanking pulses),

3.5 V for horizontal pulses,

6.5 V for the burst key pulse.

The internal threshold voltages, control bit SC5 = 1, are:

1.5 V for horizontal and vertical blanking pulses,

3.5 V for the burst key pulse.

7. Vertical signal blanking is determined by the vertical component of the sandcastle pulse. The leakage and the RGB cut-off measurement lines are positioned in the first four complete lines after the end of the vertical component. In this case, the RGB output signals are blanked until the end of the last measurement line; see Fig 9(a). If an extra vertical flyback pulse VFB is applied to pin 18, the four measurement lines start in the first complete line after the end of the VFB pulse; see Fig 9(b). In this case, the output signals are blanked either until the end of the last measurement line or until the end of the vertical component of the sandcastle pulse, according to which occurs last.

8. If no VFB pulse is applied, pin 18 can be left open-circuit or connected to VP. If pin 18 is always LOW neither automatic cut-off control nor output clamping can happen.

9. Average beam current limiting reduces the contrast, at minimum contrast it reduces the brightness.

10. Peak drive limiting reduces the RGB outputs by reducing the contrast, at minimum contrast it reduces the brightness. The maximum RGB outputs are determined via the I2C-bus under sub-address 0A the maximum voltage, peak drive limiting is delayed by one horizontal line.

11. During leakage current measurement, the RGB channels are blanked to ultra-black level. During cut-off measurement one channel is set to the measurement pulse level, the other channels are blanked to ultra-black. Since the brightness adjust shifts the colour signal relative to the black level, the brightness adjust is disabled during the vertical blanking interval (see Fig.8 and Fig.9).

12. During picture cathode warm-up (first switch-on delay) the RGB outputs (pins 24, 22 and 20) are blanked to the ultra-black level during line scan. During the vertical blanking interval a white-level monitor pulse is fed out on the RGB outputs and the cathode currents are measured. When the voltage threshold on pin 19 is greater than 4.5 V, the monitor pulse is switched off and cut-off control is activated (second switch-on delay). As soon as cut-off control stabilizes, RGB output blanking is removed.

13. The cut-off measurement level range at the RGB outputs is 1 to 5 V. The recommended value is 3 V.

14. The hue control output at pin 26 is an emitter follower with current source.

. When an RGB output exceeds

Hex

May 1993 18

Page 19

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

handbook, full pagewidth

FSW

−(B−Y)

−(R−Y)

FSW

VP = 8 V

beam

current

information

10 nF 10 nF 10 nF

75

Ω

75

Ω

22 µH

220 µF

75

Ω

75

Ω

10 nF 10 nF 10 nF 47 nF

10 nF 10 nF 10 nF

3.9 kΩ

FSW

−(B−Y)

−(R−Y)

GND

R G

FSW

1N4148

2 2

2 2 P

1 1 1 1

1 2 3 4 5 6 7

TDA4685

8 9 10 11 12 13 14

(1)

BR1

TDA4685

SCL SDA hue

100 Ω

SCL

100 Ω

SDA

HUE

BCL

10 kΩ

R O G O B O

FB L PDL

220 nF

330 nF

1 µF

22 µF

82

kΩ

BZX79 C6V2

1 2 3 4 5 6 7 8 9

CON2

VFB (optional)

200 V +12 V

GND

MED712

May 1993 19

(1) Insert link BR1 if average beam

current limiting is not applied.

Fig.7 Test and application circuit.

Page 20

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

handbook, full pagewidth

maximum brightness

nominal brightness

cut-off measurement line

for red signal

Fig.8 Cut-off measurement pulse.

andbook, full pagewidth

sandcastle pulse

with vertical

component

TDA4685

MED713

ultra-black

R channel

G channel

B channel

vertical flyback

pulse (VFB)

R channel

G channel

B channel

(a) Timing controlled by sandcastle pulse

LM = leakage current measurement time MR, MG, MB = R, G, B cutt-off measurement pulses

(b) Timing controlled by additional vertical flyback pulse (VFB)

MED714

May 1993 20

Fig.9 Leakage and cut-off current measurement timing diagram.

Page 21

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

PACKAGE OUTLINE

handbook, full pagewidth

DIP28: plastic dual in-line package; 28 leads (600 mil)

seating plane

TDA4685

SOT117-1

w M

(e )

pin 1 index

0 5 10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

inches

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

max.

1 2

min.

max.

1.7

1.3

0.066

0.051

0.53

0.38

0.020

0.014

cD E weM

0.32

0.23

0.013

0.009

(1) (1)

36.0

35.0

1.41

1.34

14.1

13.7

0.56

0.54

(1)

3.9

3.4

15.80

15.24

0.62

0.60

17.15

15.90

0.68

0.63

0.252.54 15.24

0.010.10 0.60

0.15

0.13

max.

1.75.1 0.51 4.0

0.0670.20 0.020 0.16

OUTLINE VERSION

SOT117-1

May 1993 21

REFERENCES

IEC JEDEC EIAJ

051G05 MO-015AH

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17 95-01-14

Page 22

Philips Semiconductors Preliminary speciﬁcation

Video processor with automatic cut-off control

SOLDERING Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

Soldering by dipping or by wave

The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact

DEFINITIONS

(order code 9398 652 90011).

TDA4685

with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.

stg max

). If the

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development. Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later. Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

PURCHASE OF PHILIPS I

C COMPONENTS

May 1993 22

Purchase of Philips I components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.

C components conveys a license under the Philips’ I2C patent to use the