Datasheet TDA4663T Datasheet (Philips)

Page 1
INTEGRATED CIRCUITS
DATA SH EET
TDA4663T
Baseband delay line
Product specification Supersedes data of September 1993 File under Integrated Circuits, IC02
1996 Nov 22
Page 2
Philips Semiconductors Product specification
Baseband delay line TDA4663T

FEATURES

Two delay lines, using the switched-capacitor technique, for a delay time of one horizontal line (1H) minus 55 ns (64 µs 55 ns)

GENERAL DESCRIPTION

The TDA4663T is an integrated baseband delay line circuit with a delay time of one horizontal line (1H) minus 55 ns (64 µs 55 ns).
Adjustment-free application
Handles negative or positive colour-difference input
signals
Clamping of AC-coupled input signals [mostly colour-difference signals ±(RY) and ±(BY)]
VCO without external components
3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle pulse (64 µs line)
Sample-and-hold circuits and low-pass filters to
suppress the 3 MHz clock signal
Output buffer amplifiers.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
P1
V
P2
I
P(tot)
V
i(p-p)
analog supply voltage (pin 9) 4.75 5 5.25 V digital supply voltage (pin 1) 4.75 5 5.25 V total supply current 5.9 7.0 mA input signal PAL/NTSC (peak-to-peak value)
±(RY); pin 16 1.3 V ±(BY); pin 14 1.3 V
G
v
V
o
gain of colour-difference output signals for PAL and NTSC
-----­V
i
V
11
-------- ­V
16
V
12
-------- ­V
14
1 0 +1 dB
1 0 +1 dB

ORDERING INFORMATION

TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
TDA4663T SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
Page 3
Philips Semiconductors Product specification
Baseband delay line TDA4663T

BLOCK DIAGRAM

±(RY)
11
LP
SAMPLE-
AND-HOLD
LINE
MEMORY
mostly
output signals
colour-difference
output
buffers
pre-amplifiers
±(BY)
12
LP
SAMPLE-
AND-HOLD
LINE
MEMORY
n.c.
n.c.13n.c.15n.c.
2
6
TDA4663T
3 MHz shifting clock
BY-192
DIVIDER
PHASE
DETECTOR
FREQUENCY
BY-2
DIVIDER
CCO
6 MHz
LP
MED800
4, 8 3
GND2
1
P2
V
digital supply
Fig.1 Block diagram.
clamping pulse
SIGNAL
CLAMPING
16
±(RY)
handbook, full pagewidth
mostly
colour-difference
SIGNAL
CLAMPING
14
±(BY)
input signals
1996 Nov 22 3
analog supply
5
9
P1
V
DETECTOR
SANDCASTLE
sandcastle
pulse input
107GND1
Page 4
Philips Semiconductors Product specification
Baseband delay line TDA4663T

PINNING

SYMBOL PIN DESCRIPTION
V
P2
n.c. 2 not connected GND2 3 ground for digital part (0 V) i.c. 4 internally connected SAND 5 sandcastle pulse input n.c. 6 not connected V
CL
i.c. 8 internally connected V
P1
GND1 10 ground for analog part (0 V) V
o(RY)
V
o(BY)
n.c. 13 not connected V
i(BY)
n.c. 15 not connected V
i(RY)
1 supply voltage for digital part (+5 V)
7 clamping pulse input
9 supply voltage for analog part (+5 V)
11 ±(RY) output signal 12 ±(BY) output signal
14 ±(BY) input signal
16 ±(RY) input signal
handbook, halfpage
V
1
P2
n.c.
2 3
GND2
4
i.c.
TDA4663T
5
SAND
6
n.c.
7
V
CL
8
i.c.
MED801
Fig.2 Pin configuration.
16
V
i(RY)
15
n.c.
14
V
i(BY)
13
n.c.
12
V
o(BY)
11
V
o(RY)
10
GND1
9
V
P1

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). Ground pins 3 and 10 connected together.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
P1
V
P2
V
5
V
n
I
n
T
stg
T
amb
P
tot
V
es
supply voltage (pin 9) 0.5 +7 V supply voltage (pin 1) 0.5 +7 V voltage on pin 5 0.5 VP+ 1.0 V voltage on pins 7, 11, 12, 14 and 16 0.5 V
P
V current on pins 7, 11 and 12 20 mA storage temperature 25 +150 °C operating ambient temperature 20 +70 °C total power dissipation 100 mW electrostatic handling for all pins note 1 −±500 V
Note
1. Equivalent to discharging a 200 pF capacitor through a 0 series resistor.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air 220 K/W
Page 5
Philips Semiconductors Product specification
Baseband delay line TDA4663T

CHARACTERISTICS

VP= 5.0 V; input signals as specified in characteristics with 75% colour bars; super-sandcastle frequency of 15.625 kHz; T
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
P1
V
P2
I
P1
I
P2
analog supply voltage (pin 9) 4.75 5 5.25 V digital supply voltage (pin 1) 4.75 5 5.25 V supply current 5.1 5.9 mA supply current 0.8 1.1 mA
Colour-difference input signals
V
i(p-p)
input signal (peak-to-peak value)
pin 16 1.3 V pin 14 1.3 V
V
i(max)(p-p)
maximum symmetrical input signal (peak-to-peak value)
pin 16 before clipping 1.6 −−V pin 14 before clipping 1.6 −−V
I
14, 16
input leakage current
(during picture content) R C V
14, 16 14, 16
14, 16
input resistance during clamping −−40 k
input capacitance −−10 pF
input clamping voltage proportional to V
Colour-difference output signals
V
o(p-p)
output signal (peak-to-peak value)
pin 11 1.3 V pin 12 1.3 V
V
11/V12
ratio of output amplitudes at equal
input signals V
11, 12
R G
V
n(rms)
11, 12 v
DC output voltage proportional to V
output resistance 300 400
V
voltage gain
------
o
V
i
noise voltage
(RMS value; pins 11 and 12) S/N(W) weighted signal-to-noise ratio
(pins 11 and 12) t
j
α
ct(11, 12)
α
ct(12, 11)
α
ct(14, 12)
jitter of output signal to external
sandcastle reference V
5
crosstalk between channels V14=0V; RS= 300 ;
crosstalk between channels V16=0V; RS= 300 ;
crosstalk direct from input to output
signal
=25°C; measurements taken in Fig.3; unless otherwise specified.
amb
0.06 0.085 0.1 µA
1.3 1.5 1.7 V
2.5 2.9 3.3 V
V
i14, 16
P
= 665 mV (p-p) 0.4 0 +0.4 dB
P
1 0 +1 dB
V
V
= 0 V; note 1 −−1.2 mV
i14, 16
= 1 V (p-p); note 1 54 dB
o
−−20 ns
30 −−dB
V11= 1.35 V (p-p)
30 −−dB
V12= 1.35 V (p-p) V16=0V; RS= 300 ;
30 −−dB
V14= 1.35 V (p-p)
Page 6
Philips Semiconductors Product specification
Baseband delay line TDA4663T
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
α
ct(16, 11)
crosstalk direct from input to output
signal SVRR supply voltage ripple rejection
V
11, 12/VR
V
11,12(p-p)
clamping offset during H-clamp
(peak-to-peak value) V
11,12(p-p)
unwanted signals (line-locked)
(peak-to-peak value)
residual clock (3 MHz) −−6.25 mV meander −−1.5 mV needles −−2.5 mV
t
d
line delay time for PAL signals 64 0.125 64 0.055 64 + 0.015 µs
Sandcastle pulse input (pin 5)
f
BK
burst-key frequency/sandcastle
frequency V
5
t
BK
V
slice
I
i
C
i
t
li
top pulse voltage note 2 4.0 VP+ 1.0 V
top pulse duration 2.5 −µs
internal slicing level V5− 1.0 V5− 0.5 V
input current −−10 µA
input capacitance −−10 pF
lock-in time for PLL −−1ms
Clamping pulse input (pin 7)
V
clamp
clamping pulse ON 3.5 VP− 0.1 V
clamping pulse OFF 0.5 +0.1 +1.5 V I
i
C
i
t
clamp
t
r
t
f
input current −−10 µA
input capacitance −−10 pF
clamping pulse duration 0.1 2 3 µs
rise time 10 −−ns
fall time 10 −−ns
Notes
1. Noise voltage at f = 10 kHz to 1 MHz; RS< 300 .
2. The leading edge of the burst-key pulse or H-blanking pulse is used for timing.
V14=0V; RS= 300 ;
30 −−dB
V16= 1.35 V (p-p) VR= 100 mV (p-p);
34 −−dB fR= 10 Hz to 1 kHz; V
= 1.35 V (p-p)
11, 12
V14=V16=0V;
−−5mV
RS= 300 V14=V16=0V;
active video; RS= 300
for NTSC signals 63.555
0.125
14.2 15.625 17.0 kHz
63.555
0.055
63.555 +
0.015
P
µs
V
Page 7
Philips Semiconductors Product specification
Baseband delay line TDA4663T

APPLICATION INFORMATION

handbook, full pagewidth
1 nF
1 nF
SSC (5 V)
colour-
difference
signals
V
i(RY)
V
i(BY)
TDA4663T
16
14
5
LINE DELAY
LINE DELAY
LINE-LOCKED PLL /
PULSE PROCESSING
+5.1 V +5.1 V
9
10
(1) (1)
100
nF
22 µF
VCO
10
10
11
V
o(RY)
12
V
o(BY)
4 8
clamping pulse
7
(CMOS)
n.c.
2
n.c.
6
n.c.
13
n.c.
15
1
3
100
nF
560
+12 V
5.1 V
MED802
(1) Positioned close to pins.
Fig.3 Application circuit.
Page 8
Philips Semiconductors Product specification
Baseband delay line TDA4663T

PACKAGE OUTLINE

SO16: plastic small outline package; 16 leads; body width 3.9 mm
D
c
y
Z
16
pin 1 index
1
e
9
8
w M
b
p

SOT109-1

E
H
E
A
2
A
1
L
detail X
A
X
v M
A
Q
(A )
L
p
A
3
θ
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
OUTLINE VERSION
SOT109-1
A
max.
1.75
0.069
A
1
0.25
0.10
0.0098
0.0039
A2A
1.45
1.25
0.057
0.049
IEC JEDEC EIAJ
076E07S MS-012AC
0.25
0.01
b
3
p
0.49
0.25
0.36
0.19
0.0098
0.019
0.0075
0.014
UNIT
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
(1)E(1) (1)
cD
10.0
4.0
9.8
3.8
0.39
0.16
0.15
0.050
0.38
REFERENCES
eHELLpQZywv θ
1.27
6.2
5.8
0.24
0.23
1.0
0.7
1.05
0.4
0.039
0.041
0.016
0.25
0.6
0.028
0.01 0.004
0.020
EUROPEAN
PROJECTION
0.25 0.1
0.01
0.7
0.3
0.028
0.012
ISSUE DATE
91-08-13 95-01-23
o
8
o
0
Page 9
Philips Semiconductors Product specification
Baseband delay line TDA4663T
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“IC Package Databook”
Reflow soldering
Reflow soldering techniques are suitable for all SO packages.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
(order code 9398 652 90011).
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
Wave soldering
Wave soldering techniques can be used for all SO packages if the following conditions are observed:
A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
The longitudinal axis of the package footprint must be parallel to the solder flow.
The package footprint must incorporate solder thieves at the downstream end.
Page 10
Philips Semiconductors Product specification
Baseband delay line TDA4663T

DEFINITIONS

Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Nov 22 10
Page 11
Philips Semiconductors Product specification
Baseband delay line TDA4663T
NOTES
1996 Nov 22 11
Page 12
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© Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 537021/1200/02/pp12 Date of release: 1996 Nov 22 Document order number: 9397 750 01375
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