Datasheet TDA1592 Datasheet (Philips)

Page 1
INTEGRATED CIRCUITS
DATA SH EET
TDA1592
PLL stereo decoder and noise blanker
Preliminary specification Supersedes data of June 1993 File under Integrated Circuits, IC01
1996 May 31
Page 2
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
FEATURES
• Adjustment-free voltage controlled PLL oscillator for ceramic resonator (f = 456 kHz)
• Pilot signal dependent mono/stereo switching
• Analog control of mono/stereo change over
[stereo blend, Stereo Noise Controller (SNC)]
• Adjacent channel noise suppression (114 kHz)
• Pilot canceller
• Analog control of de-emphasis; High Cut Control (HCC)
• Reduced and controlled de-emphasis for AM operation
(pin 7 to GND)
• Applicable as source selector for AM/FM/cassette switching
• Soft mute for silent tuning
• Separate interference noise detector
• Integrated input low-pass filter for delayed noise
blanking
• Noise blanking at MPX-demodulator outputs.
QUICK REFERENCE DATA
GENERAL DESCRIPTION
The TDA1592 is a monolithic bipolar integrated circuit providing the stereo decoder function and noise blanking for FM car radio applications.
The device operates in a power supply range of
7.5 to 12 V.
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
V
P
I
P
V
o(rms)
supply voltage (pin 5) 7.5 10 12 V supply current − 15 20 mA
audio output signal (RMS value) 800 900 1000 mV THD total harmonic distortion − 0.1 0.3 % S/N signal-to-noise ratio − 82 − dB
α
cs
V
trigg
channel separation 30 40 − dB
interference voltage trigger level − 10 − mV
ORDERING INFORMATION
TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
TDA1592 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1 TDA1592T SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1996 May 31 2
Page 3
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
BLOCK DIAGRAM
out
R
input
auxiliary
HCC
V
SNC
V
ref
andbook, full pagewidth
V
out R
R
6.8
6.8
nF nF
11
(120 kHz)
ref
V
DETECTOR
NOISE AND AGC
AGC
kΩ
6.8
TDA1592
SNC
ref
V
AND
HCC
GATE
7.4 kΩ
7.4 kΩ
FILTER
2-POLE
(30 kHz)
MUTE
6.8 kΩ
PULSE
DETECTOR
INTERFERENCE
AMPLIFIER
HIGH-PASS
ref
V
FORMER
47 kΩ
15 14 13 12
10987654321
out L
47 kΩ
R
BC548
820
33 kΩ
47
68
pF
off
VCO
47 kΩ
27 kΩ
27 kΩ
kΩ
nF
33 pF
out
L
MED724
input
auxiliary
mute
input
interference
P
V
mono
in
R
164 kΩ
18 17 16
SWITCH
PILOT
CANCEL
19
PILOT
DETECTOR
PHASE
ref
V
20
75
kΩ
FILTER
4-POLE
(80 kHz)
pilot
indicator
MPX input
kΩ
750
100 nF
100 nF
1996 May 31 3
19 19 19 38
DETECTOR
LOGIC
ref
I
ref
V
POWER
SUPPLY
100 kΩ
100 nF
Fig.1 Block diagram with external components, also used as test circuit.
CSB
VCO
456 F11
10 nF
68 kΩ
100 nF
Page 4
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
PINNING
SYMBOL PIN DESCRIPTION
PLL 1 phase locked loop filter OSC
GND 3 ground (0 V) I
ref
V
P
INFI 6 interference signal input PUFO
NDET
FB-L
V
oL
V
oR
FB-R
C
DEEL
C
DEER
HCC 15 HCC input for de-emphasis control SNC 16 stereo blend input V
ref
IDENT
PILOT
V
i MPX
oscillator input/output pin for
2
ceramic resonator
4 reference current 5 supply voltage (+10 V)
pulse former time constant; VCO
7
off
noise detector time constant; mute
8
on
AF feedback input for left audio
9
signal 10 AF output signal left 11 AF output signal right
AF feedback input for right audio 12
signal
de-emphasis capacitor for left 13
channel
de-emphasis capacitor for right 14
channel
externally applied reference 17
voltage of 1 to 5 V
identification output (HIGH = pilot 18
existing; stereo)
pilot detector level (forced mono 19
input)
MPX input signal from IF 20
demodulator
handbook, halfpage
PLL
1
OSC
2
GND
3
I
4
ref
V
5
P
6 7 8 9
10
TDA1592
MED726
INFI PUFO NDET
FB-L
V
oL
Fig.2 Pin configuration.
V
20
i MPX
19
PILOT
18
IDENT
17
V
ref
16
SNC HCC
15
C
14
DEER
C
13
DEEL
FB-R
12
V
11
oR
1996 May 31 4
Page 5
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
FUNCTIONAL DESCRIPTION
The MPX input of the TDA1592 (pin 20) is the null-node of an operational amplifier with internal feedback resistor. Adapting the stereo decoder input to the level of the FM demodulator output is realized by the value of input resistor Rin (see Fig.3). The total gain of the stereo decoder is applicable by varying the feedback resistors R
(pins 9, 10, 11 and 12) of the output operational
out
amplifiers (see Fig.4). The input amplifier is followed by an integrated 4th order
Bessel low-pass filter with a cut-off frequency of 80 kHz. It provides necessary signal delay for noise blanking and damping of high frequency interferences at the stereo decoder input.
The soft mute facility (pin 8) provides silent tuning for RDS processing. The mute time constant may be adjusted from pin 8. In mute position and the VCO switched off (pin 7), the output amplifiers can be used for cassette playback, AM stereo purpose or other signal sources.
The voltage to current converted MPX signal is fed to phase detector, pilot detector and pilot canceller circuits. The oscillator is alignment-free with an external ceramic resonator at 456 kHz as reference (pin 2). The required 19 kHz and 38 kHz signals are generated by division of the oscillator output signal in a logical circuit. For regeneration of the 38 kHz subcarrier, a PLL is used. The 19 kHz quadrature phase signal is fed to the 19 kHz phase detector, where it is compared with the incoming pilot tone. The DC output signal of the phase detector (pin 1) controls the oscillator (PLL).
The pilot presence detector is driven by internally generated in-phase 19 kHz. Its pilot-dependent DC output voltage (pin 19) is fed to a threshold switch, which activates the pilot indicator logic output (pin 18) and turns the stereo decoder to stereo operation. The same DC voltage is used to control the amplitude of an anti-phase internally generated 19 kHz signal. In the pilot canceller, the pilot tone is compensated by this anti-phase 19 kHz signal.
The pilot cancelled signal is fed to the multiplex decoder. There, the side signal is demodulated and combined with the main signal in a matrix to left and right audio channel.
Compensation for roll-off in the incoming MPX signal caused by IF filters and FM demodulator is realized by corresponding side signal amplification.
A smooth mono to stereo take-over, which is controlled by the level detector voltage of the IF part, is achieved by the SNC (pins 16 and 17; see Fig.6).
From the output of the MPX demodulator the signals are fed to 2-pole low-pass filters with a cut-off frequency of 30 kHz to provide additional signal delay for noise blanking and attenuation of the subcarrier and its harmonics.
These filters are followed by the noise suppression gates, which are combined with de-emphasis and HCC. The de-emphasis is defined by internal resistors (aligned by an external current) and external capacitors (pins 13 and 14). For HCC, the de-emphasis time constant can be changed to higher values (pins 15 and 17; see Figs 7 to 9). This function is controlled by an analog input signal, derived from the level detector voltage of the IF part. When the VCO is turned off (pin 7 to GND), de-emphasis is reduced to 20 µs for full frequency response when AM-AF is fed through the stereo decoder. De-emphasis remains controllable.
From the gate circuits audio is fed through internal series resistors to the inverting inputs of the output operational amplifiers (pins 9 and 12), which can also be used as signal inputs for cassette playback or other sources when the mute is activated. The gain of these amplifiers is defined by external feedback resistors R (pins 9, 10, 11 and 12).
The input of the ignition noise blanker is the null node of an operational amplifier (pin 6). It can be driven by the level detector output of the FM-IF limiter and/or the MPX signal. Its sensitivity is dependent on the value of the series input resistor at pin 6.
The operational amplifier output signal is fed through an integrated 120 kHz high-pass filter, becomes amplified and is then fed in parallel to the noise detector and the interference detector. The noise detector is a negative peak detector. Its output (pin 8) controls the trigger sensitivity (prevention to false triggering at noisy input signals) and the attenuation of the input operational amplifier. The output of the interference detector, when receiving a steep pulse, triggers a mono flip-flop, which is a part of the pulse former circuit. The time constant of the mono flip-flop is defined by an external capacitor (pin 7) and its output activates the blanking gates in the audio.
out
1996 May 31 5
Page 6
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER MIN. MAX. UNIT
V
P
P
tot
T
stg
T
amb
V
es
Note
1. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor.
CHARACTERISTICS
= 10 V; T
V
P
amb
and series resistor at input R1= 164 kΩ; measurements taken in Fig.1; unless otherwise specified.
supply voltage (pin 5) 0 13.2 V total power dissipation 0 0.25 W storage temperature −55 +150 °C operating ambient temperature −40 +85 °C electrostatic handling for all pins; note 1 −400 +400 V
=25°C; input signal V
i MPX(p-p)
= 1.7 V; m = 100% (∆f=±75 kHz, f
= 1 kHz); de-emphasis of 50 µs
mod
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
P
I
P
supply voltage (pin 5) 7.5 10 12 V supply current − 15 20 mA
Stereo decoder
V
i MPX(p-p)
∆V
i MPX(p-p)
V
o(rms)
MPX input signal − 1.7 − V overdrive margin of MPX input signal THD = 1% 6 −−dB AF mono output signal at pins 10 and 11
without pilot 800 900 1000 mV
(RMS value)
∆V
o
V
10-11/Vo
V
o 10,11
R
o 10,11
I
o
R
2,3
V
4,3
α
cs
overdrive margin of output signal THD = 1% 6 −−dB difference of output voltage levels −−1dB DC output voltage (pins 10 and 11) 3.2 3.7 4.2 V output resistance − 150 −Ω output current 330 400 −µA maximum feedback resistor −−68 kΩ reference voltage 3.7 3.8 3.9 V channel separation pin 16 open-circuit;
30 40 − dB
see Fig.6 THD total harmonic distortion − 0.1 0.3 % S/N signal-to-noise ratio f = 20 to 16000 Hz 77 82 − dB
α
19
α
38
α
57
α
76
IM2 intermodulation for f IM3 f
α
57 VF
α
67
pilot signal suppression f = 19 kHz 40 50 − dB subcarrier suppression f = 38 kHz 35 50 − dB
f = 57 kHz 46 −−dB
f = 76 kHz − 60 − dB
= 1 kHz f
spur
= 10 kHz; note 1 − 60 − dB
mod
= 13 kHz − 58 − dB
mod
traffic radio (VWF) f = 57 kHz; note 2 − 70 − dB SCA (Subsidiary Communications
f = 67 kHz; note 3 70 −−dB
Authorization)
1996 May 31 6
Page 7
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
α
114
α
190
PSRR power supply ripple rejection f = 100 Hz;
VCO (pin 2)
f
osc
∆f/f capture and holding range −±0.65 − % V
7
Mono/stereo control (pins 16, 17 and 19)
V
i pilot
HYS hysteresis of pilot threshold voltage − 2 − dB V
19
V
ref
V
16-17
Pilot indicator logic level output (pin 18)
V
18
I
18
Muting (pin 8)
MUTE
V
o(offset)
HCC (pin 15)
CR
deem
V
15-17
ACI (Adjacent Channel Interference) f = 114 kHz; note 4 − 80 − dB
f = 190 kHz; note 4 − 70 − dB
− 35 − dB
V
ripple (rms)
= 100 mV
oscillator frequency (ceramic resonator) − 456 − kHz frequency range of free running oscillator 451 − 459 kHz
VCO-off voltage (pin 7) 0 − 0.6 V
pilot threshold voltage for automatic switching by pilot input voltage (RMS value)
switching voltage for external mono control
stereo on − 24 30 mV
stereo off 820−mV
−−0.7 V
(pin 19) reference input voltage range (pin 17) 1 − 5V control voltage for channel separation due to
pin 17 (V
ref
)
αcs= 6 dB; see Fig.5 −80 −100 −120 mV
= 20 dB; see Fig.5 −40 −55 −70 mV
α
cs
LOW voltage I18= 500 µA − 250 400 mV HIGH current V18=10V −−1µA
mute attenuation (pin 8) V8< 1.6 V 80 −−dB
att
>4V −−0.2 dB
V
8
DC offset voltage (pins 10 and 11)
after muting
−−±50 mV
control range of de-emphasis see Figs 7 and 8
for European standard C for USA standard C
control voltage (pin 15 due to pin 17) in both standards
lower value CR
upper value CR
= 6.8 nF 50 − 150 µs
deem
=10nF 75 − 225 µs
deem
deem
deem
− 0 − mV
−−300 − mV
1996 May 31 7
Page 8
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
HCC (pin 15, pin 7 to GND)
CR
deem
V
15-17
, ∆V11DC offset voltage at AF outputs (AM on/off) −−±200 mV
∆V
10
Noise interference detector
V
pulse
∆V
8
t
sup
I
13,14
control range of de-emphasis see Fig.9
for European standard C for USA standard C
control voltage (pin 15 due to pin 17) in both standards
trigger sensitivity τ trigger threshold voltage offset as a function of
V
trigg
lower value CR
upper value CR
pulse
f
int
= 6.8 nF 15 − 90 µs
deem
=10nF 22 − 135 µs
deem
deem
deem
− 0 − mV
−−300 − mV
=10µs − 10 − mV
= 120 kHz V V
= 10 mV 150 200 250 mV
interf.in
= 100 mV 550 650 750 mV
interf.in
AF suppression time; pulse width − 40 −µs input offset current (pins 13 and 14) during AF suppression
− 20 − nA
time
Notes
1. Intermodulation suppression [Beat Frequency Components (BFC)]: V
IM2
IM3
o(signal)
= f
------------------------------------------------------- ­V
o(spurious)
V
o(signal)
= f
------------------------------------------------------- ­V
o(spurious)
measured with 91% mono signal; f
at 1 kHz()
at 1 kHz()
at 1 kHz()
at 1 kHz()
;
s
;
s
2 10 kHz×()19 kHz–=
3 13 kHz×()38 kHz–=
= 10 kHz or 13 kHz; 9% pilot signal.
mod
2. ARI suppression:
V
α
=
ARI
57
o(signal)
---------------------------------------------------------------------------- ­V
o(spurious)
measured with 91% stereo signal; f
= 57 kHz; f
(f
s
= 23 Hz; AM m = 0.6).
mod
at 1 kHz()
at 1 kHz 23 Hz±()
= 1 kHz; 9% pilot signal; 5% ARI subcarrier
mod
3. Subsidiary Communication Authorization (SCA):
V
α
67
o(signal)
= f
------------------------------------------------------- ­V
o(spurious)
measured with 81% mono signal; f
at 1 kHz()
at 9 kHz()
;
s
238kHz×()67 kHz–=
= 1 kHz; 9% pilot signal; 10% SCA subcarrier (fs= 67 kHz, unmodulated).
mod
4. Adjacent Channel Interference (ACI):
V
α
114
α
190
o(signal)
= f
------------------------------------------------------- ­V
o(spurious)
V
o(signal)
= f
------------------------------------------------------- ­V
o(spurious)
measured with 90% mono signal; f
= 110 kHz or 186 kHz, unmodulated).
(f
s
at 1 kHz()
at 4 kHz()
at 1 kHz()
at 4 kHz()
;
s
;
s
mod
110 kHz 3 38 kHz×()–=
186 kHz 5 38 kHz×()–=
= 1 kHz; 9% pilot signal; 1% spurious signal
1996 May 31 8
Page 9
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
MED727
Rin (kΩ)
i MPX(p-p)
(V)
4
3
2
1
0
0 100 300
handbook, halfpage
V
200
Fig.3 Input signal as a function of series input resistor Rin.
handbook, halfpage
+4
G
(dB)
+2
0
−2
−4
0204060
Fig.4 Overall signal gain as a function of feedback resistors R
1996 May 31 9
MED728
R
(kΩ)
out
(Rin= 164 kΩ).
out
Page 10
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
50
handbook, full pagewidth
αcs
(dB)
40
30
20
10
0
10
(1) Coupling capacitor CK at pin 20= 10µF. (2) Coupling capacitor CK at pin 20= 0.1µF.
Fig.5 Channel separation as a function of audio frequency.
MED729
(1)
(2)
2
10
3
10
4
10
AF
out
(Hz)
5
10
16-17
MED730
0
(mV)
50
handbook, halfpage
αcs
(dB)
40
30
20
10
0
−200 −100 control voltage V
Fig.6 Stereo blend characteristic (SNC).
1996 May 31 10
handbook, halfpage
0 ∆Vo (dB)
−2
−4
−6
−8
−10
−300 −200 0
control voltage V
Fig.7 HCC with f
−100
mod
15-17
= 10 kHz.
MED731
(mV)
Page 11
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
MED732
handbook, full pagewidth
V
(dB)
2
o
0
(1)
−2
−4
−6
−8
−10
−12
10
(1) V (2) V
handbook, full pagewidth
=0.
15-17
= −300mV.
15-17
2
0
V
o
(dB)
−2
−4
(2)
2
10
3
10
4
10
Fig.8 HCC with pre-emphasis as a function of audio frequency.
(1)
AF
out
(Hz)
MED733
5
10
−6
−8
−10
−12
−14
−16
(1) V (2) V
−18
15-17 15-17
10
=0. = −300mV.
2
10
10
Fig.9 HCC as a function of audio frequency (pin 7 connected to GND; without pre-emphasis).
1996 May 31 11
(2)
3
4
10
AF
out
(Hz)
5
10
Page 12
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
INTERNAL PIN CONFIGURATION
handbook, full pagewidth
20
19
18
3.8 V V
i MPX
4.5 V (0.4 V) PILOT
IDENT
4.3 V (4.6 V) PLL
3.6 V OSC
GND
1
2
3
TDA1592
3.8 V
2.1 V ( 3 × VBE) INFI
2.1 V ( 3 × VBE) PUFO
VP − 2.2 V
NDET
3.8 V FB-L
17
4
I
ref
5
V
P
6
7
14 µA
8
400 µA
9
1 to 5 V V
ref
16
1 to 5 V SNC
15
1 to 5 V HCC
14
3.8 V C
DEER
13
3.8 V C
DEEL
12
3.8 V FB-R
10
3.6 V
V
oL
400 µA
Fig.10 Internal circuitry.
1996 May 31 12
400 µA
MED725
11
3.6 V  V
oR
Page 13
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
TEST INFORMATION
handbook, full pagewidth
100 nF
10 nF
33 pF
VCO off
mute
47 nF
220 nF
100 µF
10 Ω
27 kΩ 68 pF
27 kΩ
820
interference IN
68 kΩ
CSB456F11
100 nF
33 kΩ
kΩ
kΩ
47
BC548
100 kΩ
47 kΩ
TDA1592
220 nF
82 kΩ
47 kΩ
220 nF
82 kΩ
100 nF
6.8 nF
47 kΩ
mono
820 kΩ
27 kΩ
27 kΩ 100 kΩ 100 kΩ
100 nF
220 nF
6.8 nF
MPX IN
10 kΩ
V
SNC
HCC
GND
+V
12 kΩ
ref
Pilot indicator
P
101 mm
AUX IN
right
right OUT
76 mm
Fig.11 TDA1592 test board (component side).
1996 May 31 13
left
OUT
AUX IN
left
MED734
Page 14
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
PACKAGE OUTLINES
DIP20: plastic dual in-line package; 20 leads (300 mil)
D
seating plane
L
Z
20
pin 1 index
e
b
SOT146-1
M
E
A
2
A
A
1
w M
b
1
11
E
c
(e )
1
M
H
1
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
A 
A 
UNIT
inches
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
max.
mm
OUTLINE VERSION
SOT146-1
1 2
min.
max.
1.73
1.30
0.068
0.051
IEC JEDEC EIAJ
SC603
b
b
1
0.53
0.38
0.021
0.015
0.36
0.23
0.014
0.009
REFERENCES
cD E e M
(1) (1)
26.92
26.54
1.060
1.045
1996 May 31 14
6.40
6.22
0.25
0.24
10
(1)
1
3.60
8.25
3.05
7.80
0.14
0.32
0.12
0.31
EUROPEAN
PROJECTION
H
E
10.0
0.2542.54 7.62
8.3
0.39
0.010.10 0.30
0.33
ISSUE DATE
M
L
e
w
92-11-17 95-05-24
Z
max.
2.04.2 0.51 3.2
0.0780.17 0.020 0.13
Page 15
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
SO20: plastic small outline package; 20 leads; body width 7.5 mm
D
c
y
Z
20
pin 1 index
1
e
11
A
2
10
w M
b
p
SOT163-1
E
H
E
Q
A
1
L
p
L
detail X
(A )
A
X
v M
A
A
3
θ
0 5 10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
mm
OUTLINE
VERSION
SOT163-1
A
max.
2.65
0.10
A
1
0.30
0.10
0.012
0.004
A2A
2.45
2.25
0.096
0.089
IEC JEDEC EIAJ
075E04 MS-013AC
0.25
0.01
b
3
p
0.49
0.32
0.36
0.23
0.019
0.013
0.014
0.009
UNIT
inches
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
(1)E(1) (1)
cD
13.0
7.6
7.4
0.30
0.29
1.27
0.050
12.6
0.51
0.49
REFERENCES
1996 May 31 15
eHELLpQ
10.65
10.00
0.42
0.39
1.4
0.055
1.1
0.4
0.043
0.016
1.1
1.0
0.043
0.039
PROJECTION
0.25
0.25 0.1
0.01
0.01
EUROPEAN
ywv θ
Z
0.9
0.4
8
0.004
ISSUE DATE
0.035
0.016
92-11-17 95-01-24
0
o o
Page 16
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
SOLDERING Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“IC Package Databook”
(order code 9398 652 90011).
DIP
OLDERING BY DIPPING OR BY WA VE
S The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T
stg max
). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
EPAIRING SOLDERED JOINTS
R Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
SO
REFLOW SOLDERING Reflow soldering techniques are suitable for all SO
packages.
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C.
AVE SOLDERING
W Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.
• The longitudinal axis of the package footprint must be parallel to the solder flow.
• The package footprint must incorporate solder thieves at the downstream end.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
EPAIRING SOLDERED JOINTS
R Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
1996 May 31 16
Page 17
Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 May 31 17
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Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
NOTES
1996 May 31 18
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Philips Semiconductors Preliminary specification
PLL stereo decoder and noise blanker TDA1592
NOTES
1996 May 31 19
Page 20
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© Philips Electronics N.V. 1996 SCA49 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 517021/1200/02/pp20 Date of release: 1996 May 31 Document order number: 9397 750 00875
Internet: http://www.semiconductors.philips.com/ps/ (1) ADDRESS CONTENT SOURCE May 31, 1996
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