Datasheet tda1318 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

TDA1318

DCC read amplifier

Preliminary specification
File under Integrated Circuits, IC01

Philips Semiconductors

April 1996

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

FEATURES

• Differential inputs for a low-power head configuration

• Low-noise current sources for the sense currents of the

DCC head

• Reduced power consumption by separate on/off
switching of the circuits and sense current of the DCC
and CC parts of the IC

• The IC can be used with both the first and second
generation DCC digital signal processing ICs

• High-impedance outputs in the OFF state so that the
outputs of the ICs can be connected in parallel for dual
decks or for decks with electrical auto-reverse heads

• AGC of DCC preamplifiers (can be switched off)

• Possibility of analog audio via DCC preamplifiers

(analog via digital readers, ADR mode)

• Single 5 V supply.

GENERAL DESCRIPTION

The TDA1318 amplifies, filters and multiplexes signals
arriving from magneto-resistive thin film heads (MRHs)
which are suitable for DCC (Digital Compact Cassette)
and CC (Compact Cassette) systems. The device also has
current sources to provide sense currents through the
DCC-MRHs and two amplifiers for magnetic feedback and
biasing.

QUICK REFERENCE DATA

SYMBOL PARAMETER

V

DD

V

CCM

I

DDDCC

I

DDDCCadr

I

DDCC

I

DDCCadr

I

CCM

I

DD

I

DD(Q)

P

tot

T

amb

supply voltage −− −4.5 5.0 5.5 V
supply voltage feedback amplifiers −− −4.5 5.0 5.5 V
supply current DCC mode (note 2) 1 1 0 − 31 41 mA
supply current DCC mode (ADR) 1 1 1 − 31 41 mA
supply current CC mode 1 0 0 − 9.7 13 mA
supply current CC mode (ADR) 1 0 1 − 17.8 24.5 mA
supply current feedback amplifiers 1 1 1 − 8.5 12 mA

supply current (ADC reference ON) 0 1 −− 1.6 2.2 mA
total quiescent current in OFF mode 0 0 −− − 300 µA
total power dissipation, DCC mode −− −− 250 − mW
operating ambient temperature −− −−30 − +85 °C

Notes

1. In the conditions column 0 = LOW; 1 = HIGH.

2. ADR = 1 when pin INL and/or INR is connected to V

CONDITIONS

(1)

CS SD ADR

10 0
10 1

.

SS

MIN. TYP. MAX. UNIT

April 1996 2

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

ORDERING INFORMATION

EXTENDED TYPE

NUMBER

TDA1318H 44 QFP44S10

Note

1. When using IR reflow soldering it is recommended that the Dry Packing instructions in the

book”

(order number 9398 510 34011) are followed.

BLOCK DIAGRAM

PINS PIN POSITION MATERIAL CODE

PACKAGE

(1)

plastic SOT307-2

“Quality Reference Pocket

April 1996 3

Fig.1 Block diagram.

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

PINNING

SYMBOL

PIN

DESCRIPTION

RDMUX 1 output for sampled and multiplexed

auxiliary and main data signals

OUTX 2 auxiliary channel preamplifier

output
MUXINX 3 auxiliary channel multiplexer input
DSENAD

J1
DSENAD

J2
DSENAD

J3

4 adjustment pin for DCC sense

current 1

5 adjustment pin for DCC sense

current 2

6 adjustment pin for DCC sense

current 3
VD14 7 reference voltage output DCC

sense
DSEN1 8 DCC sense current output 1
DSEN2 9 DCC sense current output 2
DSEN3 10 DCC sense current output 3
INX0 11 auxiliary channel input/channel 0

input
IN01 12 channels 0 and 1 input
IN1 13 channel 1 input
INX25 14 channels AUX, 2 and 5 input
IN23 15 channels 2 and 3 input
IN34 16 channels 3 and 4 input
IN4 17 channel 4 input
IN56 18 channels 5 and 6 input
IN67 19 channels 6 and 7 input
IN7 20 channel 7 input
V14 21 reference voltage output for

DCC/analog inputs
OUTR 22 right channel analog output

SYMBOL

PIN

DESCRIPTION

INMFR 23 right channel feedback amplifier

input

MFR1 24 right channel feedback amplifier

output 1
INR 25 right channel analog input
MFR2 26 right channel feedback amplifier

output 2
INRL 27 right/left channel analog input
V
V

EEM
CCM

28 ground for feedback amplifiers
29 positive supply for feedback

amplifiers
MFL2 30 left channel feedback amplifier

output 2
INL 31 left channel analog input
MFL1 32 left channel feedback amplifier

output 1
INMFL 33 left channel feedback amplifier

input
OUTL 34 left channel analog output
VA14 35 reference voltage output CC sense
V33 36 ADC reference voltage output
SD 37 select DCC part input
V

DD

V

SS

38 positive supply voltage

39 ground
RDCLK 40 read clock input
RDSYNC 41 read sync pulse input
CS 42 chip select input
AGC 43 AGC time constant
VBIAS 44 DCC preamplifier control voltage

April 1996 4

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION
DCC data amplifiers

For DCC operation the TDA1318 has eight channels for
the main data and one channel for the auxiliary data. The
eight main data channels have low-noise preamplifiers,
pre-equalisation for frequencies from 1 kHz to 50 kHz
(1st order high-pass filter, −3 dB point 75 kHz) and
low-pass filtering for anti-aliasing (2nd order active, −3dB
point 120 kHz). The auxiliary channel has a preamplifier
with a flat frequency response. A continuous output
(OUTX) is available for this channel. All inputs are
differential and must be AC-coupled to the MRHs. The
inputs are internally biased by V14.

Automatic gain control

The DCC part is equipped with an AGC circuit which
diminishes the gain of the DCC preamplifiers when the
level at output RDMUX exceeds a preset value.

April 1996 5

In this way, an optimum voltage swing at the RDMUX
output is obtained. The response time of the AGC can be
set by an external capacitor at pin 43. There is a fixed
relation between the source and sink current at this pin.
This results in a fixed relationship between decay and
recovery time of the gain. The AGC can be switched off by
connecting pin 43 to V
gains are maximum, as specified in Chapter
“Characteristics”.

Multiplexer

A multiplexing circuit switches the nine digital channels
sequentially to the output. The AUX data is switched to the
output buffer during two clock periods, the eight main data
channels are all sampled for one clock period. The
effective sample frequency is one tenth of the clock
frequency at RDCLK. Multiplexer timing is illustrated in
Fig.4.

. In this condition the preamplifier

SS

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

Analog amplifiers

For Compact Cassette operation the TDA1318 has two
low-noise preamplifiers, and two amplifiers for the
magnetic feedback current. The analog amplifier inputs
are differential, and must be AC-coupled to the MRHs. The
analog inputs are internally biased by V14.

When one of the analog inputs, INL or INR, is connected
to VSS the circuit is set to the ADR mode. In this condition
the analog amplifiers are switched OFF and four DCC
preamplifiers are available for amplification of the left and
right analog signals.

Feedback amplifiers

Two feedback amplifiers are available for driving a coil in
the MRH, thus providing a feedback loop in order to
improve the linearity of the analog audio response. In the
DCC mode the feedback amplifiers can be used for biasing
the MRH (for ADR = 1).

Current and voltage sources

Separate, adjustable low-noise current sources are
present for the sense currents of the DCC MRHs.
The DC output voltages V14, VA14, VD14, and V33 are
derived from an internal bandgap voltage reference
source.

VD14 is a reference voltage for the DCC sense current
sources. VA14 (referenced to V

) can be used to control

SS

external sense current sources. V33 (referenced to VSS)
can be used as reference voltage for an analog-to-digital
converter.

Modes of operation

The amplifiers and sense current circuits of the DCC and
CC parts can be switched ON or OFF separately by the
mode switch signals CS and SD. In addition, a connection
of one of the analog inputs INL or INR to V

is recognized

SS

as the ADR mode, thereby providing amplification of audio
signals by the DCC preamplifiers. This enables the use of
heads containing only DCC readers as well as heads
equipped with analog and DCC readers.

The data and analog output buffers have high-output
impedance in the OFF state, thus allowing the outputs of
ICs to be connected in parallel.

Table 1 Total supply current per mode.

MODE CS SD ADR

TYP.

I

DD+ICCM

(mA)

IDD+I

MAX.

CCM

OFF 0 0 X <0.3 0.3
ADC reference only 0 1 X 1.6 2.2
CC 1 0 0 18.2 25.0
CC via DCC inputs 1 0 1 26.3 36.5
DCC (analog and digital readers) 1 1 0 31.0 41.0
DCC (digital readers only) 1 1 1 39.5 53.0

(mA)

April 1996 6

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

Table 2 Modes of operation.

CONTROL

MODE

SIGNAL

CS SD ADR

DCC

PARTCCPARTFBAMPS

(1)

OFF 0 0 X off off off off OUTX; RDMUX;

ADC

REF

OUTPUTS

SWITCHED OFF

OUTPUTS
ENABLED

−

OUTL; OUTR

ADC reference only 0 1 X off off off on OUTX; RDMUX;

V33

OUTL; OUTR
CC 1 0 0 off on on off OUTX; RDMUX OUTL; OUTR
CC via DCC inputs 1 0 1 on
DCC (analog and digital

1 1 0 on off off on OUTL; OUTR V33; OUTX;

readers)

(2)

on

(3)

on off OUTX; RDMUX OUTL; OUTR

RDMUX

DCC (digital readers only) 1 1 1 on off on on OUTL; OUTR V33; OUTX;

RDMUX

Notes

1. ADR = 1 when pin INL and/or INR is connected to VSS.

2. Preamplifiers only; AGC disabled.

3. Output stages only; VA14 off.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V

DD
CCM

supply voltage VSS= 0; V

supply voltage feedback amplifiers −0.3 5.5 V
∆V difference in ground potential between V
V

I

I

EEM

I

CCM

I

n

I

DD

I

SS

I

max

P

tot

T

stg

T

amb

V

es

voltage on any pin VDD+ 0.5 < 5.5 V 0.3 VDD+ 0.5 V

maximum ground current (pin 28) −±120 mA

maximum supply current (pin 29) −±120 mA

maximum current on pins 24, 26, 30 and 32 −±80 mA

maximum supply current (pin 38) −±80 mA

maximum ground current (pin 39) −±80 mA

maximum current on all other pins −±20 mA

total power dissipation − 350 mW

storage temperature −65 +150 °C

operating ambient temperature −30 +85 °C

electrostatic handling −2000 +2000 V

and V

SS

EEM

=0 −0.3 5.5 V

EEM

00V

April 1996 7

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

THERMAL RESISTANCE

SYMBOL PARAMETER THERMAL RESISTANCE

R

th j-a

CHARACTERISTICS

= 5 V; V

V

DD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DD

V

CCM

I

DDDCC

I

DDCC

I

CCM

I

DD

I

tot

V

ref

from junction to ambient in free air 90 K/W

= 5 V; VSS=V

CCM

EEM

= 0 V; f

= 3.072 MHz; T

clk

=25°C; unless otherwise specified.

amb

supply voltage 4.5 5.0 5.5 V
supply voltage feedback

4.5 5.0 5.5 V

amplifiers
supply current DCC part CS = 1; SD = 1; ADR = 0 21 31 41 mA

CS = 1; SD = 1; ADR = 1 21 31 41 mA

supply current CC
amplifiers

supply current feedback

CS = 1; SD = 0; ADR = 0 7 9.7 13 mA
CS = 1; SD = 0; ADR = 1 12.5 17.8 24.5 mA
note 1 6.0 8.5 12 mA

amplifiers
supply current

CS = 0; SD = 1 1.1 1.6 2.2 mA

(ADC reference ON)
total current in OFF state

of IDD and I

CCM

reference voltage for DCC

CS = 0; SD = 0 −−300 µA

Io< −1 mA 1.3 1.4 1.5 V

inputs (pin 21)
reference voltage for DCC

I

< −20 µA 1.25 1.4 1.55 V

o

sense (pin 7)
reference voltage for CC

< −20 µA 1.25 1.4 1.6 V

I

o

sense (pin 35)
reference voltage for ADC

< −2.5 mA 3.2 3.3 3.4 V

I

o

(pin 36)

DCC part

MPLIFIER CHANNEL 0 TO 7; NOTE 2

A
G amplifier gain f

∆G relative gain f

V

O

V

os

DC output voltage note 4 1.8 2.1 2.4 V
DC offset voltage between

channels

V

n(ref)

input referred noise
voltage

∆V

n(ref)

3 × standard deviation in
amplitude spread of input
referred noise

April 1996 8

= 50 kHz 75 78 81 dB

i

= 100 kHz 75 80 83 dB

f

i

= 10 kHz; note 3 −14 −12 −10 dB

i

= 300 kHz; note 3 −22 −12 −3dB

f

i

note 4 −−300 mV

fi= 50 kHz; R

fi= 50 kHz; R

=70Ω− 1.9 − nV√Hz

source

=70Ω− 0.5 − nV√Hz

source

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

THD total harmonic distortion fi= 10 kHz;

V1= 0.5 V (RMS)

Z

i

SR supply rejection f

α

cs

input impedance to V

SS

= 50 kHz; note 5 −−18 −30 dB

i

channel separation fi= 10 kHz 30 40 − dB
AMPLIFIER AUXILIARY CHANNEL; CHANNEL X; NOTE 2
G

2

G

1

amplifier gain at pin 2 fi= 100 Hz to 100 kHz 48 51 54 dB

amplifier gain at pin 1 fi= 100 Hz to 100 kHz;

note 6

V

n(ref)

input referred noise

fi= 10 kHz; R

source

voltage
∆V

n(ref)

3 × standard deviation in

fi= 10 kHz; R

source

amplitude spread of input

referred noise
V

2(rms)

maximum output voltage

fi= 10 kHz 0.5 −−V

(RMS value)
THD total harmonic distortion f

= 1 kHz;

i

V1= 0.5 V (RMS)
SR supply rejection f
R

L(DC)

C

L(AC)

Z

o

DC load to VSS (pin 2) 10 −−kΩ
AC load to VSS (pin 2) −−100 pF
output impedance at pin 2

= 1 kHz; note 5 −−6−15 dB

i

see Table 2 1 −−MΩ

in OFF state
OUTPUT BUFFER: PIN 1 (RDMUX)
V

1(rms)

maximum output voltage

RL=2kΩ 0.5 −−V

(RMS value)
R

L(DC)

t

set

DC load to V

SS

settling time RL=2kΩ; CL= 100 pF;

settling within 10 mV

Z

o

output impedance in OFF

see Table 1 1 −−MΩ

state
V

1(rms)

∆V

1

I

source

AGC level (RMS value) note 7 120 270 410 mV

AGC voltage range 8 9.5 12 dB

AGC source current

(pin 43)
I

sink

AGC sink current (pin 43) − 0.7 −µA
SELECTED LOGIC AND MODE SWITCH: PINS RDCLK, RDSYNC, CS AND SD
V

IH

V

IL

I

LI

C

i

HIGH level input voltage 2.2 − 5.0 V

LOW level input voltage 0 − 1.0 V

input leakage current −10 0 +10 µA

input capacitance note 8 −−10 pF

=70Ω− 1.9 − nV√Hz

=70Ω− 0.5 − nV√Hz

−−40 −30 dB

811−kΩ

62 65 68 dB

−−40 −30 dB

2 −−kΩ

− 100 150 ns

− 80 −µA

April 1996 9

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

su

t

h

t

r

V

ADR

V

TEST

SENSE CURRENT SOURCE
I

DSEN(min)

I

DSEN(max)

I

no

Z

o

CC part

set-up time RDCLK and

note 9 20 −−ns

RDSYNC

hold time RDCLK and

note 9 20 −−ns

RDSYNC

rise time note 9 −−50 ns

ADR mode detection level

0 − 0.4 V

(pins 25 and 31)

test mode detection level

0 − 0.4 V

(pin 27)

minimum output current note 10 −−5mA

maximum output current note 11 20 −−mA

output noise current note 11 − 20 − pA√Hz

output impedance I

=10mA 20 −−kΩ

DSEN

A

NALOG AMPLIFIER

G amplifier gain fi= 20 Hz to 20 kHz 43 45 47 dB
V

i(rms)

input voltage level

fi= 1 kHz − 2.75 − mV

(RMS value)
V

∆V

n(ref)

n(ref)

input referred noise

voltage

3 × standard deviation in

amplitude spread of input

fi= 10 kHz;
R

source

= 300 Ω

fi= 10 kHz;
R

source

= 300 Ω

− 2.8 − nV√Hz

− 1.0 − nV√Hz

referred noise
V

o(rms)

maximum output voltage

fi= 1 kHz 0.5 −−V

(RMS value)
THD total harmonic distortion f

= 1 kHz;

i

−−60 −50 dB

Vo= 0.5 V (RMS)

SR supply rejection f

α

R

cs

L(DC)

channel separation fi= 1 kHz 40 −−dB

DC load to V

SS

= 1 kHz; note 5 − 37 − dB

i

10 −−kΩ

(pins 22 and 34)
C

L(AC)

AC load to V

SS

−−300 pF

(pins 22 and 34)
Z

o

output impedance in OFF

see Table 2 1 −−MΩ

state (pins 22 and 34)
ANALOG INPUT VIA DCC PREAMPLIFIERS
G amplifier gain fi= 20 Hz to 20 kHz 48 51 54 dB

V

i(rms)

input voltage level

fi= 1 kHz − 1.4 − mV

(RMS value)
V

n(ref)

input referred noise

fi= 10 kHz; R

=70Ω− 1.9 − nV√Hz

source

voltage

April 1996 10

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆V

n(ref)

V

o(rms)

THD total harmonic distortion f

SR supply rejection f

α

cs

FEEDBACK AMPLIFIER
I

o(rms)

THD total harmonic distortion note 13 −−60 −50 dB
B bandwidth note 14 50 −−kHz

3 × standard deviation in

fi= 10 kHz; R

=70Ω− 0.5 − nV√Hz

source

amplitude spread of input

referred noise

maximum output voltage

fi= 1 kHz 0.5 −−V

(RMS value)

= 1 kHz;

i

−−40 −30 dB

V1= 0.5 V (RMS)

= 1 kHz; auxiliary data

i

−−6−dB

channel; see Fig.6

channel separation fi= 1 kHz 40 −−dB

maximum output current

note 12 30 −−mA

(RMS value)

Notes

1. CS = 1, SD = 1, ADR = 1; CS = 1, SD = 0, ADR = 0; CS = 1, SD = 0, ADR = 1; feedback amplifiers unloaded. The
supply pins for the feedback amplifiers are pins 28 and 29. The supply pins for all other circuits are pins 38 and 39
(see Tables 1 and 2).

2. AGC circuit OFF (maximum gain; pin 43 connected to VSS).

3. Gain relative to gain at fi= 50 kHz. See Fig.5 for typical frequency response.

4. Difference between minimum and maximum DC level at the outputs of the data channels. To be measured at pin 1.

5. See Figs 6 and 7 for typical supply rejection.

6. Pin 2 AC-coupled to pin 3 via 100 nF capacitor.

7. Measured with a continuous sinewave of 10 kHz at pin 1, multiplexer in a fixed position. A 1 V (RMS) sinewave
corresponds with a multiplexed DCC signal of 4.3 V (p-p).

8. Periodically sampled, not tested.

9. Timing relationship between the edges of RDCLK and RDSYNC is illustrated in Fig.3. Figure 4 illustrates the action
of the multiplexer switches.

10. The output current can be adjusted by connecting a resistor between the adjust pin and VSS. A 68 Ω resistor will
produce 10 mA (typ.) through the MRHs (see Fig.9).

11. A resistor of 210 Ω connected between sense current output and VDD; frequency range from 10 kHz to 100 kHz;
sense current = 10 mA; pin 7 decoupled to VSS by 10 µF capacitor.

12. Closed loop; unity gain; fi= 1 kHz; THD < −45 dB; RL=40Ω; in accordance with Fig.10.

13. Closed loop; unity gain; fi= 1 kHz; 10 mA (RMS) output current into 40 Ω; in accordance with Fig.10.

14. Closed loop; unity gain; −3 dB bandwidth; measured in test circuit of Fig.10.

April 1996 11

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

Fig.3 Timing relationship between the edges of RDCLK and RDSYNC.

April 1996 12

Fig.4 Multiplexer timing diagram.

Philips Semiconductors Preliminary specification

BBBB
BBBB

BBBB
BBBB

DCC read amplifier TDA1318

Fig.5 Typical gain of main data channel (AGC off).

Fig.6 Typical supply rejection of main data and auxiliary data channel (AGC off).

April 1996 13

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

Fig.7 Typical supply rejection of analog amplifier.

TEST INFORMATION

The circuit can be set to the TEST mode by connecting
pin 27 to VSS. In this configuration the multiplexer at pin 3
allows monitoring of the input stage and low-pass filter of
each digital amplifier, and also allows input to the
high-pass filter of the second stage. The test multiplexer
operates in phase with the output multiplexer.

Measurement of the gain of the digital channels can be
carried out in two steps: the gain from DCC input to pin 3,
and the gain from pin 3 to pin 1.

Figure 8 illustrates how to use pin 3 in the test mode;
CL< 20 pF, RL> 100 kΩ, Ci> 47 nF, R
The DC voltage, when driving pin 3, should be 0.7 V

bias

=1kΩ.

greater than the measured DC level at pin 3 in order to
shut-off the emitter follower. The impedance of the sense
current source outputs can be measured from the
difference in sense current when applying different
voltages to the sense current output. This voltage can vary
from 1.5 V to V
sense current sources.

The feedback amplifiers consist of two operational
amplifiers providing one input and a differential output with
respect to the internal 2.5 V reference (see Fig.10).

. Figure 9 illustrates the principle of the

DD

April 1996 14

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

Fig.8 Test by using MUXINX (pin 3).

Fig.9 Principle of the sense current source.

April 1996 15

Fig.10 Principle of the feedback amplifier and test

circuit.

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

APPLICATION INFORMATION

full pagewidth

4.6 to 5.5 V

1 Ω

R

10 µF

10 Ω

5 V

10

100

100

10

right

equalization

amplifier

10 kΩ

22

23

OUTR

READ

AMPLIFIER 2

27 kΩ

24

INMFR

Ω

10

Ω

40

RDCLK

RDMUX

10

41

RDSYNC

37

10

kΩ

100

10 kΩ

µF

nF

V

38 29

nF

µF

21

V14 V

nF

2

CCM

DD

OUTX

3

MUXINX

TA8 TA9

1

1 nF

42

36

CS

SD

V33

TDA1318

feedback

4.7 kΩ

µF
10

263433

MFR2

MFR1

5 V

level

1 kΩ

1.8 nF

OUTL

kΩ
82

4.7 kΩ

32

INMFL

DC bias

27 kΩ

MFL1

5 V

4.7 kΩ

kΩ
82

1 kΩ

1.8 nF

1 nF

30

MFL2

AGC

BIAS

V

VD14

EEM

V

SS

V

DSENADJ1

DSENADJ1

DC bias

74443

456 3928

left

equalization

amplifier

Ω

10

Ω

10

µF

0.68

µF

2.2

10

µF

68 Ω68 Ω68 Ω

kΩ

feedback

level

4.7

10 µF

10 kΩ

MBD050

TA1 TA2

Fig.11 Application diagram.

INX25

INX0

IN01

IN1

DSEN1

IN23

IN34

IN4

DSEN2

IN56

IN67

IN7

10 µF 100 nF

10

µF

14

11

F

µ

1

µF
1

10nF10nF10

0

X

8

12

13

15

F

µ

1 µF

1

F

µ

1

10nF10nF10

nF

1

2

9

16

F

µ

1

3

181920

17

F

F

µ

1

F

µ

1

10nF10nF10

µF
1

5

µ

1

nF

4

April 1996 16

DSEN3

10

6

INR

INRL

252731

µF

2.2

µF

4.7

nF

7

µF

2.2

INL

VA14

35

10

10

R

DSENADJ1

nF

nF

10

µF

BSV52

68 Ω 68 Ω

BSV52

TA2

TA2

TA9

TA8

L

FLEX

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

ok, full pagewidth

4.6 to 5.5 V

10 Ω

R

10 µF

10 Ω

5 V

10

100

100

10

right

equalization

amplifier

kΩ
10

OUTR

INMFR

READ

AMPLIFIER 2

27 kΩ

24

Ω

10

10

kΩ

nF

100

2

3

1

10 kΩ

OUTX

RDMUX

CCM

V

DD

V14 V

MUXINX

µF

nF

38 29

nF

µF

21

40

RDCLK

10

41

RDSYNC

Ω

37

42

362223

CS

SD

V33

TDA1318

kΩ

4.7

kΩ
1

1 nF

MFR1

feedback

level

1.5 µF

1.8 nF

1 nF

26

MFR2

5 V

82 kΩ

34

OUTL

33

DC bias

4.7 kΩ

32

INMFL

27 kΩ

MFL1

5 V

4.7 kΩ

kΩ
82

kΩ
1

1.8 nF

30

MFL2

AGC

BIAS

V

VD14

EEM

V

SS

V

DSENADJ1

DSENADJ1

DC bias

74443

456 3928

left

equalization

amplifier

Ω

10

Ω

10

µF

0.68

µF

2.2

10

µF

68 Ω68 Ω68 Ω

kΩ
10

4.7 kΩ

feedback

level

µF
10

MBD051

INX25

INX0

IN01

IN1

DSEN1

IN23

IN34

IN4

DSEN2

IN56

IN67

100 nF

10 µF

14

11

1 µF

1 µF

10nF10nF10

0

X

8

12

13

151617

F

µF

µ

1

1

µF
1

10nF10nF10

nF

1

2

9

181920

µF

µF

1

nF

µF
1

µF
1

10nF10nF10

5

1

µF
1

4

3

April 1996 17

IN7

DSEN3

10

6

INR

INRL

252731

nF

7

INL

35

VA14

DSENADJ1

Fig.12 Application diagram, read amplifier 2 in ADR mode.

FLEX

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

34 mA typ

3.8 to 5.5 V

ok, full pagewidth

0.1

0.1

0.1

µF

µF

µF

3

DD

V

DDAD

V

91112

BIASA

43

37

2

LABEL

RDCLK

RDSYNC

F24

VIN

5

24.576 MHz

82

120 Ω

to

or TFE

microcontroller

38

36

AENV

VIRGIN

to DDSP

23242526272829301514432353433

CH7

CH6

CH5

CH4

CH3

CH2

CH122CH0

AUX

SAA2032

REFP

REFN

7

6

0.1

µF

0.1

pF

virtual ground

µF

point

to dolby

circuitry

right

n.c.

16

TEST

TEST

40

41

ANALOG

EQUALIZER

ANEYE

DIGEYE

TEST1

4

to dolby

circuitry

VAL

TEST4

18

left

LTCLK

LTENDEQ

TEST5

TEST6

192021

ANALOG

EQUALIZER

to

microcontroller

31

V

LTCNT1

LTCNT0

LTDATA

V

V

V

V

V

TEST7

TEST10

42

SS

SS

SS

SSAD

SSA

SSA

39171310148

testpoint

1 kΩ

OSC

1 nF

87 mA typ

4.6 to 5.5 V

1 Ω
R

10 µF

to AMY head

right A

dolby

level

SDA

SELA

231404137423622232426343332

CS

SD

OUTX

RDCLK

RDMUX

MUXINX

10

µF

µF

0.1
CCM

V

38 29

DD

10 Ω

10 µF

21

V14 V

10 µF

INX25

INX0

IN01

IN1

1112138151617181920252731

14

0.1µF

CB

RDSYNC

DSEN1

IN23

TO

IN34

A

HEAD

V33

OUTR

TDA1318

IN4

DSEN2

9

MFR1

INMFR

IN56

IN67

MFR2

IN7

10

OUTL

DSEN3

dolby

INMFL

INR

level

30

MFL1

INRL

left A

MFL2

BIAS

V

SS

V

DSENADJ1

INL

VA14

35

AGC

74443

VD14

EEM

V

DSENADJ1

10

0.1

10 Ω

for application diagram TDA1318

READ AMPLIFIER SECTOR A

456 3928

DSENADJ1

to AMY head

CB

SDA

SELA

231404137423622232426343332

CS

SD

OUTX

RDCLK

RDMUX

MUXINX

µF

µF

CCM

V

38 29

DD

10 µF

21

V14 V

10 µF

INX25

INX0

IN01

IN1

1112138151617181920252731

14

0.1µF

RDSYNC

DSEN1

IN23

TO

IN34

V33

IN4

9

B

HEAD

dolby

level

right B

MFR1

OUTR

INMFR

TDA1318

DSEN2

IN56

IN67

MFR2

IN7

10

dolby

OUTL

DSEN3

level

INMFL

INR

right B

30

MFL1

INRL

MFL2

BIAS

V

SS

V

DSENADJ1

INL

VA14

35

MBD052

AGC

74443

VD14

EEM

V

DSENADJ1

5 6 39 28

4

DSENADJ1

Fig.13 Read amplifier 2 and DEQ25 interconnection diagram.

April 1996 18

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

PACKAGE OUTLINE

seating

plane

0.15 S

12.9

12.3

44

1

pin 1 index

11

12

34

22

S

1.2
(4x)

0.8

33

0.8

0.40

0.20

23

B

10.1

9.9

12.9

12.3

B

0.15 M

Dimensions in mm.

0.8

0.40

0.20

10.1

9.9

0.15 M A

1.85

1.65

MBC864 - 2

Fig.14 44-lead quad flat-pack; plastic (QFP44S10, SOT307-2).

April 1996 19

0.50

0.20

1.2

0.8

A

(4x)

detail X

0.95

0.55

0.85

0.75

X

0.25

0.14

0 to 10

2.35

1.85

o

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

SOLDERING
Plastic quad flat-packs

YWAVE

B
During placement and before soldering, the component

must be fixed with a droplet of adhesive. After curing the
adhesive, the component can be soldered. The adhesive
can be applied by screen printing, pin transfer or syringe
dispensing.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder bath is
10 s, if allowed to cool to less than 150 °C within 6 s.
Typical dwell time is 4 s at 250 °C.

A modified wave soldering technique is recommended
using two solder waves (dual-wave), in which a turbulent
wave with high upward pressure is followed by a smooth
laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
applications.

Y SOLDER PASTE REFLOW

B
Reflow soldering requires the solder paste (a suspension

of fine solder particles, flux and binding agent) to be

applied to the substrate by screen printing, stencilling or
pressure-syringe dispensing before device placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 min at 45 °C.

EPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING

R

IRON OR PULSE

-HEATED SOLDER TOOL)

Fix the component by first soldering two, diagonally
opposite, end pins. Apply the heating tool to the flat part of
the pin only. Contact time must be limited to 10 s at up to
300 °C. When using proper tools, all other pins can be
soldered in one operation within 2 to 5 s at between 270
and 320 °C. (Pulse-heated soldering is not recommended
for SO packages.)

For pulse-heated solder tool (resistance) soldering of VSO
packages, solder is applied to the substrate by dipping or
by an extra thick tin/lead plating before package
placement.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

April 1996 20

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

NOTES

April 1996 21

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

NOTES

April 1996 22

Philips Semiconductors Preliminary specification

DCC read amplifier TDA1318

NOTES

April 1996 23

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. [phone], Fax. [phone]

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. [phone], Fax. [phone]

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P.O. Box 7383 (01064-970).
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Tel. [phone], Fax. [phone]
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Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. [phone] 911, Fax. [phone]

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KWAI CHUNG, N.T. Tel. [phone], Fax. [phone]

India: Philips Components Division,

A Block Shivsagar Estate Worli,
Dr. Annie Besant Rd., Bombay 400 018
Tel. [phone], Fax. [phone]

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,
Tel. [phone], Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. [phone], Fax. [phone]

Italy: Viale F. Testi, 327, 20162 MILANO,

Tel. [phone], Fax. [phone]

Japan: Philips Bldg13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. [phone], Fax. [phone]

Korea: (Republic of) Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. [phone], Fax. [phone]

Mexico: Philips Components, 5900 Gateway East, Suite 200,

EL PASO, TX 79905, Tel. [phone], Fax. [phone]

Netherlands: Postbus 90050, 5600 PB EINDHOVEN,

Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

th

floor, Suite 51,

Pakistan: Philips Markaz, M.A. Jinnah Rd., KARACHI 3,

Tel. [phone], Fax. [phone]

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Metro MANILA, Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Tel. [phone], Fax. [phone]

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Taiwan: 23-30F, 66, Chung Hsiao West Road, Sec. 1,

P.O. Box 22978, TAIPEI 10446,
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60/14 MOO 11, Bangna - Trad Road Km. 3
Prakanong, BANGKOK 10260,
Tel. [phone] to 9, (2)398-2083, Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL,

Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Limited, P.O. Box 65,

Philips House, Torrington Place, LONDON, WC1E 7HD,
Tel. [phone], Fax. [phone]

United States:INTEGRATED CIRCUITS:

811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]
DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd.,
P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404,
Tel. [phone] and [phone], Fax. [phone]

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. [phone], Fax. [phone]

For all other countries apply to: Philips Semiconductors,
International Marketing and Sales, Building BAF-1,
P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Telex 35000 phtcnl, Fax. [phone]

SCD30 © Philips Electronics N.V. 1994

All rights are reserved. Reproduction in whole or in part is prohibited without the
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Philips Semiconductors