Datasheet TC901CPA, TC901COA Datasheet (TelCom Semiconductor)

MONOLITHIC, AUT O-ZEROED OPERATIONAL AMPLIFIER

1

TC901

FEATURES

■ Second-Generation Monolithic,

Chopper-Stabilized Op Amp

■ No External Capacitors Required

■ Single-Supply Operation ........... ±15V or 5V to 32V

■ Supply Current............................450µA at 15V, Typ

■ Input Offset Voltage ...................................7µV, Typ

■ Common-Mode Rejection Ratio ............140dB, Typ

■ Open-Loop Gain ............ 140dB Into 10k Load, Typ

■ Input Noise ......................... 5µV at 10Hz Bandwidth

■ Pinout Compatible With ICL7650

■ Lowest Parts Count Chopper Op Amp

PIN CONFIGURATION (DIP and SOIC)

NC
–INPUT
+INPUT

V

SS

TC901CPA

1
2
3
4

8

–

+

NC

DD

–INPUT
+INPUT

7

V

6

OUTPUT
NC

5

NC = NO INTERNAL CONNECTION

V

NC

SS

TC901COA

1
2
3
4

8

–

+

NC
V

7

OUTPUT

6

NC

5

DD

GENERAL DESCRIPTION

The TC901 is a monolithic, auto-zeroed operational
amplifier. It is a second-generation design of the TC91X
CMOS chopper-stabilized op amps with on-chip capacitors.

Elimination of the external capacitors allows the de­signer to increase reliability, lower cost, and simplify design
by lowering parts count.

Since the TC901 is an auto-zeroing op amp, input offset
voltage is very low. More important, there is almost zero drift
with time. This eliminates production line adjustments, as
well as periodic calibration.

Notable electrical characteristics are low supply cur­rent (450µA, typical), single-supply operation (5V to 32V),
low input offset voltage (7µV, typical), low noise (<5µV

P-P

typical, for a 10Hz bandwidth), and fast recovery from
saturation without the use of external clamp circuitry.

This device is supplied in 8-pin plastic DIP and plastic
SOIC packages. It is pin compatible with bipolar, CMOS,
JFET and other chopper-stabilized op amps using the
industry-standard 741 pinout.

ORDERING INFORMATION

Temperature

Part No. Package Range

TC901COA 8-Pin SOIC 0°C to +70°C
TC901CPA 8-Pin Plastic DIP 0°C to +70°C

2

3

,

4

5

FUNCTIONAL BLOCK DIAGRAM

–INPUT

+INPUT

2

3

NOTE: Internal capacitors. No external capacitors required.

TELCOM SEMICONDUCTOR, INC.

V

DD

47

V CORRECTION AMPLIFIER

OS

+

–

A

+

–

V

SS

*

*

MAIN
AMPLIFIER

A

B

B

+

–

INTERNAL

OSCILLATOR

(f 200 Hz)

OSC

LOW IMPEDANCE
OUTPUT BUFFER

TC901

≈

6

OUTPUT

6

7

8

TC901- 7 9/5/96

3-259

TC901

MONOLITHIC, AUTO-ZEROED

OPERATIONAL AMPLIFIER

ABSOLUTE MAXIMUM RATINGS*

Package Power Dissipation (TA = ≤ 70°C)

Plastic DIP ......................................................730mW

Total Supply Voltage (VDD to VSS) ........................... +36V

Input Voltage ........................ (V

+ 0.3V) to (V

DD

– 0.3V)

SS

Current Into Any Pin.................................................10mA

While Operating................................................100µA

Storage Temperature Range ................– 65°C to +150°C

Lead Temperature (Soldering, 10 sec) .................+300°C

Operating Temperature Range

Plastic SOIC ...................................................470mW

*Static-sensitive device. Appropriate precautions should be taken when
handling, shipping, or storing these devices. Stresses above those listed
under "Absolute Maximum Ratings" may cause permanent damage to the
devices. These are stress ratings only and functional operation of the
device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.

C Device ................................................0°C to +70°C

ELECTRICAL CHARACTERISTICS: V

±15V, TA = +25°C, unless otherwise indicated.

S

Symbol Parameter Test Conditions Min Typ Max Units

V

OS

TCV

OS

I

BIAS

I

OS

e

N

e

N

CMRR Common-Mode Rejection VSS ≤ VCM ≤ VDD –2V 120 140 — dB

CMVR Common-Mode Voltage VS = ±5V to ±15V V

A

OL

V

OUT

BW Closed-Loop Bandwidth Closed-Loop Gain = +1 — 0.8 — MHz

SR Slew Rate RL = 10 kW, CL = 50 pF — 2 — V/µsec
PSRR Power Supply Rejection Ratio VS = ±5V to ±15V 120 140 — dB
V

S

I

S

NOTES: 1. Characterized; not 100% tested.

2. Single supply operation: VDD = +5V to +32V.

Input Offset Voltage TA = +25°C—715µV
(Figure 2)

Average Temperature 0°C ≤ TA ≤ +70°C — 0.05 0.15 µV/°C
Coefficient of Input (Note 1)
Offset Voltage

Average Input Bias TA = +25°C — 30 50 pA
Current 0°C ≤ T

≤ +70°C — 0.2 10 nA

A

–25°C ≤ TA ≤ +85°C — 0.2 10 nA

Average Input TA = +25°C — 50 100 pA
Offset Current TA = +85°C——1nA

Input Voltage Noise 0.1 to 1 Hz, RS ≤ 100Ω — 1.2 — µV

P-P

(Figure 1B)
Input Voltage Noise 0.1 to 10 Hz, RS ≤ 100Ω —5—µV

P-P

(Figure 1A)

Ratio

SS

—VDD –2 V

Range
Open-Loop Voltage Gain RL = 10 kΩ, VS = ±15V 120 140 — dB
Output Voltage Swing RL = 10 kΩ V

+ 1 — VDD –1.2 V

SS

(Figure 7)

Operating Supply Voltage Note 2 ±3—±16 V
Range

Quiescent Supply (Figure 2) VS = ±15V — 0.45 0.6 mA

3-260

TELCOM SEMICONDUCTOR, INC.

MONOLITHIC, AUTO-ZEROED
OPERATIONAL AMPLIFIER

1

TC901

Overload Recovery

The TC901 recovers quickly from output saturation.
Typical recovery time from positive output saturation is 20
msec. Negative output saturation recovery time is typically
5 msec.

Thermocouple Errors

Heating a junction made from two different metallic
wires causes current flow. This is known as the Seebeck
effect. An open-circuit voltage (Seebeck voltage) can be
measured across the junction. Junction temperature and
metal type determine the magnitude. Typical values are

0.1µV/°C to 10µV/°C. Thermal-induced voltages can be
many times larger than the TC901's offset voltage drift.
Unless unwanted thermocouple potentials can be con­trolled, system performance will be less than optimum.

Unwanted thermocouple junctions are created when
leads are soldered or sockets/connectors are used. Low
thermoelectric coefficient solder can reduce errors. A 60%
Cd/40% Sn Pb solder has one-tenth the thermal voltage of
common 64% Sn/36% Pb solder at a copper junction.

The number and type of dissimilar metallic junctions in
the input circuit loop should be balanced. If the junctions are
kept at the same temperature, their summation will add to
zero, canceling errors (Figure 7).

Shielding precision analog circuits from air currents —
especially those caused by power dissipating components
and fans — will minimize temperature gradients and mini­mize thermocouple-induced errors.

J = J

3

4

NO TEMPERATURE DIFFERENTIAL

J = J

2

5

AND SAME METALLIC CONNECTION

J = J

1

6

J

3

J

2

J

1

PACKAGE
PIN

Larger voltages can turn the p-n-p-n device on, causing
excessive device power supply current and excessive power
dissipation. TC901's power supply should be established at
the same time (or before) input signals are applied. If this is
not possible, input current should be limited to 100µA to
avoid triggering the p-n-p-n structure.

Pin Compatibility

The CMOS TC901 is pin compatible with other chopper­stabilized amplifiers, such as the 7650, 7652 and 1052.
Amplifiers such as the 7650 require 0.1µF external capaci­tors connected to pins 1 and 8. The TC901 includes the
chopper capacitors on-chip, so external capacitors are not
required. Since pins 1, 5 and 8 of the TC901 are not
connected, the TC901 can directly replace other chopper­stabilized amplifiers in existing circuits.

The TC901 pinout also matches many popular bipolar
and JFET op amps, such as the OP-07, OP-20, LM101,
LM108, 356 and 741. In many applications that operate from
±15V power supplies, the TC901 offers superior electrical
performance and is a functional pin-compatible replace­ment. Offset voltage correction potentiometers, compensa­tion capacitors, and chopper-stabilization capacitors can be
removed when retrofitting existing equipment designs.
System parts count, assembly time, and system cost are
reduced, while reliability and performance are improved.

Overload Recovery

The TSC90X Series recovers quickly from output
saturation. Typical recovery time from positive output satu­ration is 20 msec. Negative output saturation recovery time
is typically 5 msec.

2

3

4

5

6

J

4

J

5

J2J

+–+–

–

V

J

3

3

+

V = V + V + V – V – V – V = 0

+

V

J

4

4

–

Figure 7. Unwanted Thermocouple Errors Eliminated by Reducing
Thermal Gradients and Balancing Junctions

V2V

T123456

V5V

+–+–

J

5

J

1
1

6

J

6

6

V = 0

T

Avoiding Latch-Up

Junction-isolated CMOS circuits inherently contain a
parasitic p-n-p-n transistor circuit. Voltages exceeding the
supplies by 0.3V should not be applied to the device pins.

TELCOM SEMICONDUCTOR, INC.

7

8

3-261

20 msec/DIV

OUTPUT
5 V/DIV

OUTPUT
5 V/DIV

2V

0V

0V

–2V

5 msec/DIV

INPUT

2 V/DIV

OUTPUT
5 V/DIV

2V
0V

0V

–15V

TC901

(B) 0.1 TO1.0 Hz (A) 0.1 TO 1.0 Hz

1 µV/DIV 1 µV/DIV

0 1 2 3 4 5 6 7 8

1 sec/DIV

MONOLITHIC, AUTO-ZEROED

OPERATIONAL AMPLIFIER

9 10

VOS (µV)

10
12
14
16

18

20

22

3-262

4
6
9

0 2 4

Figure 1. Input Voltage Noise

VOS

6 8 10 12 14 16 18 20

±VS (V)

VDD (µA)

450
400
350

300
250
200
150
100

50

0

Figure 3. Recovery From Negative Saturation

Figure 2. VOS and IDD vs Supply Voltage Figure 4. Recovery From Positive Saturation

R

2

R

1

+15V
–

+

–15V

GAIN = 40
R

= 1kΩ

1

R

= 40kΩ

2

Figure 5. Saturation Test Circuit

OUTPUT

+50
+40
+30
+20
+10

0

GAIN (dB)

–10
–20
–30
–40

PHASE MARGIN

10kΩ with 50 pF LOAD

36° at 700 kHz at 70°C
40° at 800 kHz at 25°C

0 10 100 1k

10k 100k 1M

FREQUENCY (Hz)

Figure 6. Phase-Gain

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+240

+180

+120

+60

0°C

–120

–180