Datasheet TC835CPI, TC835CKW, TC835CBU Datasheet (Microchip Technology)

TC835

Personal Computer Data Acquisition A/D Converter

Features

• Upgrade of Pin-Compatible TC7135, ICL7135

• 200kHz Operation

• Single 5V Operation With TC7660

• Multiplexed BCD Data Output

• UART and Microprocessor Interface

• Control Outputs for Auto-Ranging

• Input Sensitivity: 100µV

• No Sample and Hold Required

Applications

• Personal Computer Data Acquisition

• Scales, Panel Meters, Process Controls

• HP-IL Bus Instrumentation

Device Selection Table

Part Number Package Temperature Range

TC835CBU 64-PinPQFP 0°Cto+70°C

TC835CKW 44-Pin PQFP 0°Cto+70°C

TC835CPI 28-Pin PDI P 0°Cto+70°C

Note: Tape and Reel available for 44-Pin PQFP

package.

General Description

The TC835 is a low power, 4-1/2 digit (0.005%
resolution), BCD analog to digital converter (ADC) that
has been characterized for 200kHz clock rate opera­tion. The five conversions per second rate is nearly
twice as fast as the I CL7135 or TC7135. The TC835,
like the TC7135, does not use the external diode resis­tor rollover error compensation circuits required by the
ICL7135.

The multiplexed BCD data output is perfectforinterfac­ing to personal computers. The low cost, greater than
14-bit high-resolution and 100µV sensitivity makes the
TC835 exceptionally cost-effective.

Microprocessor-based data acquisition systems are
supported by the BUSY and STROBE
with the RUN/HOLD
OVERRANGE, UNDERRANGE, BUSY and RUN/
HOLD control functions, plus multiplexed BCD data
outputs, make the TC835 the ideal converter for µP­based scales, measurement systems and intelligent
panel meters.

The TC835 interfaces with full function LCD and LED
display decoder/drivers. The UNDERRANGE and
OVERRANGE outputs may be used to implement an
auto-ranging scheme or special display functions.

input of the TC835. The

outputs, along



2002 Microchip TechnologyInc. DS21478B-page 1

TC835

D

Package Type

V-

REF IN

ANALOG

COM

INT OUT

AZ IN

BUFF OUT

C

REF

C

REF

–INPUT

+INPUT

V+

(MSD) D5

(LSB) B1

B2

1

2

3

4

5

6

-

7

+

8

9

10

11

12

13

14

28-Pin PDIP

TC835CPI

UNDERRANGE

28

OVERRANGE

27

26

STROBE

RUN/HOLD

25

24

DIGTAL GND

23

POLARITY

22

CLOCK IN

21

BUSY

20

D1 (LSD)

19

D2

18

D3

17

D4

16

B8 (MSD)

15

B4

INT OUT

AZ IN

BUFF OUT

REF CAP–

REF CAP+

–INPUT

+INPUT

64-Pin PQFP

NCNCNC

44 43 42 41 39 3840

NC

1

2

3

4

5

6

7

8

V+

9

NC

10

NC

11

12 13 14 15 17 18

NC

NC

44-Pin PQFP

ANALOG

REF INV–UR

COMMON

TC835CKW

16

B2

B4

(LSB) B1

(MSD) D5

OR

STROBE

37 36 35 34

19 20 21 22

D4

D3

(MSB) B8

NC

NC

33

NC

32

NC

31

RUN/HOL

30

DGND

29

POLARITY

28

CLK IN

27

BUSY

26

NC

D1 (LSD)

25

D2

24

NC

23

NC

NC

OVERRANGE

UNDERRANGE

ANALOG COM

NOTES:

1. NC = No internal connection.

2. Pins 9, 25, 40 and 56 are connected to the die substrate. The potential at these pins is approximately V+.
No external connections should be made.

NC

NC
NC

NC

NC
NC

SUB

V–

REF IN

NC

NC

NC

NC

NCNCNC

NC

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

NC

61 60 59 58 57 56 55 545352 51 50 4964

63

62

NC

AZ IN

INT OUT

DGND

STROBE

RUN/HOLD

TC835CBU

NC

OUT

BUFF

BUF CAP–

POL

NC

SUB

SUB

D1

CLK IN

BUSY

NC

–INPUT

BUF CAP+

D2

NC

NC

NC

32

NC

+INPUT

NC

V+

48

NC

47

NC

46

NC

45

D3

44

D4

43

B3

42

B4

41

B2

40

SUB

39

B1

38

D5

37

NC

36

NC

35

NC

34

NC

33

NC

DS21478B-page 2



2002 Microchip TechnologyInc.

Typical Application

3

4

Address Bus

Control

Data Bus

TC835

+

5V

R 6522 P

PB0

Channel Selection

PA0
PA1
PA2

PA3
PA4
PA5
PA6
PA7
CA1
CA2

PB3PB2PB1

HCTS157

1Y
2Y
3Y

1B
2B
3B

1A
2A
3A

S

F

IN

V+ REF CAP

BUF

INPUT+

TC835

Analog

Common

F

IN

AZ

INT

V

Input

DGND

-

5V

POL
OR
UR
D5
B8
B4
B2

B1
D1
D2
D3
D4
STB
R/H

-15V

+15V

DG529

D

A

D

B

R

REF Voltage

WR

A1A0EN

Channel 1

Channel 2

Channel

Channel

Differential
Multiplexer



2002 Microchip TechnologyInc. DS21478B-page 3

TC835

1.0 ELECTRICAL
CHARACTERISTICS

Absolute Maximum Ratings*

Positive Supply Voltage......................................... +6V

*Stresses above those listed under "Absolute Maximum Rat­ings"maycause permanentdamage to the device.These are
stress ratings only and functional operation of the device at
these or any other conditions above t hose indicated in the
operation sections of the specifications is not implied. Expo­sure to Absolute Maximum R ating conditions for extended
periodsmay affectdevice reliability.

Negative Supply Voltage........................................-9V

Analog Input Voltage (Pin 9 or 10) ...V+ to V– (Note 2)

Reference Input Voltage (Pin 2) .....................V+ to V–

Clock Input Voltage ........................................ 0V to V

+

Operating Temperature Range................0°C to +70°C

StorageTemperature Range............. -65°C to +150°C

Package Power Dissipation (T

≤ 70°C)

A

28-Pin Plastic DIP ............................ 1.14Ω

44-Pin PQFP .................................... 1.00Ω

64-Pin PQFP .................................... 1.14Ω

TC835 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: TA=+25°C,F
Symbol Parameter Min Typ Max Unit Test Conditions

Analog

Display Reading with Zero Volt Input -0.0000 ±0.0000 +0.0000 DisplayReading Note 3, Note 4
ZeroReading TemperatureCoefficient — 0.5 2 µV/°C VIN=0V,(Note 5)

TC

Z

Full-Scale Temperature Coefficient — — 5 ppm/°C VIN=2V;

TC

FS

NL Nonlinearity Error — 0.5 1 Count Note 7

DNL Differential Linearity Error — 0.01 — LSB Note 7

Display Reading in Ratiometric Operation +0.9996 +0.9998 +1.0000 Display Reading V

±FSE ± Full Scale Symmetry Error (Rollover Error) — 0.5 1 Count –V

Input Leakage Current — 1 10 pA Note 4

I

IN

Noise — 15 — µV

e

N

Digital

Input Low Current — 10 100 µAV

I

IL

Input High Current — 0.08 10 µAV

I

IH

Output Low Voltage — 0.2 0.4 V IOL=1.6mA

V

OL

Output High Voltage;

V

OH

f

CLK

Note 1: Functional operation is not implied.

2: Limit input current to under 100 µA if input voltages exceed supply voltage.
3: Full scale voltage = 2V.
4: V
5: 0°C ≤ T
6: Externalreference temperature coefficient less than 0.01ppm/°C.
7: -2V ≤ V
8: |V
9: Test circuit shown in Figure 1-1.
10: Specification relatedtoclock frequency range over which the TC835 correctly performs its various functions.Increased

B

1,B2,B4,B8,D1–D5

Busy, Polarity,Overrange,

Underrange, Strobe

ClockFrequency 0 200 1200 kHz Note 10

=0V.

IN

≤ +70°C.

A

≤ +2V. Error of readingfrom best fit straightline.

IN

| = 1.9959.

IN

errors result at higher operating frequencies.

= 200kHz, V+ = +5V, V-= -5V,unless otherwise specified.

CLOCK

2.4 4.4 5 V I

4.9 4.99 5 V I

P-P

(Note 5, Note 6

IN=VREF

Peak to Peak Value not
Exceeded 95% of Time

IN
IN

OH
OH

,(Note 3)

=+VIN, (Note 8)

IN

=0V
=+5V

=1mA
=10µA

DS21478B-page 4



2002 Microchip TechnologyInc.

TC835 ELECTRICAL S P EC IFICATIONS (CONTINUED)

TC835

Electrical Characteristics: TA=+25°C,F
Symbol Parameter Min Typ Max Unit Test Conditions

Power Supply

V+ Positive Supply Voltage 4 5 6 V
V– Negative SupplyVoltage -3 -5 -8 V

I+ PositiveSupply Current — 1 3 mA f
I– Negative Supply Current — 0.7 3 mA f

PD Power Dissipation — 8.5 30 mΩ f

Note 1: Functional operation is not implied.

2: Limit input current to under 100 µA if input voltages exceed supply voltage.
3: Full scale voltage = 2V.
4: V

=0V.

IN

5: 0°C ≤ T
6: Externalreference temperature coefficient less than 0.01ppm/°C.
7: -2V ≤ V
8: |V
9: Test circuit shown in Figure 1-1.
10: Specification relatedtoclock frequency range over which the TC835 correctly performs its various functions.Increased

errors result at higher operating frequencies.

≤ +70°C.

A

≤ +2V. Error of readingfrom best fit straightline.

IN

| = 1.9959.

IN

= 200kHz, V+ = +5V, V-= -5V,unless otherwise specified.

CLOCK

CLK
CLK
CLK

=0Hz
=0Hz
=0Hz



2002 Microchip TechnologyInc. DS21478B-page 5

TC835

2.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1: PIN FUNCTION TABLE

Pin Number
28-Pin PDIP

1 V- Negative powersupply input.
2 REF IN External reference input.
3 ANALOG COMMON Reference point for REF IN.
4 INT OUT Integrator output. Integrator capacitor connection.
5 AZ IN Auto zero input. Auto zero capacitor connection.
6 BUFF OUT Analog input buffer output. Integrator resistor connection.
7C
8C
9 -INPUT Analog input. Analoginputnegative connection.

10 +INPUT Analog input. Analog input positive connection.

11 V+ Positive power supplyinput.
12 D5 Digit drive output.Most Significant Digit(MSD)
13 B1 Binary CodedDecimal (BCD) output.LeastSignificantBit(LSB)
14 B2 BCD output.
15 B4 BCD output.
16 B8 BCD output. Most Significant Bit (MSB)
17 D4 Digit drive output.
18 D3 Digit drive output.
19 D2 Digit drive output.
20 D1 Digit drive output. Least Significant Digit (LSD)
21 BUSY Busy output.At the beginning of the signal-integration phase,BUSYgoesHighand

22 CLOCK IN Clock input. Conversion clock connection.
23 POLARITY Polarity output.A positive input is indicatedby a logic High output.The polarity output is

24 DGND Digitallogic referenceinput.
25 RUN/HOLD

26 STROBE
27 OVERRANGE Over range output. A logic High indicates that the analog input exceeds the full scale input

28 UNDERRANGE Underrangeoutput. A logic High indicatesthatthe analog input is less than 9% of the full

Symbol Description

- Reference capacitor input. Reference capacitornegative connection.

REF

+ Reference capacitor input. Reference capacitor positive connection.

REF

remainsHighuntilthefirstclockpulseafter the integratorzerocrossing.

valid at the beginning of the reference integratephaseandremains valid until determined
duringthenext conversion.

Run / Hold input. When at a logic High,conversions are performed continuously. A logic
Low holds the current data as long as the Low condition exists.

Strobe output. The STROBE output pulses low in the center of the digit drive outputs.

range.

scaleinputrange.

DS21478B-page 6



2002 Microchip TechnologyInc.

TC835

3.0 DETAILED DESCRIPTION

(All Pin Designations Refer to 28-Pin DIP)

3.1 Dual Slope Conversion Principles

The TC835 is a dual slope, integrating analog to digital
converter. An understanding of the dual slope conver­sion technique will aid in following the detailed TC835
operational theory.

The conventional dual slope converter measurement
cycle has two distinct phases:

1. Input signal i ntegration

2. Referencevoltage integration (de-integration)
Theinputsignalbeingconvertedisintegratedforafixed

timeperiod,witht ime beingmeasuredby countingclock
pulses.An opposite polarity constantreference voltage
is then integrated until the integrator output voltage
returnstozero.Thereference integrationtimeisdirectly
proportional to the input signal.

In a simple dual slope converter, a complete
conversion requires the integrator output to "ramp-up"
and "ramp-down."

A simple mathematical equation relates the input sig­nal, reference voltage and integration time:

EQUATION 3-1:

where:

1

R

INTCINT

V

REF

T

INT

T

DEINT

T

INT

VIN(T)DT =

∫

0

= Reference voltage
= Signal integration time (fixed)
= Reference voltage integration time

(variable).

V

REFTDEINT

R

INTCINT

FIGURE 3-1: BASIC DUAL SLOPE

CONVERTER

Analog Input

Signal

REF

Voltage

Output

Integrator

Fixed

Signal

Integrate

Time

Integrator

-

+

Switch

Drive

Polarity Control

Display

Variable
Reference
Integrate
Time

Phase
Control

V

IN

V

IN

≈ V

REF

≈ 1/2 V

Comparator

-

+

Control

Logic

REF

Clock

Counter

3.2 TC835 Operational Theory

The TC835 incorporates a system zero phase and
integrator output voltage zero phase to the normal two
phase dual slope measurement cycle. Reduced sys­tem errors, fewer calibration steps and a shorter over­range recovery time result.

The TC835 measurement cycle contains four phases:

1. System zero

2. Analog input signal integration

3. Referencevoltage integration

4. Integrator output zero
Internal analog gate status for each phase is shown in

Table 3-1.

For a constant VIN:

EQUATION 3-2:

VIN=

V

REFTDEINT

t

INT

3.2.1 SYSTEM ZERO

During this phase, errors due to buffer, integrator and
comparator offset voltages are compensated for by
charging C
ing error voltage. With a zero input voltage the

(auto zero capacitor) with a compensat-

AZ

integrator output wi ll remain at zero.

The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated, or averaged, to zero during the integration
periods. Integrating ADCs are immune to the large
conversion errors that plague successive approxima­tion converters in high noise environments (see
Figure3-1).



2002 Microchip TechnologyInc. DS21478B-page 7

The externalinputsignal is disconnectedfromtheinter­nal circuitry by opening the two SW

switches. The

I

internal input points connect to ANALOG COMMON.
The reference capacitor charges to the reference
voltage potential through SW

. A feedback loop,

R

closed around the integrator and comparator, charges
the C

capacitor with a voltage to compensate for

AZ

buffer amplifier, integrator and comparator offset
voltages (see Figure 3-2).

TC835

A

FIGURE 3-2: SYSTEM Z ERO PHASE

Analog

SWRI+

C

REF

Input Buffer

SW

1

+

-

SWIZSW

SW

Z

C

R

INT

INT

C

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To Digital
Section

+IN

REF

Analog
Common

–

SW

I

SWRI-

SW

R

IN

SW

Z

SWRI+SWRI-

SW

I

IN

3.2.2 ANALOG INP UT SIGNAL
INTEGRATION

The TC835 integrates the differential voltage between
the +INPUT and -INPUT pins. The differential voltage
mustbewithinthedeviceCommonmoderange(-1V
fromeithersupplyrail,typically). Theinputsignalpolarity
is determined at the end of this phase (see Figure 3-3).

FIGURE 3-3: INPUT SIGNAL

INTEGRATION PHASE

Analog

+IN

REF

nalog

Common

–

SW

I

SW

R

IN

SW

Z

SWRI+SWRI-

SW

I

IN

Input Buffer

+

SW

-

+SWRI-

RI

SW

SW

C

REF

IZ

SW

Z

SW

1

C

R

INT

INT

C

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To
Digital
Section

3.2.3 REFERENCE VOLTAGE
INTEGRATION

FIGURE 3-4: REFERENCE VOLTAGE

INTEGRATION CYCLE

Analog

SWRI+

-

C

REF

+SWRI-

SW

1

Input Buffer

+

-

SW

IZ

SW

Z

C

R

INT

INT

C

SW

SZ

Z

-

Comparator

+

+

-

Integrator

Switch Open
Switch Closed

To Digital
Section

+IN

REF

Analog
Common

–

SW

I

SW

RI

SW

R

IN

SW

Z

SW

RI

SW

I

IN

3.2.4 INTEGRATOR OUTPUT ZERO

This phase guarantees the integrator output is at 0V
when the system zero phase is entered and that the
true system offset voltages are compensated for. This
phase normally lasts 100 to 200 clock cycles. If an
overrange condition exists, the phase is extended to
6200 clock cycles ( see Figure 3-5).

FIGURE 3-5: INTEGRATOR OU TPUT

ZERO PHASE

Analog

Input Buffer

SWRI+SWRI-

C

REF

SW

1

SW

R

+

-

SW

INTCINT

C

SW

IZ

Z

SZ

Z

-

+

Integrator

Switch Open
Switch Closed

Comparator

+

-

To Digital
Section

+

REF

Analog
Common

–

SW

I

IN

SW

R

IN

SW

Z

SWRI+SWRI-

SW

I

IN

The previously charged reference capacitor is con­nected with the proper polarity to ramp the integrator
outputbacktozero(see Figure 3-4). The digitalreading
displayed is:

Reading = 10,000

[Differential Input]

V

REF

TABLE 3-1: INTERNAL ANALOG GATE STATUS

Conversion Cycle Phase SWISWRI+SWRI-SWZSW

System Zero Closed Closed Closed Figure3-2
InputSignal Integration Closed Figure 3-3
Reference Voltage Integration Closed* Closed Figure3-4
Integrator OutputZero Closed Closed Figure3-5

*Note: Assumes a positive polarity input signal. SW

DS21478B-page 8

would be closed for a negative input signal.

RI

SW

R

SW

1



2002 Microchip TechnologyInc.

Reference Figures

IZ

TC835

4.0 ANALOG SECTION
FUNCTIONAL DESCRIPTION

(In Reference to the 28-Pin Plastic Package)

4.1 Differential Inputs
(+INPUT (Pin 10) and
–INPUT (Pin 9))

The TC835 operates with differential voltages within
the input amplifier Common mode range. The input
amplifier Common mode range extends from 0.5V
below the positive supply to 1V above the negative
supply. Within this Common mode voltage range, an
86dB Common mode rejection ratio is typical.

The integrator output also follows the Common mode
voltage. The integrator output must not be allowed to
saturate. An example of a worst case condition would
be when a large positiveCommon mode voltagewith a
near full scale negative differential input voltage is
applied. The negative input signal drives the integrator
positive when most of its swing has been used up by
the positive Common mode voltage. For these critical
applications, the integrator swing can be reduced to
less than the recommended 4V full scale swing, with
the effect of reduced accuracy. The integrator output
can swing within 0.3V of either supply without loss of
linearity.

4.3 Reference Voltage Input
(REF IN (Pin 2))

The REF IN input must be a positive voltage with
respect to ANALOG COMMON. A reference voltage
circuit is shown in Figure 4-1.

FIGURE 4-1: USING AN EXTERNAL

REFERENCE

V+

V+

TC835

REF

IN

ANALOG

COMMON

10k

10k

MCP1525

2.5 V

REF

1µF

Analog Ground

4.2 Analog Common Input (Pin 3)

ANALOG COMMON is us ed as the -INPUT return dur­ing auto zero and de-integrate. If -INPUT is different
from ANALOG COMMON, a Common mode voltage
exists in the system. This signal is rejected by the
excellent CMRR of the converter.In most applications,

-INPUT will be set at a fixed, known voltage (power
supply common, for instance). In this application,
ANALOG COMMON should be tied to the same point,
thus removing the common-mode voltage from the
converter. The reference voltage is referenced to
ANALOG COMMON.



2002 Microchip TechnologyInc. DS21478B-page 9

TC835

5.0 DIGITAL SECTION
FUNCTIONAL DESCRIPTION

The major digital subsystems within the TC835 are
illustrated in Figure 5-1, with timing relationships
shown in Figure 5-2. The multiplexed BCD output data
can be displayed on LCD or LED. The digital section is
best described through a discussion of the control sig­nals and data outputs.

FIGURE 5-1: DIGITAL SE CTION FUNCTIONAL DIAGRAM

Polarity

From

Analog

Section

Polarity

FF

Zero
Cross
Detect

24 22 25 27 28 26 21

DGND ClockInRUN/

D5 D4 D3 D2 D1

MSB Digit Drive Signal LSB

Multiplexer

Latch Latch Latch Latch Latch

Counters

Control Logic

HOLD

Overrange STROBE BusyUnderrange

Data

Output

13 B1
14 B2

15 B4
16 B8

DS21478B-page 10



2002 Microchip TechnologyInc.

TC835

FIGURE 5-2: TIMING DIAGRAMS FO R

OUTPUTS

Integrator

Output

Busy

Overrange when

Applicable

Underrange when

Applicable

Digit Scan

STROBE

Digit Scan

for Overrange

Signal

Integrate

System

10,000

Zero

Counts

10,001

(Fixed)

Counts

Full Measurement Cycle

40,002 Counts

Expanded Scale Below

100

Counts

Auto Zero

*

D5

D4

D3

D2

D1

Reference

Integrate

20,001

Counts (Max)

D5

D4

D3
D2

D1

First D5 of System Zero and

*

Reference Integrate One Count
Longer

*

Reference
Integrate

Signal

Integrate

5.1 RUN/HOLD Input (Pin 25)

When left open, this pin assumes a logic "1" level.With
a RUN/HOLD
continuously,withanew measurement cycle beginning
every 40,002 clock pulses.

When RUN/HOLD
ment cyclein progresswillbecompleted,anddataheld
and displayed as long as the logic "0" condition exists.

A positive pulse (>300nsec) at RUN/HOLD
new measurement cycle. The measurement cycle in
progress when RUN/HOLD
"0" state must be completed before t he positive pulse
can be recognized as a single conversion run
command.

The new measurement cycle begins with a 10,001­count auto zero phase. At the end of this phase, the
busy signal goes high.

= 1, the TC835 performs conversions

changestoa logic "0," the measure-

initiates a

initially assumed the logic

5.2 STROBE Output (Pin 26)

During the measurement cycle, the STROBE control
line is pulsed low five times. The five low pulses occur
in the center of the digit drive signals (D

1,D2,D3,D5

(see Figure 5-3).
D

(MSD) goes high for 201 counts when the measure-

5

ment cycles end. In the center of the D

pulse, 101

5

clock pulses after the end of the measurement cycle,
the first STROBE
the D

digit strobe, D4goes high for 200 clock pulses.

5

The STROBE
high. This continues through the D

occurs for one-half clock pulse. After

goes low 100 clock pulses after D4goes

digit drive pulse.

1

The digit drive signals will continue to permit display
scanning.STROBE

pulsesarenotrepeateduntilanew
measurement is completed. The digit drive signals will
not continue if the previous signal resulted in an
overrange condition.

TheactivelowSTROBE

pulses aid BCD data transfer

to UARTs, processors and external latches.

FIGURE 5-3: STROBE SIGNAL L OW

FIVE TIMES PER
CONVERSION

TC835
Outputs

Busy

B1–B8

STROBE

D5

D4

D3

D2

D1

*Delay between Busy going Low and First STROBE pulse is
dependent on Analog Input.

End of Conversion

*

D5 (MSD)

Data

200

Counts

201

Counts

D4

Data

200

Counts

D3

DataD2Data

200

Counts

200

Counts

D1 (LSD)

DataD5Data

Note Absence of
STROBE

Counts

200

Counts

200

5.3 BUSY Output

At the beginning of the signal integration phase, BUSY
goes hi gh and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to the
logic "0" state after the measurement cycle ends in an
overrange condition. The internal display latches are
loaded during the first clock pulse after BUSY and are
latched at the clock pulse end. The BUSY signal does
not go high at the beginningof the measurement cycle,
which starts with the auto zero cycle.

)



2002 Microchip TechnologyInc. DS21478B-page 11

TC835

5.4 OVERRANGE Output

If the input signal causes the reference voltageintegra­tion time to exceed 20,000 clock pulses, the
OVERRANGE output i s set to a logic "1." The over­range output register is set when BUSY goes l ow, and
is reset at the beginning of the next reference
integration phase.

5.5 UNDERRANGE Output

If the output count is 9% of full scale or less (-1800
counts), the underrange register bit is set at the end of
BUSY. The bit is set low at the next signal integration
phase.

5.6 POLARITY Output

A positive input is registered by a logic "1" polarity
signal. The POLARITY bit is valid at the beginning of
ReferenceIntegrateandremainsvaliduntildetermined
during the next conversion.

The POLARITY bit is valid even for a zero reading.
Signals less than the converter's LSB will have the sig­nal polarity determined correctly. This is useful in null
applications.

5.7 Digit Drive Outputs

Digit drive signals are positive going signals. The scan
sequence is D
pulseswide,exceptD

Allfive digitsarescannedcontinuously,unless an over­range condition occurs. In an overrange condition, all
digit drives are held low from the final STROBE
until the beginning of the next reference integrate
phase. The scanning sequence is then repeated. This
provides a blinking v isual display indication.

to D1. All positive pulses are 200 clock

5

, which is 201 clock pulses wide.

5

pulse

6.0 TYPICAL APPLICATIONS

6.1 Component Value Selection

The integrating resistor is determined by the full-scale
input voltage and the output current of the buffer used
to charge the integrator capacitor. Both the buffer
amplifier and the integrator have a class A output
stage, with 100µA of quiescent current. A 20µAdrive
current gives negligible linearity errors. Values of 5µA
to 40µA gi ve good results. The exact value of an
integrating resistor for a 20µA current is easily calcu­lated.

EQUATION 6-1:

Full scale voltage

=

R

INT

6.1.1 INTEGRATING CAPACITOR

The productof integratingresistor and capacitorshould
be selected to give the maximum voltage swing that
ensures the tolerancebuildupwill not s aturate the inte­grator swing (approximately 0.3V from either supply).
For ±5Vsupplies and ANALOG COMMON tied to sup­ply ground, a ±3.5V to ±4Vfull-scaleintegrator swing is
adequate. A 0.10µFto0.47µF is recommended. In
general, the value of C

EQUATION 6-2:

C

INT

[10,000 x clock period] x I

=

Integrator output voltage swing
(10,000) (clock period) (20µA)

=

Integrator output voltage swing

20µA

is given by:

INT

INT

5.8 BCD Data Outputs

The binary coded decimal (BCD) bits B8,B4,B2,B1are
positive-true logicsignals. The data bits become active
simultaneously with the digit drive signals. In an
overrangecondition, all data bitsareata logic "0" state.

DS21478B-page 12

A very importantcharacteristicof the integratingcapac­itor is t hat it has low dielectric absorption to pr event
rollover or ratiometric errors. A good test for dielectric
absorption would be to use the capacitor with the input
tied to the reference. This ratiometric condition should
read half scale 0.9999, with any deviationprobablydue
to dielectric absorption. Polypropylene capacitors give
undetectable errors at reasonable cost. Polystyrene
and polycarbonate capacitorsmay also be used in less
critical applications.

6.1.2 AUTO ZERO AND REFERENCE
CAPACITORS

The size of the auto zero capacitorhas some influence
on the noise of the system. A large capacitor reduces
the noise. The reference capacitor should be large
enough such that stray capacitance to ground from i ts
nodes is negligible.

The dielectricabsorption of the reference capacitorand
auto zero capacitor are only important at power-on or
when the circuit i s recovering from an overload.



2002 Microchip TechnologyInc.

TC835

Smaller or cheaper capacitors can be used if accurate
readings are not required for the first few seconds of
recovery.

6.1.3 REFERENCE VOLTAGE

he analog input r equired to generate a full scale out-

T

put is V

IN

=2V

REF

.

The stabilityofthereferencevoltageisa major factorin
the overall absolute accuracy of the converter. For this
reason,itisrecommendedthatahigh-quality reference
be used w here high-accuracy absolute measurements
are being made.

6.2 Conversion Timing

6.2.1 LINE FREQUENCY REJECTION

A signal integrationperiod at a multipleof the 60Hz line
frequency will maximize 60Hz "line noise" rejection. A
200kHz clock frequency will reject 60Hz and 400Hz
noise. This corresponds to five readings per second
(see Table 6-1 and Table 6-2).

TABLE 6-1: CONVERSION RATE VS.

CLOCK FREQUENCY

Oscillator Frequency

(kHz)

100 2.5
120 3
200 5
300 7.5
400 10
800 20

1200 30

TABLE 6-2: LINE FREQUENCY VS.

CLOCK FREQUENCY

Oscillator Frequency

(kHz)

50.000 • • •

53.333 — — •

66.667 • — •

80.000 — — •

83.333 — • •

100.000 • • •

125.000 — • •

133.333 — — •

166.667 — — •

200.000 • — •

250.000

Conversion Rate

(Conv./Sec.)

Line Frequency Rejection

60Hz 50Hz 400Hz

The c onversion rate is easily calculated:

EQUATION 6-3:

Reading 1/sec =

Clock Frequency (Hz)

4000

6.3 Power Supplies and Grounds

6.3.1 POWER SUPPLIES

The TC835 is designed to work from ±5V supplies. For
single +5V operation, a TC7660 can provide a
–5V supply.

6.3.2 GROUNDING

Systems should use separate digital and analog
ground systems to avoid loss of accuracy.

6.4 High-Speed Operation

The maximum conversion rate of most dual-slope A/D
converters i s limited by the frequency response of the
comparator. The comparator in this circuit follows the
integrator ramp with a 3µsec delay, and at a clock fre­quency of 200kHz (5µsec period), half of the first refer­ence integrate clock period is lost in delay. This means
that the meter reading will change from 0 to 1 with a
50µVinput, 1 to 2 with 150µV,2to3at250µV, etc. This
transition at midpoint is considered desirable by most
users, however, if the clock frequency is increased
appreciablyabove200kHz,the instrumentwill flash "1"
on noise peaks even when the input is shorted.

For many dedicated applicationswheretheinput signal
is always of one polarity, the delay of the comparator
need not be a limitation. Since t he nonlinearity and
noise do not increase substantially with f requency,
clock rates of up to ~1MHz may be used. For a fixed
clock frequency, the extra count or counts caused by
comparator delay will be a constant and can be
subtracted out digitally.

The clock frequency may be extended above 200kHz
without this error, however, by using a low-value resis­tor in series with t he integrating capacitor. The effectof
theresistoristointroduce a small pedestalvoltage onto
the integrator output at the beginning of the reference
integrate phase. By careful selection of the ratio
between this resistor and the integrating resistor (a few
tens of ohms in the recommended circuit), the compar­ator delay can be compensated and the maximum
clock frequency extended by approximately a factor of

3. At higher frequencies, ringing and second-order
breaks will cause significant nonlinearities in the first
few counts of the instrument.

The minimum clock frequency is established by leak­age on the auto zero and reference capacitors. With
most devices, measurement cycles as long as 10 sec­onds give no measurable leakage error.



2002 Microchip TechnologyInc. DS21478B-page 13

TC835

The clock used should be free from significant phase or
frequency jitter. Several suitable low-cost oscillators
are shown in Section 6.0, Typical Applications. The
multiplexed output means that if the display takes sig­nificant current from the logic supply, the cl ock should
have good PSRR.

6.5 Zero Crossing Flip-Flop

The flip flop interrogates the data once every clock
pulse after the transients of the previous clock pulse
and half-clock pulse have died down. False zero cross­ings caused by clock pulses are not recognized. Of

course, the flip flop delays the true zero crossing by up
to one count in every instance.If a correction were not
made, the display would always be one count too high.

Therefore, the counter is disabled for one clock pulse
at the beginning of the reference integrate (de-inte­grate) phase. This one-count delay compensates for
the delay of the zero crossing flip flop and allows the
correct number to be latched into the display.Similarly,
a one-count delay at the beginning of auto zero gives
an overload display of 0000 instead of 0001. No delay
occurs during signal integrate, so that t rue ratiometric
readings result.

FIGURE 6-1: 4-1/2 DIGIT ADC MULTIPLEXED COMMON ANODE LED DISP LAY

20 19 18 17 12

D1 D2 D3 D4 D5

4

0.33µF

200kHz

+

Analog

Input

–

100kΩ

100kΩ

1µF

1µF

5

6

22

10

9

3

–5V

INT OUT

AZ IN

BUFF
OUT

TC835

F

IN

+INPUT

–INPUT

ANALOG
COMMON

REF

V–

IN

21

100kΩ

POL

C

REF

C

REF

MCP1525

1µF

B8
B4

B2
B1

V+

+

11

4.7kΩ

23

7

-

1µF

8

16
15
14
13

V+

Blank MSD On Zero

bc

6

D

2

C

1

B

7

A

7777

X7

9–15

5

RBI

DM7447A

16

+5V

+5V

DS21478B-page 14



2002 Microchip TechnologyInc.

TC835

V

FIGURE 6-2: RC OSCILLATOR CIRCUIT FIGURE 6-3: COMPARATOR CLO CK

CIRCUITS

R

2

C

R

1

F

O

16kΩ

+5V

1kΩ

56kΩ

Gates are 74C04

1. fO=
2C(0.41R

1

+0.7R1)

P

a. If R1=R2=R1,F≅ 0.55/RC
b. If R

>> R1,f≅ 0.45/R1C

2

c. If R

<< R1,f≅ 0.72/R1C

2

,R

0.22µF

R1R

=

P

2

R1+R

2

16kΩ

R2

100kΩ

2

3

+5V

+

LM311

-

4

8

1

R4

2kΩ

7

30kΩ

390pF

2. Examples:
a. f = 120kHz, C = 420pF

1=R2

≈ 10.9kΩ

R

b. f = 120kHz, C = 420pF, R

R

= 8.93k Ω

1

c. f = 120kHz, C = 220pF, R

= 27.3kΩ

R

1

= 50kΩ

2

=5kΩ

2

R2

100kΩ

C1

0.1µF

2

3

+

LM311

-

1

C2

6

10pF

7

4

R3
50kΩ

FIGURE 6-4: 4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON CATHODE LED DISPLAY

150Ω

+5V

150Ω

10

11

12

13

14

15

16

17

18

MC14513

9

8

7

6

5

4

3

2

1

+5V

MCP1525

SIG

IN

1µF

0.33µF

100

kΩ

+

–

100

Analog

GND

0.1
µF

kΩ

1µF

100 kΩ

1µF

+5V

SET V

–5V

1

2

3

4

5

6

7

8

9

10

11

12

13
14

= 1V

REF

V-

TC835

REF IN

ANALOG
GND

INT
OUT

AZ IN
BUFF

OUT

+

C

REF

-

C

REF

–INPUT

+INPUT

V+

D5 (MSD)

B1 (LSB)
B2

UR

OR

STROBE

RUN/HOLD

DGND

POLARITY

CLK IN

BUSY

(LSD) D1

D2

D3

D4

(MSB) B8

B4

28

27

26

47
kΩ

25

24

23

22

21

20

19

18

17

16
15

V

V

OUT

OUT

+5

F

= 200kHz

OSC



2002 Microchip TechnologyInc. DS21478B-page 15

TC835

z

FIGURE 6-5: TEST CIRCUIT

V

REF

0.47

5V

µF

REF

IN

= 1V

100kΩ

100 kΩ

100
kΩ

0.1µF

SET V

ANALOG GND

Signal
Input

+

–5V

1µF

1µF

1

2

3

4

5
6

7
8
9

10
11
12

13

14

TC835

V-

UNDERRANGE

REF IN
ANALOG

COMMON

INT OUT

AZ IN
BUFF OUT

-

C

REF

C

+

REF

–INPUT

+INPUT
V+
D5 (MSD)

B1 (LSB)

B2

OVERRANGE

STROBE

RUN/HOLD

DIGTAL GND

POLARITY

CLOCK IN

BUSY

(LSD) D1

(MSB) B8

D2

D3

D4

B4

28

27

26

25

24

23

Clock

22

Input
120kH

21

20

19

18

17

16

15

DS21478B-page 16



2002 Microchip TechnologyInc.

7.0 PACKAGING INFORMATION

7.1 Package Marking Information

Package marking data not available at this time.

7.2 Taping Forms

Component Taping Orientation for 64-Pin PQFP Devices

User Direction of Feed

Standard Reel Component Orientation
for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

64-Pin PQFP 32 mm 24 mm 250 13 in

NOTE: Drawing does not represent total number of pins.

TC835

PIN 1

W

P

Component Taping Orientation for 44-Pin PQFP Devices

User Direction of Feed

PIN 1

W

P
Standard Reel Component Orientation
for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

44-Pin PQFP 24 mm 16 mm 500 13 in

NOTE: Drawing does not represent total number of pins.



2002 Microchip TechnologyInc. DS21478B-page 17

TC835

)

7.3 Package Dimensions

28-Pin PDIP (Wide)

.200 (5.08)
.140 (3.56)

.150 (3.81)
.115 (2.92)

.110 (2.79)
.090 (2.29)

44-Pin PQFP

1.465 (37.21)

1.435 (36.45)

.070 (1.78)
.045 (1.14)

.022 (0.56)
.015 (0.38)

PIN 1

.555 (14.10)
.530 (13.46)

.040 (1.02)
.020 (0.51)

.015 (0.38)
.008 (0.20)

.610 (15.49)
.590 (14.99)

.700 (17.78)
.610 (15.50)

Dimensions: inches (mm)

7

˚

MAX.

3

˚

MIN.

PIN 1

.018 (0.45)
.012 (0.30)

.031 (0.80) TYP.

.398 (10.10)

.390 (9.90)

.557 (14.15)
.537 (13.65)

.398 (10.10)

.390 (9.90)

.557 (14.15)
.537 (13.65)

.009 (0.23)
.005 (0.13)

.096 (2.45) MAX.

.041 (1.03)
.026 (0.65)

.010 (0.25) TYP.

.083 (2.10)
.075 (1.90)

Dimensions: inches (mm

DS21478B-page 18



2002 Microchip TechnologyInc.

7.3 Package Dimensions (Continued)

)

64-Pin PQFP

˚

MAX.

7

TC835

.018 (0.45)
.012 (0.30)

.031 (0.80) TYP.

PIN 1

.555 (14.10)
.547 (13.90)

.687 (17.45)
.667 (16.95)

.555 (14.10)
.547 (13.90)

.687 (17.45)
.667 (16.95)

.009 (0.23)
.005 (0.13)

.130 (3.30) MAX.

Dimensions: inches (mm

.041 (1.03)
.031 (0.78)

.010 (0.25) TYP.

.120 (3.05)
.100 (2.55)



2002 Microchip TechnologyInc. DS21478B-page 19

TC835

NOTES:

DS21478B-page 20



2002 Microchip TechnologyInc.

TC835

SALES AND SUPPORT

Data Sheets

Products supportedby a preliminaryData Sheet may have an errata sheet describingminor operationaldifferences and recom­mendedworkarounds.To determine if an erratasheetexists for a particulardevice, please contactone of the following:

1. Your local Microchip sales office

2. The MicrochipCorporate Literature Center U.S. FAX:[phone]

3. The Microchip Worldwide Site (www.microchip.com)
Pleasespecify which device, revision of silicon and Data Sheet (includeLiterature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most currentinformationon our products.

 2002 Microchip Technology Inc. DS21478B-page21

TC835

NOTES:

DS21478B-page 22  2002 Microchip Technology Inc.

TC835

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information,or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com­ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con­veyed, implicitly or otherwise, under any intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,
K

EELOQ,microID,MPLAB,PIC,PICmicro,PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

SolutionsCompany areregiste red trademarksof MicrochipTech­nologyIncorp or ated in the U.S.A. and other countries .

dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and TotalEndurancearetrademarksofMicrochipTechnology
Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip TechnologyIncorporated in t he U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its

®

PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systemsisISO 9001certified.



2002 Microchip TechnologyInc. DS21478B-page 23

8-bit MCUs, KEELOQ®code hopping

WORLDWIDE SALES AND SERVICE

AMERICAS

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04/20/02

DS21478B-page 24

*DS21478B*



2002 Microchip Technology Inc.