■Easy to Use – Requires Only 2 External Non-Critical
Passive Components
■Improved Direct Replacement for Industry Stan-
dard ICL7660 and Other Second Source Devices
APPLICATIONS
■Simple Conversion of +5V to ±5V Supplies
■Voltage Multiplication V
■Negative Supplies for Data Acquisition Systems
and Instrumentation
■RS232 Power Supplies
■Supply Splitter, V
OUT
PIN CONFIGURATION (DIP AND SOIC)
BOOST
CAP
GND
CAP
1
+
2
3
–
4
TC7662BCPA
TC7662BEPA
+
8
V
7
OSC
LOW
6
VOLTAGE (LV)
V
5
OUT
OUT
= ±VS/2
BOOST
CAP
GND
CAP
= ±nV
1
+
2
TC7662BCOA
3
TC7662BEOA
–
4
IN
+
8
V
7
OSC
LOW
6
VOLTAGE (LV)
V
5
OUT
GENERAL DESCRIPTION
The TC7662B is a pin-compatible upgrade to the Industry standard TC7660 charge pump voltage converter. It
converts a +1.5V to +15V input to a corresponding – 1.5 to
– 15V output using only two low-cost capacitors, eliminating
inductors and their associated cost, size and EMI.
The on-board oscillator operates at a nominal frequency of 10kHz. Frequency is increased to 35kHz when
pin 1 is connected to V+, allowing the use of smaller external
capacitors. Operation below 10kHz (for lower supply current
applications) is also possible by connecting an external
capacitor from OSC to ground (with pin 1 open).
The TC7662B is available in both 8-pin DIP and 8-pin
small outline (SO) packages in commercial and extended
temperature ranges.
ORDERING INFORMATION
Temperature
Part No.PackageRange
TC7662BCOA8-Pin SOIC0°C to +70°C
TC7662BCPA8-Pin Plastic DIP0°C to +70°C
TC7662BEOA8-Pin SOIC– 40°C to +85°C
TC7662BEPA8-Pin Plastic DIP– 40°C to +85°C
SO ..................................................................470mW
ELECTRICAL CHARACTERISTICS: V
+
= 5V, TA = +25°C, OSC = Free running, Test Circuit Figure 2, Unless
* Static-sensitive device. Unused devices must be stored in conductive
material. Protect devices from static discharge and static fields. Stresses
above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those
indicated in the operation sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Otherwise Specified.
SymbolParameterTest ConditionsMinTypMaxUnit
+
I
+
I
+
V
H
+
V
L
R
OUT
f
OSC
P
Eff
V
EffVoltage Conversion EfficiencyRL = ∞9999.9—%
OUT
Z
OSC
Supply Current (Note 3)RL = ∞, +25°C—80160µA
(Boost pin OPEN OR GND)0°C ≤ TA ≤ +70°C——180µA
Supply Current0°C ≤ TA ≤ +70°C——300µA
(Boost pin = V+)– 40°C ≤ T
≤ +85°C350
A
– 55°C ≤ TA ≤ +125°C400
Supply Voltage Range, HighRL = 10 kΩ, LV Open, T
≤ TA ≤ T
MIN
MAX
3.0—15V
(Note 4)
Supply Voltage Range, LowRL = 10 kΩ, LV to GND, T
Output Source ResistanceI
= 20mA, 0°C ≤ TA ≤ +70°C—65100Ω
OUT
I
= 20mA, – 40°C ≤ TA ≤ +85°C——120Ω
OUT
I
= 20mA, – 55°C ≤ TA ≤ +125°C——150Ω
OUT
I
= 3mA, V+ = 2V, LV to GND ,——250Ω
OUT
0°C ≤ T
I
OUT
– 40°C ≤ T
I
OUT
≤ +70°C
A
= 3mA, V+ = 2V, LV to GND ,——300Ω
≤ +85°C
A
= 3mA, V+ = 2V, LV to GND ,——400Ω
≤ TA ≤ T
MIN
MAX
1.5—3.5V
– 55°C ≤ TA ≤ +125°C
Oscillator FrequencyC
= 0,Pin 1 Open or GND510—kHz
OSC
Pin 1 = V
+
35
Power EfficiencyRL = 5kΩ9696—%
T
≤ TA ≤ T
MIN
MAX
9597
Oscillator ImpedanceV+ = 2V—1—MΩ
V+ = 5V—100—kΩ
NOTES:
1. Connecting any terminal to voltages greater than V+ or less than GND may cause destructive latch-up. It is recommended that no inputs from
sources operating from external supplies be applied prior to “power up” of the TC7662B.
2. Derate linearly above 50°C by 5.5 mW/°C.
3. In the test circuit, there is no external capacitor applied to pin 7. However, when the device is plugged into a test socket, there is usually a very
small but finite stray capacitance present, of the order of 5pF.
4. The TC7662B can operate without an external diode over the full temperature and voltage range. This device will function in existing designs which
incorporate an external diode with no degradation in overall circuit performance.
The TC7662B contains all the necessary circuitry to
complete a negative voltage converter, with the exception of
two external capacitors which may be inexpensive 1µF
polarized electrolytic types. The mode of operation of the
device may be best understood by considering Figure 2,
which shows an idealized negative voltage converter. Capacitor C1 is charged to a voltage V+ for the half cycle when
switches S1 and S3 are closed. (Note: Switches S2 and S
are open during this half cycle.) During the second half cycle
of operation, switches S2 and S4 are closed, with S1 and S
open, thereby shifting capacitor C1 negatively by V+ volts.
Charge is then transferred from C1 to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and no
load on C2. The TC7662B approaches this ideal situation
more closely than existing non-mechanical circuits.
In the TC7662B, the four switches of Figure 2 are MOS
power switches; S1 is a P-channel device and S2, S3 and S
are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of
S3 and S4 must always remain reverse biased with respect
to their sources, but not so much as to degrade their “ON”
resistances. In addition, at circuit start up, and under output
short circuit conditions (V
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.
The problem is eliminated in the TC7662B by a logic
network which senses the output voltage (V
with the level translators, and switches the substrates of S
and S4 to the correct level to maintain necessary reverse
bias.
The voltage regulator portion of the TC7662B is an
integral part of the anti-latchup circuitry; however, its inherent voltage drop can degrade operation at low voltages.
Therefore, to improve low voltage operation, the “LV” pin
should be connected to GND, disabling the regulator. For
supply voltages greater than 3.5 volts, the LV terminal must
be left open to insure latchup proof operation and prevent
device damage.
+
V
1
2
+
C
10 µF
1
TC7662B
3
4
= V+), the output voltage must
OUT
) together
OUT
I
I
R
S
L
L
V
(+5V)
8
7
6
5
+
THEORETICAL POWER EFFICIENCY
CONSIDERATIONS
In theory, a voltage converter can approach 100%
efficiency if certain conditions are met:
A. The drive circuitry consumes minimal power.
B. The output switches have extremely low ON resistance
and virtually no offset.
4
C. The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.
3
The TC7662B approaches these conditions for nega-
tive voltage conversion if large values of C1 and C2 are used.
Energy is lost only in the transfer of charge between
capacitors if a change in voltage occurs. The energy lost
is defined by:
2
4
E = 1/2 C1 (V
1
– V
2
)
2
where V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C1 and C2 are relatively
high at the pump frequency (refer to Figure 2) compared to
the value of RL, there will be a substantial difference in
voltages V1 and V2. Therefore, it is desirable not only to
make C2 as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C1 in order to achieve maximum efficiency of operation.
Dos and Don’ts
3
1. Do not exceed maximum supply voltages.
2. Do not connect the LV terminal to GND for supply
voltages greater than 3.5 volts.
3. Do not short circuit the output to V+ supply for voltages
above 5.5 volts for extended periods; however,
transient conditions including start-up are okay.
4. When using polarized capacitors in the inverting mode,
the + terminal of C1 must be connected to pin 2 of the
TC7662B and the – terminal of C2 must be connected
to GND.
5. If the voltage supply driving the TC7662B has a large
source impedance (25-30 ohms), then a 2.2µF capacitor from pin 8 to ground may be required to limit the
rate of rise of the input voltage to less than 2V/µsec.
TYPICAL APPLICATIONS
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
TC7662B for generation of negative supply voltages. Figure
3 shows typical connections to provide a negative supply
where a positive supply of +1.5V to +15V is available. Keep
in mind that pin 6 (LV) is tied to the supply negative (GND)
for supply voltages below 3.5 volts.
V+
1
10 µF
Figure 3. Simple Negative Converter and its Output Equivalent
2
+
–
TC7662B
3
4
a.b.
The output characteristics of the circuit in Figure 3 can
be approximated by an ideal voltage source in series with a
resistance as shown in Figure 3b. The voltage source has a
value of–(V+). The output impedance (RO) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 2), the switching frequency, the value of C1 and C2,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for RO is:
8
7
6
5
10 µF
R
O
V
V
= –V+
–
+
OUT
–
V+
+
OUT
voltage and temperature (See the Output Source Resistance graphs), typically 23Ω at +25°C and 5V. Careful
selection of C1 and C2 will reduce the remaining terms,
minimizing the output impedance. High value capacitors will
reduce the 1/(f
x C1) component, and low ESR capaci-
PUMP
tors will lower the ESR term. Increasing the oscillator frequency will reduce the 1/(f
x C1) term, but may have the
PUMP
side effect of a net increase in output impedance when C1 >
10µF and there is not enough time to fully charge the
capacitors every cycle. In a typical application when f
OSC
=
10kHz and C = C1 = C2 = 10µF:
RO ≅ 2 x 23 + + 4 x ESRC1 + ESR
(5 x 103 x 10 x 10-6)
1
C2
RO ≅ (46 + 20 + 5 x ESRC) Ω
Since the ESRs of the capacitors are reflected in the
output impedance multiplied by a factor of 5, a high value
could potentially swamp out a low 1/(f
x C1) term,
PUMP
rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have
ESRs as high as 10Ω.
Output Ripple
ESR also affects the ripple voltage seen at the output.
The total ripple is determined by 2 voltages, A and B, as
shown in Figure 4. Segment A is the voltage drop across the
ESR of C2 at the instant it goes from being charged by C
(current flowing into C2) to being discharged through the
load (current flowing out of C2). The magnitude of this
current change is 2 x I
ESRC2 volts. Segment B is the voltage change across C
during time t2, the half of the cycle when C2 supplies current
to the load. The drop at B is I
peak ripple voltage is the sum of these voltage drops:
V
≅( + ESR
RIPPLE
2 x f
, hence the total drop is 2 x I
OUT
x t2/C2 volts. The peak-to-
OUT
1
x I
PUMP
x C
2
C2
OUT
OUT
)
1
x
2
RO ≅ 2(R
(f
= , R
PUMP
Combining the four R
RO ≅ 2 x RSW + + 4 x ESRC1 + ESRC2Ω
+ R
SW1
ESRC1) + + ESR
f
OSC
2
+ ESRC1) + 2(R
SW3
SW2
1
f
x C
PUMP
SWX
terms as RSW, we see that:
SWX
1
= MOSFET switch resistance)
1
f
x C
PUMP
1
+ R
C2
RSW, the total switch resistance, is a function of supply
Any number of TC7662B voltage converters may be
paralleled to reduce output resistance (Figure 5). The reservoir capacitor, C2, serves all devices, while each device
requires its own pump capacitor, C1. The resultant output
resistance would be approximately:
R
(of TC7662B)
R
=
OUT
1
2
C
1
3
4
TC7662B
"1"
Figure 5. Paralleling Devices
OUT
n (number of devices)
+
V
8
7
6
5
C
1
1
2
3
4
TC7662B
"n"
8
7
6
5
R
L
C
2
+
Cascading Devices
The TC7662B may be cascaded as shown to produce
larger negative multiplication of the initial supply voltage.
However, due to the finite efficiency of each device, the
practical limit is 10 devices for light loads. The output voltage
is defined by:
V
= – n(VIN)
OUT
Changing the TC7662B Oscillator Frequency
It may be desirable in some applications (due to noise or
other considerations) to increase the oscillator frequency.
This is achieved by one of several methods described
below:
By connecting the BOOSTPin (Pin 1) to V+, the oscillator
charge and discharge current is increased and, hence the
oscillator frequency is increased by approximately 3-1/2
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface mount applications where capacitor size and cost are critical. Smaller
capacitors, e.g., 0.1µF, can be used in conjunction with the
Boost Pin in order to achieve similar output currents compared to the device free running with C1 = C2 = 1µF or 10µF.
(Refer to graph of Output Source Resistance as a Function
of Oscillator Frequency).
Increasing the oscillator frequency can also be achieved
by overdriving the oscillator from an external clock as shown
in Figure 7. In order to prevent device latchup, a 1kΩ resistor
must be used in series with the clock output. In a situation
where the designer has generated the external clock frequency using TTL logic, the addition of a 10kΩ pullup
resistor to V+ supply is required. Note that the pump frequency with external clocking, as with internal clocking, will
be 1/2 of the clock frequency. Output transitions occur on the
positive-going edge of the clock.
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual TC7662B
R
values.
OUT
+
V
1
2
+
TC7662B
10µF
3
4
*V
= –nV
OUT
Figure 6. Cascading Devices for Increased Output Voltage
8
7
6
5
"1"
+
10µF
+
10µF
1
2
3
4
TC7662B
"n"
8
7
6
5
+
10µF
V
OUT
Figure 7. External Clocking
It is also possible to increase the conversion efficiency
of the TC7662B at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 8. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (C1) and reservoir (C2) capacitors; this is overcome by
increasing the values of C1 and C2 by the same factor that
the frequency has been reduced. For example, the addition
of a 100pF capacitor between pin 7 (Osc) and V+ will lower
the oscillator frequency to 1kHz from its nominal frequency
of 10kHz (multiple of 10), and thereby necessitate a corresponding increase in the value of C1 and C2 (from 10µF to
100µF).
The TC7662B may be employed to achieve positive
voltage doubling using the circuit shown in Figure 9. In this
application, the pump inverter switches of the TC7662B are
used to charge C1 to a voltage level of V+ – VF (where V+ is
the supply voltage and VF is the forward voltage on C1 plus
the supply voltage (V+) applied through diode D2 to capacitor
C2). The voltage thus created on C2 becomes (2 V+) – (2 VF),
or twice the supply voltage minus the combined forward
voltage drops of diodes D1 and D2.
The source impedance of the output (V
on the output current, but for V+ = 5V and an output current
of 10 mA, it will be approximately 60Ω.
8
7
6
5
C
2
+
) will depend
OUT
C
V
OSC
OUT
CHARGE PUMP DC-TO-DC
VOLTAGE CONVERTER
+
V
1
2
TC7662B
3
4
+
C
1
Figure 10. Combined Negative Converter and Positive Doubler
8
7
6
5
+
C
2
D
D
Voltage Splitting
The bidirectional characteristics can also be used to
split a higher supply in half, as shown in Figure 11. The
combined load will be evenly shared between the two sides
and a high value resistor to the LV pin ensures start-up.
Because the switches share the load in parallel, the output
impedance is much lower than in the standard circuits, and
higher currents can be drawn from the device. By using this
circuit, and then the circuit of Figure 6, +15V can be
converted (via +7.5V and –7.5V) to a nominal –15V, though
with rather high series resistance (~250Ω).
V
–(V+–VF)
+
1
V
OUT
(2 V+) – (2 VF)
2
+
OUT
C
3
=
C
4
=
+
V
1
2
TC7662B
3
4
Figure 9. Positive Voltage Multiplier
8
D
7
6
5
1
+
C
1
D
2
V
OUT
(2 V+) – (2 VF)
+
C
2
=
Combined Negative Voltage Conversion
and Positive Supply Multiplication
Figure 10 combines the functions shown in Figures 3
and 9 to provide negative voltage conversion and positive
voltage doubling simultaneously. This approach would be,
for example, suitable for generating +9V and –5V from an
existing +5V supply. In this instance, capacitors C1 and C
perform the pump and reservoir functions, respectively, for
the generation of the negative voltage, while capacitors C
and C4 are pump and reservoir, respectively, for the doubled
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.
In some cases, the output impedance of the TC7662B
can be a problem, particularly if the load current varies
substantially. The circuit of Figure 12 can be used to overcome this by controlling the input voltage, via an ICL7611
low-power CMOS op amp, in such a way as to maintain a
nearly constant output voltage. Direct feedback is advisable,
since the TC7662B’s output does not respond instantaneously to change in input, but only after the switching delay.
The circuit shown supplies enough delay to accommodate
the TC7662B, while maintaining adequate feedback. An
increase in pump and storage capacitors is desirable, and
the values shown provide an output impedance of less than
5Ω to a load of 10mA.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your re sponsib ility to en sure that your applicatio n mee ts with your specifica tions. No repr esentation or warra nty is given and no liability is
assumed by Microc hip Technology Incorporated with re spec t to the accur acy or use of such infor mation, or infrin gemen t of patents or other intel lectual
property rights arising from such use or otherwise. Use of Microchipís products as critical components in life support systems is not authorized except with
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