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● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Six Pair, N- and P-Channel
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID
*
= “Green” Packaging
*May be part of top marking
Top Marking
Bottom Marking
YYWW
TC7320FG
LLLLLLLLL
CCCCCCCC
AAA
1
32
Enhancement-Mode MOSFET
TC7320
Features
Six N- and P-channel MOSFET pairs
►
Integrated gate-to-source resistor
►
Integrated gate-to-source Zener diode
►
Low threshold
►
Low on-resistance
►
Low input capacitance
►
Fast switching speeds
►
Free from secondary breakdown
►
Low input and output leakage
►
Applications
High voltage pulsers
►
Amplifiers
►
Buffers
►
Piezoelectric transducer drivers
►
General purpose line drivers
►
Logic level interfaces
►
Ordering Information
32-Lead LQFP
Device
7.00x7.00mm body
1.60mm height (max)
0.80mm pitch
General Description
The Supertex TC7320 consists of a six pairs of high voltage, low
threshold, N- and P-channel MOSFETs in a 32-lead LQFP package.
All of the MOSFETs have integrated gate-to-source resistors and
gate-to-source Zener diode clamps which are desired for high
voltage pulser applications. This low threshold, enhancement-mode
(normally-off), transistor utilizes an advanced lateral DMOS structure
and Supertex’s well-proven silicon-gate manufacturing process. This
combination produces a device with the power handling capabilities
of bipolar transistors and with the high input impedance and positive
temperature coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal runaway and
thermally induced secondary breakdown.
Supertex’s lateral DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
R
BV
/BV
DSS
DGS
(V)
N-Channel P-Channel N-Channel P-Channel
DS(ON)
(max)
(Ω)
TC7320 TC7320FG-G 200 -200 20 20
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BV
Drain-to-gate voltage BV
DSS
DGS
Operating and storage temperature -55°C to +150°C
Soldering temperature* +300°C
Power dissipation 1.5W
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
Package Marking
Package may or may not include the following marks: Si or
32-Lead LQFP (FG)
32-Lead LQFP (FG)
Page 2
TC7320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
R
GEN
Input
Puls
e
Genera to
r
V
DD
R
L
D.U. T
OUTPUT
10
V
0V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON)
t
(OFF)
10%
90
%
90
%
10
%
90
%
10
%
N-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
GS(th)
ΔV
R
ΔR
VZ
ΔVZ
GS(th)
Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 1.0mA
DSS
Gate threshold voltage - 0.4 - V VGS = VDS, ID = 1.0mA
Change in V
Gate-to-source shunt resistor 0.8 - 2.0 KΩ I
GS
Change in RGS with temperature - -7.5 - %/OC I
GS
Gate-to-source Zener voltage 10 - 18 V I
GS
Change in VZGS with temperature - -0.5 - mV/OC I
GS
with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA
GS(th)
= 100µA
GS
= 100µA
GS
= 2.0mA
GS
= 2.0mA
GS
- - 10.0 µA VDS = Max rating, VGS = 0V
I
DSS
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
C
ISS
C
OSS
C
RSS
t
d(ON)
t
t
d(OFF)
t
V
t
Notes:
1.
2.
Zero gate voltage drain current
- - 1.0 mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
On-state drain current 1.0 - - A VGS = 10V, VDS = 25V
Static drain-to-source on-state resistance - - 20 Ω VGS = 10V, ID = 150mA
Change in R
Forward transconductance - 150 - mmho VDS = 25V, ID = 200mA
FS
Input capacitance - - 150
Common source output capacitance - - 75
Reverse transfer capacitance - - 25
with temperature - 0.6 1.0 %/OC VGS = 10V, ID =150mA
DS(ON)
VGS = 0V,
pF
VDS = 25V,
f = 1.0MHz
Turn-on delay time - - 12
Rise time - - 15
r
ns
Turn-off delay time - - 25
Fall time - - 40
f
Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 500mA
SD
Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA
rr
All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
VDD =25V,
ID = 500mA,
R
= 25Ω
GEN
N-Channel Switching Waveforms and Test Circuit
2
Page 3
TC7320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
R
GEN
Input
Puls
e
Generato
r
V
DD
R
L
D.U. T
OUTPUT
0V
-10V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON)
t
(OFF)
90%
10
%
90
%
10
%
10%
90
%
P-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
GS(th)
ΔV
GS(th)
R
ΔR
VZ
ΔZ
I
DSS
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
C
ISS
C
OSS
C
RSS
t
d(ON)
t
t
d(OFF)
t
V
t
Notes:
1.
2.
Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -1.0mA
DSS
Gate threshold voltage - -2.3 - V VGS = VDS, ID = -1.0mA
Change in V
Gate-to-source shunt resistor 0.8 - 2.0 KΩ I
GS
Change in RGS with temperature - -7.5 - %/OC I
GS
Gate-to-source Zener voltage 10 - 18 V I
GS
Change in VZGS with temperature - -0.5 - mV/OC I
GS
Zero gate voltage drain current
with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA
GS(th)
= -100µA
GS
= -100µA
GS
= -2.0mA
GS
= -2.0mA
GS
- - -10 µA V
- - -1.0 mA
= Max rating, V
DS
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
On-state drain current -1.0 - - A VGS = -10V, VDS = -25V
Static drain-to-source on-state resistance - - 20 Ω VGS = -10V, ID = -150mA
Change in R
Forward transconductance - 150 - mmho VDS = -25V, ID = -200mA
FS
Input capacitance - - 200
Common source output capacitance - - 100
Reverse transfer capacitance - - 35
with temperature - 0.6 1.0 %/OC VGS = -10V, ID =-150mA
DS(ON)
VGS = 0V,
pF
VDS = -25V,
f = 1.0MHz
Turn-on delay time - - 15
Rise time - - 20
r
ns
Turn-off delay time - - 35
Fall time - - 30
f
Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -500A
SD
Reverse recovery time - 300 - ns VGS = 0V, ISD = -500A
rr
All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
VDD = -25V,
ID = -500mA,
R
= 25Ω
GEN
GS
= 0V
P-Channel Switching Waveforms and Test Circuit
3
Page 4
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
GP1
GN1
GP2
GN2
GP3
GN3
VPP1
VNN1
DP
1
DN
1
VPP2
VNN2
DP
2
DN
2
DP3
DN
3
VNN3
VPP3
GP4
GN4
DP4
DN
4
VNN1
VPP1
GP5
GN5
DP5
DN
5
VNN2
VPP2
GP6
GN6
DP6
DN
6
VNN3
VPP3
V
SUB
Substrate Bias
0
0.2
0.4
0.6
0.8
1
1.2
1.4
V
DS
(Volts)
I
D
(amperes)
0
10
20
VGS = 5.0V
VGS = 10V
5.0
15 25
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0 -10 -20
V
DS
(Volts)
I
D
(amperes)
VGS = 5.0V
VGS = 10V
-5.0
-15 -25
N-Channel
P-Channel
TC7320
Block DiagramTypical I-V Characteristics
Pin Descriptions
Pin # Function
1 GP1
2 GN1
3 GN2
4 GN3
5 GN6
6 GN5
7 GN4
8 GP4
9 GP5
10 GP6
11
12 VPP2
13 DP5
14 DP4
15 V
16 VNN3
* The V
pin needs to be connected to the most positive supply
SUB
Pin # Function
17 DN6
18 DN3
19 DN5
20 N/C
21 VNN2
22 DN2
23 DN4
DP6
24 DN1
25 VNN1
26 VPP1
27 DP1
28 DP2
29 VPP3
*
SUB
30 DP3
31 GP3
32 GP2
4
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Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com
.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
32-Lead LQFP Package Outline (FG)
Top View
1
32
D
D1
E
E1
b
e
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
Side View
A2
A
A1
View B
Seating
Plane
Note 1
(Index Area
D1/4 x E1/4)
7.00x7.00mm body, 1.60mm height (max), 0.80mm pitch
TC7320
Note:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
1.
a printed indicator.
Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ
MIN 1.40* 0.05 1.35 0.30 8.80* 6.80* 8.80* 6.80*
Dimension
(mm)
NOM - - 1.40 0.37 9.00 7.00 9.00 7.00 0.60 3.5
0.45
0.80
BSC
1.00
REF
0.25
BSC
MAX 1.60 0.15 1.45 0.45 9.20* 7.20* 9.20* 7.20* 0.75 7
JEDEC Registration MS-026, Variation BBA, Issue D, Jan. 2001.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-32LQFPFG, Version E101708.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
O
0
O
O
Doc.# DSFP-TC7320
C122208
5
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