Datasheet TC7129CPL, TC7129CLW, TC7129CKW Datasheet (Microchip Technology)

TC7129

4-1/2 Digit Analog-to-Digital Converters with

On-Chip LCD Drivers

Features

• Count Resolution: ±19,999

• Resolutionon 200mV Scale: 10µV

• True Differential Input and Reference

• Low Power Consumption: 500µAat9V

• Direct LCD Driver for 4-1/2 Digits, Decimal Points,
Low Battery Indicator, and Continuity Indicator

• Over Range and Under Range Outputs

• Range Select Input: 10:1

• High Common Mode Rejection Ratio: 110dB

• External Phase Compensation Not Required

Applications

• Full Featured Multimeters

• Digital Measurement Devices

Device SelectionTable

Package

Code

TC7129CPL Normal 40-PinPDIP 0°Cto+70°C

TC7129CKW Formed 44-Pin PQFP 0°Cto+70°C

TC7129CLW – 44-Pin PLCC 0°Cto+70°C

Pin

Layout

Package

Temperature

Range

General Description

The TC7129 is a 4-1/2 digit analog-to-digital converter
(ADC) that directly drives a multiplexed liquid crystal
display (LCD). Fabricated in high performance, low
power CMOS, the TC7129 AD C is designed specifi­cally for high resolution, battery powered digital multi­meter applications. The traditional dual slope method
of A/D conversion has been enhanced with a succes­sive integration technique to produce readings accu­rate to better than 0.005% of full scale, and resolution
down to 10µV per count.

The TC7129 includes features important to multimeter
applications. It detects and indicates low battery condi­tion. A continuity output drives an annunciator on the
display, and can be used with an external driver to
sound an audible alarm. Over range and under range
outputs and a range change input provide the ability to
create auto-ranging instruments. For snapshot read­ings, the TC7129 includes a latch-and-hold input to
freeze the present reading. Thiscombination of features
makes the TC7129 the ideal choice for full featured
multimeter and digital measurement applications.

Typical Application

Low Battery Continuity

20

13141516171819

12

9

1011

8

TC7129

29

27262524232221

28

*

0.1µF

+

150kΩ

10kΩ

+

9V



2002 Microchip TechnologyInc. DS21459B-page 1

323130

1µF

–

3534

36

20
kΩ

100kΩ

*Note: RC network between Pins 26 and 28 is not required.

+

0.1
µF

V

33

IN

39

3837

V+

5pF

1234567

120kHz

40

330kΩ

10pF

0.1µF

V+

TC7129

Package Type

ANNUNICATOR

B2, C2, LO BATT

Display

Output

Lines

, C1, CONT

B

1

A

F1, E1, DP

A

F2, E2, DP

B3, C

A

F3, E3, DP

B4, C

A4, G4, D

F4, E4, DP

OSC1

OSC3

, G1, D

1

, G2, D

2

MINUS

3

,
, G3, D

3

4

V

DP4/OR

,

BC

BP

BP

BP

DISP

1

2

3

4

5

1

6

1

7

8

2

9

2

10

11

3

12

3

13

5

14

4

15

4

16

3

17

2

18

1

19

20

40-Pin PDIP

TC7129CPL

40

OSC2

DP

39

38

DP

37

RANGE

36

DGND

REF LO

35

REF HI

34

IN HI

33

32

IN LO

31

BUFF

C

30

29

C

28

COMMON

CONTINUITY

27

INT OUT

26

INT IN

25

V+

24

23

V-

22

LATCH/HOLD

21

DP3/UR

REF

REF

1

2

-

+

, E1, DP

F

1

B2, C2, BATT

A

, G2, D

2

F2, E2, DP

B3, C

MINUS

3

,

A

, G3, D

3

F3, E3, DP

B4, C

A4, G4, D

F4, E4, DP

44-Pin QFP 44-Pin PLCC

1

, D

, CONT

1

1

, G

, C

1

1

ANNUNCIATOR

OSC3

A

B

OSC1NCOSC2

44 43 42 41 39 3840

1

1

2

3

2

4

2

5

NC

6

7

3

8

3

BC

9

4

5

,

10

4

11

4

12 13 14 15 17 18

BP3BP

1

2

BP

TC7129CKW

16

/OR

4

DISP

V

DP

NC

/UR

3

DP

1DP2

DP

RANGE

37 36 35 34

19 20 21 22

V-

V+

LATCH/HOLD

DGND

33

32

31

30

29

28

27

26

25

24

23

INT IN

REF LO

REF HI

IN HI

IN LO

BUFF

NC

C

-

REF

C

+

REF

COMMON

CONTINUITY

INT OUT

F1, E1, DP

B2, C2, BATT

A

, G2, D

2

F2, E2, DP

B3, C

MINUS

3

,

A

, G3, D

3

F3, E3, DP

B4, C

A4, G4, D

F4, E4, DP

NC

BC

4

,

1

, D

, CONT

1

1

, G

, C

1

1

A

B

6543 1442

7

1

8

9

2

10

2

11

12

13

3

3

5

4

4

18 19 20 21 23 24

3BP2

BP

ANNUNCIATOR

OSC3

OSC1NCOSC2

TC7129CLW

22

1

/OR

BP

DISP

4

V

DP

NC

/UR

3

DP

DP1DP2RANGE

43 42 41 40

25 26 27 28

V-

V+

LATCH/HOLD

DGND

39

38

37

36

35

34

33

3214

3115

3016

2917

INT IN

REF LO

REF HI

IN HI

IN LO

BUFF

NC

C

-

REF

C

+

REF

COMMON

CONTINUITY

INT OUT

DS21459B-page 2



2002 Microchip TechnologyInc.

TC7129

1.0 ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings*

Supply Voltage (V+ to V-).......................................15V

*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affectdevice reliability.

Reference Voltage (REF HI or REF LO) ......... V+ to V-

Input Voltage (IN HI or IN LO) (Note 1)........... V+ to V-

.......................................... V+ to (DGND – 0.3V)

V

DISP

Digital Input (Pins 1, 2, 19, 20,

21, 22, 27, 37, 39, 40).......................... DGND to V+

Analog Input (Pins 25, 29, 30) ........................ V+ to V-

Package Power Dissipation (T

≤ 70°C)

A

Plastic DIP .....................................................1.23W

PLCC .............................................................1.23W

Plastic QFP ....................................................1.00W

Operating Temperature Range ............... 0°C to +70°C

StorageTemperature Range ..............-65°C t o +150°C

TC7129 ELECTRICAL SPECIFICATIONS

Electrical Characteristics: V+ to V- = 9V, V

Pinnumbersreferto40-pinDIP.

Symbol Parameter Min Typ Max Unit Test Conditions

=1V,TA=+25°C,f

REF

= 120kHz, unless otherwise indicated.

CLK

Input

Zero InputReading -0000 0000 +0000 Counts V
Zero Reading Drift — ±0.5 — µV/°C V
Ratiometric Reading 9997 9999 10000 Counts V
RangeChange Accuracy 0.9999 1.0000 1.0001 Ratio V

RE Rollover Error — 1 2 Counts V
NL Linearity Error — 1 — Counts 200mV Scale
CMRR Common Mode Rejection Ratio — 110 — dB V
CMVR Common Mode Voltage Range — (V-) + 1.5 — V V

— (V+) – 1 — V 200mV Scale

e

N

I

IN

Power

V

COM

DGND Digital Ground Voltage 4.5 5.3 5.8 V V+ to Pin 36, V+ to V- = 9V

I

S

Note 1: Input voltages may exceed supply voltages, provided input current is limited to ±400µA. Currents above this value may

Noise (Peak-to-Peak Value not
Exceeded 95% of Time)

Input Leakage Current — 1 10 pA VIN=0V,Pins32,33
Scale Factor Temperature Coefficient — 2 7 ppm/°C V

Common Voltage 2.8 3.2 3.5 V V+ to Pin 28
CommonSinkCurrent — 0.6 — mA ∆Common = +0.1V
CommonSource Current — 10 — µA ∆Common = -0.1V

Sink Current — 1.2 — mA ∆DGND= +0.5V
Supply Voltage Range 6 9 12 V V+ to V­SupplyCurrent ExcludingCommon

Current

result in invalid display readings, but will not destroy the device if limited to ±1mA. Dissipation ratings assume device is
mounted with all leads soldered to printed circuit board.

—14—µV

—0.81.3mAV+toV-=9V

P-PVIN

= 0V,200mV Scale

IN

=0V,0°C<TA<+70°C

IN
IN=VREF
IN

V

IN
IN

CM
IN

200mV Scale

IN

External V

= 1000mV, Range= 2V

=1VonHighRange,
= 0.1V on Low Range

-=VIN+ = 199mV

=1V,VIN= 0V,200mV Scale

=0V

=0V

= 199mV, 0°C < TA<+70°C

=0ppm/°C

REF



2002 Microchip TechnologyInc. DS21459B-page 3

TC7129

TC7129 ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: V+ to V- = 9V, V

Pinnumbersreferto40-pinDIP.

Symbol Parameter Min Typ Max Unit Test Conditions

f

CLK

Digital

Note 1: Input voltages may exceed supply voltages, provided input current is limited to ±400µA. Currents above this value may

ClockFrequency — 120 360 kHz

Resistance — 50 — kΩ V

V

DISP

Low Battery Flag Activation Voltage 6.3 7.2 7.7 V V+ to V-

Continuity Comparator Threshold
Voltages

Pull-down Current — 2 10 µA Pins 37, 38, 39
"Weak Output" Current

Sink/Source
Pin 22 Source Current — 40 — µA

Pin22SinkCurrent — 3 — µA

result in invalid display readings, but will not destroy the device if limited to ±1mA. Dissipation ratings assume device is
mounted with all leads soldered to printed circuit board.

=1V,TA=+25°C,f

REF

100 200 — mV V

— 200 400 mV V

—3/3— µA Pins 20, 21 Sink/Source
—3/9— µA Pin 27 Sink/Source

= 120kHz, unless otherwise indicated.

CLK

DISP

OUT
OUT

to V+

Pin27=High
Pin27=Low

DS21459B-page 4



2002 Microchip TechnologyInc.

TC7129

2.0 PIN DESCRIPTIONS

ThedescriptionsofthepinsarelistedinTable2-1.

TABLE 2-1: PIN FUNCTION TABLE

Pin No.

40-PinPDIP

1 40 2 OSC1 Input to first clock inverter.
2 41 3 OSC3 Output of second clock inverter.
3 42 4 ANNUNCIATOR Backplane square wave output for driving annunciators.
443 5B
544 6A
61 7F
72 8B
83 9A
9410F

10 5 11 B

11 7 13 A
12 8 14 F
13 9 15 B
14 10 16 A
15 11 17 F
16 12 18 BP
17 13 19 BP
18 14 20 BP
19 15 21 V
20 16 22 DP

21 18 24 DP

22 19 25 LATCH

23 20 26 V- Negative power supply terminal.
24 21 27 V+ Positive power supply terminal and positive rail for display drivers.
25 22 28 INT IN Inputto integrator amplifier.
26 23 29 INT OUT Output of integrator amplifier.
27 24 30 CONTINUITY Input: When LO, continuityflagon the displayis OFF. When HI,

28 25 31 COMMON Sets Commonmode voltage of 3.2V belowV+ for DE, 10X, etc.

29 26 32 C
30 27 33 C
31 29 35 BUFFER Output of buffer amplifier.
32 30 36 IN LO Negativeinputvoltage terminal.
33 31 37 IN HI Positive input voltage terminal.
34 32 38 REF HI Positive referencevoltage.
35 33 39 REF LO Negative reference voltage

Pin No.

44-Pin PQFP

Pin No.

44-PinPLCC

Symbol Function

, CONT Output to display segments.

1,C1

1,G1,D1

,DP1Output to display segments.

1,E1

, LO BATT Output to display segments.

2,C2

2,G2,D2

,DP2Output to display segments.

2,E2

, MINUS Output to display segments.

3,C3

3,G3,D3

,DP3Output to display segments.

3,E3

,BC5Output to display segments.

4,C4

4,D4,G4

,DP4Output to display segments.

4,E4

3
2
1

DISP

/OR Input: When HI, turns on most significant decimal point.

4

/UR Input: Second most significant decimal point on when HI.

3

Output to display segments.

Output to display segments.

Output to display segments.

Output to display segments.

Backplane #3 output to display.
Backplane #2 output to display.
Backplane #1 output to display.
Negative rail for display drivers.

Output: Pulled HI when result count exceeds ±19,999.

Output: Pulled HI when result count is less than ±1000.

/HOLD Input: When floating, ADC operates in the Free Run mode. When

pulled HI, the last displayed reading is held. When pulled LO, the
result counter contents are shown incrementing during the
de-integrate phase of cycle.
Output: Negative going edge occurs when the data latches are
updated. Can be used forconverter statussignal.

continuity flag is ON.
Output: HI whenvoltage betweeninputs is less than +200mV. LO
when voltage between inputs is more than +200mV.

Can be used as pre-regulator for external reference.

+ Positive side of external reference capacitor.

REF

REF-

Negative side of external reference capacitor.



2002 Microchip TechnologyInc. DS21459B-page 5

TC7129

TABLE 2-1: PIN FUNCTION TABLE (CONTINUED)

Pin No.

40-PinPDIP

36 34 40 DGND Internal ground reference for digital section. See Section 4.3,

37 35 41 RANGE 3µA pull-downfor 200mV scale. Pulled HI externallyfor2V scale.
38 36 42 DP
39 37 43 DP
40 38 44 OSC2 Output of first clock inverter. Inputof second clockinverter.

— 6,17, 28, 39 12, 23, 34, 1 NC No connection.

Pin No.

44-Pin PQFP

Pin No.

44-PinPLCC

Symbol Function

±5V Power Supply.

2

Internal 3µA pull-down. When HI, decimal point 2 will be on.
Internal 3µA pull-down. When HI, decimal point 1 will be on.

1

DS21459B-page 6



2002 Microchip TechnologyInc.

TC7129

3.0 DETAILED DESCRIPTION

(All Pin Designations Refer to 40-Pin PDIP.)
The TC7129 is designed to be the heart of a high

resolution analog measurement instrument. The only
additional components required are a few passive ele­ments: a voltage reference, an LCD, and a power
source. Most componentvalues are not critical; substi­tutes can be chosen based on the information given
below.

The basic circuit for a digital multimeter application is
shown i n Figure 3-1. See Section 4.0, TypicalApplica­tions for variations.Typicalvalues for each component
are shown. The sections below give component selec­tion criteria.

3.1 Oscillator (X

The primary criterion for selecting the crystal oscillator
is to choose a frequencythatachievesmaximumrejec­tion of line frequency noise. To do this, the integration
phase should last an integral number of line cycles.
The integration phase of the TC7129 is 10,000 clock
cycles on the 200mV range and 1000 clock cycles on
the 2V range. One clock cycle is equal to two oscillator
cycles. For 60Hz rejection, the oscillator frequency
should be chosen so that the period of one line cycle
equals the integration time for the 2V range:

OSC,CO1,CO2,RO

)

The resistor and capacitorvalues are not critical; those
shown work for most applications. In some situations,
the capacitor values may have to be adjusted to com­pensate for parasitic capacitance in the circuit. The
capacitorscan be low cost ceramic devices.

Some applications can use a simple RC network
instead of a crystal oscillator. The RC oscillator has
more potential for jitter, especially in the least
significantdigit. See Section 4.8, RC Oscillator.

3.2 Integrating Resistor (R

The integrating resistor sets the charging current for
the integrating capacitor.Choose a value that provides
a current between 5µA and 20µA at 2V, the maximum
full scale input. The typical value chosen gives a
charging current of 13.3µA:

INT

)

EQUATION 3-2:

I

CHARGE

ToohighavalueforR
noise pickup and increases errors due to leakage cur­rent. Too low a value degrades the linearity of the
integration,leading to inaccurate readings.

2V

=

INT

150kΩ

13.3µA

increases the sensitivity to

EQUATION 3-1:

1/60 second = 16.7msec =

1000 clock cycles *2 OSC cycles/clock cycle

OSC Frequency

This equation gives an oscillator frequency of 120kHz.
A similar calculation gives an optimum f requency of
100kHz for 50Hz rejection.



2002 Microchip TechnologyInc. DS21459B-page 7

TC7129

FIGURE 3-1: STANDARD CIRCUIT

Low Battery Continuity

V+

20

DP

4

/OR

DP

3

/UR

V

DISP

LATCH/

HOLD

V-

V+

+

INT IN

9V

13141516171819

Display Drive Outputs

CONTINUITY

COMMON

INT OUT

27262524232221

28

C

INT

0.1µF

150kΩ

R

10kΩ
R

BIAS

12

TC7129

C

C

REF

REF

+

-

29

C

+

REF

1µF

INT

9

1011

8

IN LO

323130

0.1
µF

C

V

33

IF

IN

IN HI

REF HI

R

IF

100kΩ

BUFF

– +

REF LO

3534

36

R

REF

20

kΩ

DGND

ANNUNC

RANGE

DP

2

3837

D

REF

OSC3

DP

1

39

1234567

OSC1

OSC2

40

C

RF

0.1µF

5pF

120

kHz

330kΩ

R

O

10pF

V+

C

O1

Crystal

C

O2

3.3 Integrating Capacitor (C

INT

)

The charge stored in the integrating capacitor during
the integrate phase is directly proportional to the input
voltage. The primary selection criterion for C

INT

is to
choose a value that gives the highest voltage swing
while remaining within the high linearity portion of the
integratoroutputrange.Anintegratorswingof2V is the
recommended value. The capacitor value can be
calculated using t he following equation:

EQUATION 3-3:

t

INTxIINT

=

INT

V

SWING

is the integration time.

Where t

C

INT

Using the values derived above (assuming 60Hz
operation), the equation becomes:

EQUATION 3-4:

C

16.7msec x 13.3µA

==0.1µA

INT

2V

The capacitor should have low dielectric absorption to
ensure good integration linearity. Polypropylene and
Teflon capacitors are usually suitable. A good mea­surement of the dielectric absorption is to connect the
reference capacitor across the inputs by connecting:

Pin to Pin:

20 → 33 (C

30 → 32 (C

+toINHI)

REF

-toINLO)

REF

A reading between 10,000 and 9998 is acceptable;
anything lower i ndicates unacceptably high dielectric
absorption.

3.4 Reference Capacitor (C

REF

)

The reference capacitor stores the reference voltage
during several phases of the measurement cycle. Low
leakage is the primary selection criterion for this com­ponent. The value must be high enough to offset the
effectof stray capacitance at the capacitor terminals.A
valueofatleast1µF is recommended.

DS21459B-page 8



2002 Microchip TechnologyInc.

TC7129

3.5 Voltage Reference
(D

REF,RREF,RBIAS,CRF

The reference potentiometer (R
adjustment for adjusting the reference voltage; any
value above 20kΩ is adequate. The bias resistor
(R

) limits the current through D

BIAS

150µA. The reference filter capacitor (C
RC filter with R

to help eliminate noise.

BIAS

)

)providesan

REF

to less than

REF

)formsan

RF

3.6 Input Filter (RIF,CIF)

For added stability, an RC input noise filter is usually
included in the circuit. The input filter resistor value
should not exceed 100kΩ. A typical RC time constant
value is 16.7msec to help reject line frequency noise.
The input filter capacitor should have low leakagefor a
high-impedanceinput.

3.7 Battery

The typicalcircuitusesa 9V battery as a power source.
Any value between6V and 12V can be used. For oper­ationfrom batteries with voltages lower than6V and for
operation from power supplies, see Section 4.2,
Powering the TC7129.

4.0 TYPICAL APPLICATIONS

4.1 TC7129 as a Replacement Part

The TC7129 is a direct pin-for-pinreplacement part for
the ICL7129. Note, however, that part requires a
capacitor and resistor between Pins 26 and 28 for
phase compensation. Since the TC7129 uses internal
phase compensation,these parts are not requiredand,
in fact, must be removed from the circuit for stable
operation.

4.2 Powering the TC7129

While the most common power source for the TC7129
is a 9V battery, there are other possibilities. Some of
the more common ones are explained below.

4.3 ±5V Power Supply

Measurements are made with respect to power supply
ground. DGND (Pin 36) is set internally to about 5V
less than V
ply input and must not be tied directly to power supply
ground.Itcan be usedas a reference for external logic,
as explained in Section 4.6, Connecting to External
Logic (see Figure 4-1).

+ (Pin 24); it is not intended as a power sup-

FIGURE 4-1: POWE RING THE TC7129

FROM A ±5V POWER
SUPPLY

+5V

TC7129

24

-5V

0.1µF

0.1µF

0.1µF

36

V+

REF HI

REF LO

DGND

COMMON

V-

IN HI

IN LO

23

34

35

28

33

32

+

V

IN

–

4.4 Low Voltage Ba ttery S ource

A battery with voltage between 3.8V and 6V can be
used to power the TC7129, when used with a voltage
doubler circuit, as shown in Figure 4-2. The voltage
doubler uses the TC7660 DC-to-DC voltage converter
and t wo external capacitors.

FIGURE 4-2: POWE RING THE TC7129

FROM A LOW VOLTAGE
BATTERY

24

V+

36

+

3.8V
to
6V

8

2

+

TC7660

4

5

10µF

3

+

REF HI

DGND

REF LO

COMMON

TC7129

V-

10µF

IN HI

IN LO

23

34

35

28

33

32

+

V

IN

–



2002 Microchip TechnologyInc. DS21459B-page 9

TC7129

–

4.5 +5V Power Supply

Measurements are made with respect to power supply
ground. COMMON (Pin 28) is connected to REF LO
(Pin 35). A voltage doubler is needed, since the supply
voltage is less than the 6V minimum needed by the
TC7129. DGND (Pin 36) must be isolated from power
supply ground (see Figure 4-3).

FIGURE 4-3: POWE RING THE TC7129

FROM A +5V POWER
SUPPLY

+5V

24

V+

34

35

28

33

32

V-

23

+

V

IN

8

V+

TC7660

GND

3

0.1µF

2

4

5

0.1µF

+

10µF

+

36

10µF

TC7129

DGND

FIGURE 4-4: EX TERNAL LOGIC

REFERENCED DIRECTLY
TO DGND

+

V

24

External

Logic

I

LOGIC

36

TC7129

DGND

23

V-

FIGURE 4-5: EX TERNAL LOGIC

REFERENCED TO DGND
WITH BUFFER

V+

24

External

Logic

TC7129

4.6 Connecting to External Logic

External logic can be directly referenced to DGND
(Pin 36), provided that the supply current of the exter­nal logic does not exceed the sink current of DGND
(Figure 4-4). A safe value for DGND sink current i s

1.2mA. If the sink current is expected to exceed this
value, a buffer is recommended (see Figure 4-5).

–

36

+

DGND

I

LOGIC

23

V-

4.7 Temperature Compensation

For most applications,V
directly to DGND (Pin 36). For applications with a wide
temperature range, some LCDs require that the drive
levels vary with temperature to maintain good viewing
angle and display contrast. Figure 4-6 shows two cir­cuits that can be adjusted to give temperature com­pensation of about 10mV/°C between V+ (Pin 24) and
V

. The diode between DGND and V

DISP

have a low turn-on voltage because V
exceed 0.3V below DGND.

(Pin19)canbe connected

DISP

DISP

DISP

should

cannot

DS21459B-page 10



2002 Microchip TechnologyInc.

FIGURE 4-6: TEMPERATURE COMPENSATING CIRCUITS

V+

TC7129

V+

1N4148

39kΩ

200kΩ

TC7129

5kΩ

75kΩ

–

+

19

36

V

DISP

DGND

4.8 RC O scillator

For applications in which 3-1/2 digit (100µV) resolution
is sufficient, an RC oscillator is adequate. A recom­mended value for the capacitor is 51pF. Other v alues
can be used as long as they are sufficiently larger than
the circuit parasitic capacitance. The resistor value is
calculated as:

EQUATION 4-1:

0.45

R=

Freq * C

For 120kHz frequency and C = 51pF, the calculated
value of R is 75kΩ. The RC oscillator and the crystal
oscillator circuits are shown in Figure 4-7.

FIGURE 4-7: OSCILLATOR CIRCUITS

TC7129

1 40 2

270kΩ

10pF

V+

V+

5pF

120kHz

24

20kΩ

23

V-

39kΩ

18kΩ

2N2222

19

36

TC7129

V

DISP

DGND

V-

24

23

4.9 Measuring Techniques

Twoimportant techniquesareusedintheTC7129:suc­cessive integration and digital auto-zeroing. Succes­sive integration is a refinement to the traditional dual
slope conversion technique.

4.10 Dual Slope Conversion

A dual slope conversion has t wo basic phases: inte­grate and de-integrate.During the integrate phase, the
input signal is integrated for a fixed period of time; the
integratedvoltagelevel is t hus proportionalto the input
voltage. During the de-integrate phase, the integrated
voltageis ramped down at a f ixed slope, and a counter
counts the clock cycles until the integrator voltage
crosses zero. The count is a measurement of t he time
to ramp the integrated voltage to zero, and is, there­fore, proportional t o the input voltage being measured.
This count can then be scaled and displayed as a mea­surement of the input voltage. Figure 4-8 shows the
phases of the dual slope conversion.

FIGURE 4-8: DUAL SLOPE

CONVERSION

Integrate

De-integrate

Zero
Crossing

1 40 2

75kΩ

51pF

TC7129

Time

The dual slope method has a fundamental limitation.
The count c an only stop on a clock cycle, so that mea­surement accuracy is limited to the clock f requency. In
addition, a delay in the zero cr ossing comparator can
add to t he inaccuracy. Figure 4-9 shows these errors in
an actual measurement.



2002 Microchip TechnologyInc. DS21459B-page 11

TC7129

r

FIGURE 4-9: ACCURACY ERRORS IN DUAL SL OPE CONVERSION

Integrate

De-integrate

Time

Clock Pulses

FIGURE 4-10: INTEGRATION WAVEFORM

Zero Integrate

and Latch

INT

1

Integrate

DE

1

De-integrate

REST X10

Over shoot due to zero crossing between
clock pulses

Integrator Residue Voltage

Over shoot caused by comparato
delay of 1 clock pulse

DE

2

REST X10

DE

3

Zero Integrate

TC7129

Note: Shaded area greatly expanded in time and amplitude.

Integrator

Residual Voltage

DS21459B-page 12



2002 Microchip TechnologyInc.

TC7129

4.11 Successive Integration

The successive integration technique picks up where
dual slope conversion ends. The over shoot voltage
shown in Figure 4-9, called the "integrator residue volt­age," is measured to obtain a correction to the initial
count. Figure 4-10 shows the cycles i n a successive
integration measurement.

The waveform shown is for a negativeinput signal.The
sequence of events during the measurement cycle is
shown in Table4-1.

TABLE 4-1: MEASUREMENT CYCLE

SEQUENCE

Phase Description

Inputsignal is integratedfor fixed time (1000 clock

INT

1

cycleson 2V scale, 10,000on 200 mV).
Integrator voltage is ramped to zero.Counter

DE

1

countsup until zero crossing to produce reading
accurate to 3-1/2 digits. Residue represents an
over shoot of the actual input voltage.

REST Rest; circuit settles.

X10 Residue voltage is amplified 10 times and inverted.

Integrator voltage is ramped to zero.Counter

DE

2

countsdownuntil zero crossing to correct reading
to 4-1/2 digits. Residue represents an under shoot
of the actual input voltage.

REST Rest; circuit settles.

X10 Residue voltage is amplified 10 times and inverted.

Integrator voltage is ramped to zero.Counter

DE

3

counts up until zero crossing to correct reading to
5-1/2 digits. Residue is discarded.

4.12 Digital Auto-Zeroing

To eliminate the effect of amplifier offset errors, the
TC7129 uses a digitalauto-zeroingtechnique. Afterthe
input voltage is measured as described above, the
measurement is repeatedwith the inputsshorted inter­nally. The reading with inputs shorted is a measure­ment of the internal errors and is subtracted from the
previous reading to obtain a corrected measurement.
Digitalauto-zeroingeliminatesthe need for an external
auto-zeroing capacitor used in other ADCs.

4.13 Inside the TC7129

Figure 4-11 shows a simplified block diagram of the
TC7129.



2002 Microchip TechnologyInc. DS21459B-page 13

TC7129

FIGURE 4-11: TC7129 FUNCTIONAL BLOCK DIAGRAM

Low Battery Continuity

OSC1

OSC2

OSC3

RANGE

L/H

CONT

DGND

V+
V-

TC7129

Segment Drives

Latch, Decode Display Multiplexer

Up/Down Results Counter

Sequence Counter/Decoder

Control Logic

Analog Section

Backplane

Drives

Annunciator

Drive

V

DISP

DP

1

DP

2

UR/DP

OR/DP

REF HI

REF LO

INT OUT

INT IN

3

4

COMMON INHIIN

LO

FIGURE 4-12: INTEGRATOR BLOCK DIAGRAM

IN HI

Common

IN LO

Continuity

INT

INT

INT

1

,

–

V

200mV

REF HI

1

2

+

C

REF

REF LO

DE

DE

DE- DE+

DE+

DE-

INT

–

+

Continuity
Comparator

–

+

ZI, X10

REST

500kΩ

Buffer

R

INT

C

INT

Integrator

–

+

100pF

TC7129

BUFF

X10

10

Comparator 1

pF

To Display Driver

+

To Digital
Section

–

Comparator 2

DS21459B-page 14



2002 Microchip TechnologyInc.

TC7129

4.14 Integrator Section

The integrator section includes the integrator, compar­ator, input buffer amplifier, and analog switches (see
Table 4-2),used to change the circuitconfigurationdur­ing the separate measurement phases described ear­lier. See Integrator Block Diagram (Figure 4-12).

TABLE 4-2: SWITCH LEGENDS

Label Description

Label Meaning.

DE Openduring all de-integratephases.

DE– Closed during all de-integrate phases when

input voltage is negative.

DE+ Closed during all de-integrate phases when

input voltage is positive.

INT

INT

INT Open duringbothintegrate phases.

REST Closed during the rest phase.

ZI Closed duringthe zero integrate phase.
X10 ClosedduringtheX10phase.
X10 OpenduringtheX10phase.

Closedduring the first integrate phase(mea-

1

surement of the input voltage).
Closed during the second integrate phase

2

(measurement of the amplifieroffset).

FIGURE 4-13: CONTINUITY INDICATOR

CIRCUIT

–

IN HI

COM

IN LO

CONT

200mV

V

–

500kΩ

+

+

Buffer

TC7129

To Display Driver

(Not Latched)

FIGURE 4-14: INPUT/OUTPUT PIN

SCHEMATIC

TC7129

The buffer amplifierhas a Commonmode input voltage
range from 1.5V above V-to 1V below V+. The integra­tor amplifier can swing to within 0.3V of the rails,
althoughforbestlinearity, the swing is usuallylimited to
within 1V. Both amplifiers can supplyup to 80µAofout­put current, but should be limited to 20µA for good
linearity.

4.15 Cont inuity Indicator

A comparator with a 200mV threshold is connected
between IN HI (Pin 33) and IN LO (Pin 32). Whenever
the voltage between inputs is less than 200mV, the
CONTINUITY output (Pin 27) will be pulled HIGH, acti­vating the continuity annunciator on the display. The
continuity pin can also be used as an input to drive t he
continuity annunciator directly from an external source
(see Figure 4-13).

A schematic of the input/output nature of this pin isalso
shown in Figure 4-14.

/OR, Pin 20

DP

4

DP3/UR, Pin 21
LATCH/HOLD Pin 22
CONTINUITY, Pin 27

500kΩ

4.16 Com m on and Digital Ground

The common and digital ground (DGND) outputs ar e
generated from internal zener diodes. The voltage
between V+ and DGND is t he internal supply voltage
for the digital section of the TC7129. Common can
source approximately 12µA; DGND has essentially no
source capability (see Figure 4-15).



2002 Microchip TechnologyInc. DS21459B-page 15

TC7129

FIGURE 4-15: DIGITALGROUND(DGND)

AND COMMON OUT P UTS

24

V+

12µA

–

+

N

Logic

Section

3.2V

COM

28

5V

36

P

DGND

TC7129

N

23

V-

4.17 Low Battery

The low battery annunciatorturns on when supply volt­age between V- and V+ drops below 6.8V. The internal
zener has a threshold of 6.3V.When the supply voltage
drops below 6.8V, the transistor tied to V- turns OFF,
pulling the "Low Battery" point HIGH.

4.18 S equence and Results Counter

A sequence counter and associated control logic pro­vide signals that operate the analog switches in the
integratorsection. The comparatoroutputfromt he inte­grator gates the results counter. The results counter is
a six-section up/down decade counter,which holds the
intermediate results from each successive integration.

4.19 Over Range and Under Range
Outputs

When the results counter holds a value greater than
±19,999, the DP
When the results counter value is less than ±1000, t he
DP

/UR output (Pin 21) is driven HIGH. Both signals

3

are valid on the falling edge of LATCH
do not change until the end of the next conversion
cycle. The signals are updated at the end of each con­version, unless the L
Pins 20 and 21 can also be used as inputs for external
control of decimal points 3 and 4. Figure 4-14 shows a
schematic of the i nput/output nature of these pins.

/OR output (Pin 20) is driven HIGH.

4

/HOLD (L/H) and

/H input (Pin 22) is held HIGH.

4.20 LATCH/Hold

The L/H output goes LOW during the last 100 cycles of
each conversion. This pulse latches the conversion
data into the display driver section of the TC7129. This
pin can also be used as an i nput. W hen driven HI GH,
the display will not be updated; the previous reading is
displayed.WhendrivenLOW, thedisplayreadingisnot
latched; the sequence counter reading will be dis­played. Since the counter is counting much fasterthan
the backplanes are being updated, the reading shown
in this mode is somewhat erratic.

4.21 Display Driver

TheTC7129drivesatriplexedLCDwiththreeback­planes. The LCD c an include decimal points, polarity
sign, and annunciators for continuity and low battery.
Figure 4-16 shows the assignment of the display seg­ments to the backplanes and segment drive lines. The
backplane drive frequency is obtained by dividing the
oscillator frequency by 1200. This results in a back­plane drive frequency of 100Hz for 60Hz operation
(120kHz crystal) and 83.3Hz for 50Hz operation
(100kHz crystal).

Backplane waveforms are shown in Figure 4-17.
These appear on outputs BP
and 18). They remain the same, regardless of the seg­ments being driven.

Other display output lines (Pins 4 through 15) have
waveforms that vary depending on the displayed val­ues.Figure 4-18 shows a setof waveformsfortheA, G,
D outputs (Pins 5, 8, 11, and 14) for several combina­tions of "ON" segments.

The ANNUNCIATOR DRIVE output (Pin 3) is a square
wave, running at the backplane frequency ( 100Hz or

83.3Hz) with a peak-to-peak voltage equal to DGND
voltage. Connecting an annunciator to Pin 3 turns it
ON; connecting it to its backplane turns it OFF.

,BP2,BP3(Pins 16, 17,

1

DS21459B-page 16



2002 Microchip TechnologyInc.

FIGURE 4-16: DISPLAY SEGMENT AS SIGNMENTS

TC7129

Low Battery

Continuity

BP

BP

1

2

Backplane
Connections

BP

3

Low Battery Continuity

E

DP

F

4

4

4

,

,

G

D

A

4

4

4

,

,

C

BC

B

4

4

4

,

,

F

E

DP

3

3

3

,

,

G

D

A

3

3

3

,

,

C

MINUS

B

3

3

,

,

B

1

,

A

1

,

F

1

,

B

2

,

A

2

,

F

2

,

C

Continuity

1

,

G

D

1

,

E

DP

1

,

C

Low Battery

2

,

G

D

2

,

E

DP

2

,

1

1

2

2

FIGURE 4-17: BACKPLANE

WAVEFORMS

BP

1

BP

2

BP

3

FIGURE 4-18: TYPICAL DISPLAY

OUTPUT WAVEFORMS

b Segment

Line

All Off

a Segment

On

d, g Off

a, g On

d Off

All On

V
V

V
V

V
V

V
V

V
V

V
V

V
V

V
V

DD
H

L

DISP

DD
H

L

DISP

DD
H

L

DISP

DD
H

L

DISP



2002 Microchip TechnologyInc. DS21459B-page 17

TC7129

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Package marking data not available a this time.

5.2 Taping Forms

Component Taping Orientation for 44-Pin PLCC Devices

User Direction of Feed

PIN 1

W

P

Standard Reel Component Orientation
for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

44-Pin PLCC 32 mm 24 mm 500 13 in

Note: Drawing does not represent total number of pins.

Component Taping Orientation for 44-Pin PQFP Devices

User Direction of Feed

PIN 1

W

DS21459B-page 18

P

Standard Reel Component Orientation
for TR Suffix Device

Carrier Tape, Number of Components Per Reel and Reel Size

Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size

44-Pin PQFP 24 mm 16 mm 500 13 in

Note: Drawing does not represent total number of pins.



2002 Microchip TechnologyInc.

5.3 Package Dimensions

TC7129

40-Pin PDIP (Wide)

.200 (5.08)
.140 (3.56)

.150 (3.81)
.115 (2.92)

.110 (2.79)
.090 (2.29)

2.065 (52.45)

2.027 (51.49)

.070 (1.78)
.045 (1.14)

.022 (0.56)
.015 (0.38)

PIN 1

.555 (14.10)
.530 (13.46)

.040 (1.02)
.020 (0.51)

.015 (0.38)
.008 (0.20)

.610 (15.49)
.590 (14.99)

3° MIN.

.700 (17.78)
.610 (15.50)

Dimensions: inches (mm)

44-Pin PLCC

.695 (17.65)
.685 (17.40)

.656 (16.66)
.650 (16.51)

.656 (16.66)
.650 (16.51)

.695 (17.65)
.685 (17.40)

PIN 1

.050 (1.27) TYP.

.021 (0.53)
.013 (0.33)

.630 (16.00)
.591 (15.00)

.032 (0.81)
.026 (0.66)

.020 (0.51) MIN.

.120 (3.05)
.090 (2.29)

.180 (4.57)
.165 (4.19)

Dimensions: inches (mm)



2002 Microchip TechnologyInc. DS21459B-page 19

TC7129

(

5.3 Package Dimensions (Continued)

44-Pin PQFP

PIN 1

.018 (0.45)
.012 (0.30)

.031 (0.80) TYP.

.398 (10.10)

.390 (9.90)

.557 (14.15)
.537 (13.65)

.398 (10.10)

.390 (9.90)

.557 (14.15)
.537 (13.65)

.009 (0.23)
.005 (0.13)

.096

7° MAX.

.041 (1.03)
.026 (0.65)

.010 (0.25) TYP.

.083 (2.10)
.075 (1.90)

2.45) MAX.

Dimensions: inches (mm)

DS21459B-page 20



2002 Microchip TechnologyInc.

NOTES:

TC7129



2002 Microchip TechnologyInc. DS21459B-page 21

TC7129

SALES AND SUPPORT

Data Sheets

Products supportedby a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mendedworkarounds.To determine if an errata sheet exists for a particulardevice, please contactone of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX:[phone]

3. The Microchip Worldwide Site (www.microchip.com)
Pleasespecify which device, revision of silicon and Data Sheet (includeLiterature#) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to r eceive the most current information on our products.

DS21459B-page 22



2002 Microchip TechnologyInc.

TC7129

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com­ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con­veyed, implicitly or otherwise, under any intellectual property
rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,
K

EELOQ,microID,MPLAB,PIC,PICmicro,PICMASTER,

PICSTART, PRO MATE, SEEV AL and The Embedded Control

SolutionsCompany areregiste red trademarksof MicrochipTech­nologyIncorp or ated in the U.S.A. and other countries .

dsPIC, ECONOMONITOR, FanSens e, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Enduranceare trademarksof MicrochipTechnology
Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its

®

PICmicro
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systemsisISO 9001certified.



2002 Microchip TechnologyInc. DS21459B-page 23

8-bit MCUs, KEELOQ®code hopping

WORLDWIDE SALES AND SERVICE

AMERICAS

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03/01/02

DS21459B-page 24

*DS21459B*



2002 Microchip Technology Inc.