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● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
N- and P-Channel
INA
INB
OE
-100V
+100V
Supertex
TC6320
10nF
10nF
VDD
VSS
VH
VL
Supertex
MD12xx, MD17xx, or MD18xx
Enhancement-Mode MOSFET Pair
TC6320
Features
Integrated gate-to-source resistor
►
Integrated gate-to-source Zener diode
►
Low threshold
►
Low on-resistance
►
Low input capacitance
►
Fast switching speeds
►
Free from secondary breakdown
►
Low input and output leakage
►
Independent, electrically isolated N- and P-channels
►
Applications
High voltage pulsers
►
Amplifiers
►
Buffers
►
Piezoelectric transducer drivers
►
General purpose line drivers
►
Logic level interfaces
►
General Description
The Supertex TC6320 consists of high voltage, low threshold
N-channel and P-channel MOSFETs in 8-Lead SOIC and
DFN packages. Both MOSFETs have integrated gate-tosource resistors and gate-to-source Zener diode clamps
which are desired for high voltage pulser applications. It is a
complimentary, high-speed, high voltage, gate-clamped Nand P-channel MOSFET pair, which utilizes an advanced
vertical DMOS structure and Supertex’s well-proven
silicon-gate manufacturing process. This combination
produces a device with the power handling capabilities of
bipolar transistors and with the high input impedance and
positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Typical Application Circuit
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● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Ordering Information
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YY WW
C6320
L L LL
6320
Y W L L
Y = Last Digit of Year Sealed
W = Code for Week Sealed
L = Lot Number
= “Green” Packaging
8
1
2
3
4
7
6
5
SN
GN
DN
GP
SP
DN
DP
DP
DN
DP
DP
DP
GN
SN
SP
DN
DN
GP
1
2
3
4
5
6
7
8
Package Options
BV
DSS
/BV
(V)
DGS
TC6320
R
DS(ON)
(max) (Ω)
Device
8-Lead DFN
4.0x4.0mm body
1.0mm height (max)
1.0mm pitch (dual pad)
8-Lead SOIC
4.9x3.9mm body
1.75mm height (max)
1.27mm pitch
N-Channel P-Channel N-Channel P-Channel
TC6320 TC6320K6-G TC6320TG-G 200 -200 7.0 8.0
-G indicates package is RoHS compliant (‘Green’)
Pin Configurations
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BV
Drain-to-gate voltage BV
Operating and storage temperature -55°C to +150°C
Soldering temperature* +300°C
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is not
implied. Continuous operation of the device at the absolute rating level
may affect device reliability. All voltages are referenced to device ground.
DSS
DGS
8-Lead DFN (K6)
(top view)
* Distance of 1.6mm from case for 10 seconds.
Thermal Characteristics
Package Value
8-Lead DFN (K6) θ
8-Lead SOIC (TG) θ
Note:
1.0oz, 4-layer, 3”x4” PCB
= 44OC/W
ja
= 130OC/W
ja
8-Lead SOIC (TG)
(top view)
Package Marking
Package may or may not include the following marks: Si or
8-Lead DFN (K6)
Package may or may not include the following marks: Si or
8-Lead SOIC (TG)
2
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TC6320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
R
GEN
Input
Pulse
Genera to
r
V
DD
R
L
D.U. T
OUTPUT
10
V
0V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON)
t
(OFF)
10%
90
%
90
%
10
%
90
%
10
%
N-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
ΔV
VZ
GS(th)
GS(th)
R
Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 2.0mA
DSS
Gate threshold voltage 1.0 - 2.0 V VGS = VDS, ID = 1.0mA
Change in V
Gate-to-source shunt resistor 10 - 50 KΩ I
GS
Gate-to-source Zener voltage 13.2 - 25 V I
GS
with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA
GS(th)
= 100µA
GS
= 2.0mA
GS
- - 10.0 µA VDS = Max rating, VGS = 0V
I
DSS
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
C
C
OSS
C
RSS
t
d(ON)
t
t
d(OFF)
t
V
t
Notes:
1.
2.
Zero gate voltage drain current
- - 1.0 mA
1.0 - -
On-state drain current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
VGS = 4.5V, VDS = 25V
A
2.0 - - VGS = 10V, VDS = 25V
Static drain-to-source on-state resistance
- - 8.0
Ω
VGS = 4.5V, ID = 150mA
- - 7.0 VGS = 10V, ID = 1.0A
Change in R
Forward transconductance 400 - - mmho VDS = 25V, ID = 500mA
FS
Input capacitance - - 110
ISS
Common source output capacitance - - 60
Reverse transfer capacitance - - 23
with temperature - - 1.0 %/OC VGS = 4.5V, ID =150mA
DS(ON)
VGS = 0V,
pF
VDS = 25V,
f = 1.0MHz
Turn-on delay time - - 10
Rise time - - 15
r
ns
Turn-off delay time - - 20
Fall time - - 15
f
Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 500mA
SD
Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA
rr
All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
VDD =25V,
ID = 1.0A,
R
= 25Ω
GEN
N-Channel Switching Waveforms and Test Circuit
3
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TC6320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
R
GEN
Input
Puls
e
Generato
r
V
DD
R
L
D.U. T
OUTPUT
0V
-10V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON)
t
(OFF)
90%
10%
90
%
10
%
10
%
90
%
P-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
ΔV
VZ
GS(th)
GS(th)
R
Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA
DSS
Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA
Change in V
Gate-to-source shunt resistor 10 - 50 KΩ I
GS
Gate-to-source Zener voltage 13.2 - 25 V I
GS
with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA
GS(th)
= 100µA
GS
= -2mA
GS
- - -10 µA VDS = Max rating, VGS = 0V
I
DSS
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
C
C
OSS
C
RSS
t
d(ON)
t
t
d(OFF)
t
V
t
Notes:
1.
2.
Zero gate voltage drain current
- - -1.0 mA
-1.0 - -
On-state drain current
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125OC
VGS = -4.5V, VDS = -25V
A
-2.0 - - VGS = -10V, VDS = -25V
Static drain-to-source on-state resistance
- - 10
Ω
VGS = -4.5V, ID = -150mA
- - 8.0 VGS = -10V, ID = -1.0A
Change in R
Forward transconductance 400 - - mmho VDS = -25V, ID = -500mA
FS
Input capacitance - - 200
ISS
Common source output capacitance - - 55
Reverse transfer capacitance - - 30
with temperature - - 1.0 %/OC VGS = -10V, ID =-200mA
DS(ON)
VGS = 0V,
pF
VDS = -25V,
f = 1.0MHz
Turn-on delay time - - 10
Rise time - - 15
r
ns
Turn-off delay time - - 20
Fall time - - 15
f
Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -500mA
SD
Reverse recovery time - 300 - ns VGS = 0V, ISD = -500mA
rr
All D.C. parameters 100% tested at 25°C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
VDD = -25V,
ID = -1.0A,
R
= 25Ω
GEN
P-Channel Switching Waveforms and Test Circuit
4
Page 5
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
8-Lead DFN Package Outline (K6)
Seating
Plane
Top View
Side View
Bottom View
A
A1
D
E
D2
e
b
E2
A3
L
L1
Vi
ew B
View B
Note 1
(Index Area
D/2 x E/2)
Note 3
Note 2
Note 1
(Index Area
D/2 x E/2)
1
1
8
8
Note 1
E2
D2
K1
θ
K1/2
4.00x4.00mm body, 0.90mm height (max), 1.00mm pitch (dual pad)
TC6320
Notes:
1.
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
2.
The inner tip of the lead may be either rounded or square.
3.
Symbol A A1 A3 b D D2 E E2 e K1 L L1 θ
MIN 0.80 0.00
Dimension
(mm)
NOM 0.85 - 0.30 4.00 1.45 4.00 1.45 0.50 - -
0.20
REF
0.25 3.90 1.35 3.90 1.35
1.00
BSC
0.50
REF
0.40 0.00 0
MAX 0.90 0.05 0.35 4.10 1.55 4.10 1.55 0.60 0.15 14
Drawings not to scale
Supertex Doc. #: DSPD-8DFNK64x4P100, Version B101008
O
O
5
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Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com
.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8-Lead SOIC (Narrow Body) Package Outline (TG)
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
E
E1
D
e
b
A
A2
A1
Seating
Plane
A
A
Top View
Side View
View B
View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
TC6320
Note:
This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
1.
an embedded metal marker; or a printed indicator.
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
Dimension
(mm)
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version H101708.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15
information go to http://www.supertex.com/packaging.html.)
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
Doc.# DSFP-TC6320
C122208
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