Page 1
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
N- and P-Channel
GP
SP
GN
SN
DP
DP
DN
DN
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YYWW
C6215
L L L L
Enhancement-Mode Dual MOSFET
TC6215
Features
Back to back gate-source Zener diodes
►
Guaranteed R
►
Low threshold
►
Low on-resistance
►
Independent N- and P-channels
►
Electrically isolated N- and P-channels
►
Low input capacitance
►
Fast switching speeds
►
Free from secondary breakdowns
►
Low input and output leakage
►
at 4.0V gate drive
DS(ON)
Applications
High voltage pulsers
►
Amplifiers
►
Buffers
►
Piezoelectric transducer drivers
►
General purpose line drivers
►
Logic level interfaces
►
Ordering Information
General Description
The Supertex TC6215 consists of high voltage, low threshold N-channel
and P-channel MOSFETs in an 8-Lead SOIC (TG) package. Both
MOSFETs have integrated back to back gate-source Zener diode clamps
and guaranteed R
be driven directly with standard 5.0V CMOS logic.
These low threshold enhancement-mode (normally-off) transistors utilize
an advanced vertical DMOS structure and Supertex’s well-proven silicongate manufacturing process. This combination produces devices with the
power handling capabilities of bipolar transistors and with the high input
impedance and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, these devices are free from thermal
runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range of
switching and amplifying applications where very low threshold voltage,
high breakdown voltage, high input impedance, low input capacitance,
and fast switching speeds are desired.
ratings down to 4.0V gate drive allowing them to
DS(ON)
Device
Package Option BV
8-Lead SOIC
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
N-Channel
(V)
DSS
/BV
DGS
P-Channel
(V)
R
DS(ON)
N-Channel
(Ω)
(Max)
P-Channel
TC6215 TC6215TG-G 150 -150 4.0 7.0
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Pin Configuration
Parameter Value
Drain-to-source voltage BV
Drain-to-gate voltage BV
DSS
DGS
Gate-to-source voltage ±20V
Operating and storage temperature -55°C to + 150°C
Soldering temperature
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
*
300°C
Product Marking
Package may or may not include the following marks: Si or
(Ω)
8-Lead SOIC (TG)
(top view)
8-Lead SOIC (TG)
Page 2
TC6215
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
R
GEN
Input
Puls
e
Generato
r
V
DD
R
L
D.U.T.
OUTPUT
10V
0V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON)
t
(OFF)
10%
90
%
90
%
10%
90%
10%
N-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
ΔV
VZ
GS(th)
GS(th)
Drain-to-source breakdown voltage 150 - - V VGS = 0V, ID = 1.0mA
DSS
Gate threshold voltage 1.0 - 2.0 V VGS = VDS, ID =1.0mA
Change in V
Gate-source back to back Zener voltage ±14 - ±25 V IGS = ±1.0mA
GS
with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA
GS(th)
- - 5.0 µA VGS = 0V, VDS = Max Rating
I
I
D(ON)
R
DS(ON)
DSS
Zero gate voltage drain current
On-state drain current
Static drain-to-source on-state resistance
- - 1.0 mA
- 2.0 -
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
VGS = 4.5V, VDS = 25V
A
- 3.8 - VGS = 10V, VDS = 25V
- - 4.0
- - 5.0 VGS = 5.0V, ID = 2.0A
Ω
VGS = 4.0V, ID = 0.5A
- - 4.0 VGS = 10V, ID = 2.0A
ΔR
C
C
C
t
t
d(OFF)
Notes:
1.
2.
DS(ON)
G
ISS
OSS
RSS
d(ON)
t
t
V
SD
t
rr
Change in R
Forward transconductance 560 - - mmho VDS = 10V, ID = 0.5A
FS
Input capacitance - 120 -
Common source output capacitance - 33 -
Reverse transfer capacitance - 11 -
with temperature - - 1.0 %/OC VGS = 5.0V, ID = 2.0A
DS(ON)
VGS = 0V,
pF
VDS = 25V,
f = 1.0MHz
Turn-on delay time - 2.5 -
Rise time - 2.3 -
r
Turn-off delay time - 17.2 -
Fall time - 11.3 -
f
ns
V
DD
ID = 1.0A,
R
GEN
Diode forward voltage drop - - 1.4 V VGS = 0V, ISD = 0.5A
Reverse recovery time - 90 - ns VGS = 0V, ISD = 0.5A
All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
All AC parameters sample tested.
= 25V,
= 25Ω
N-Channel Switching Waveforms and Test Circuit
2
Page 3
TC6215
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
R
GEN
Input
Puls
e
Generato
r
V
DD
R
L
D.U.T.
OUTPUT
0V
-10V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON
)
t
(OFF)
90%
10
%
90%
10
%
10
%
90%
P-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
ΔV
VZ
GS(th)
GS(th)
Drain-to-source breakdown voltage -150 - - V VGS = 0V, ID = -1.0mA
DSS
Gate threshold voltage -1.0 - -2.0 V VGS = VDS, ID =-1.0mA
Change in V
Gate-source back to back Zener voltage ±14 - ±25 V IGS = ±1.0mA
GS
with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA
GS(th)
- - -5.0 µA VGS = 0V, VDS = Max Rating
I
I
D(ON)
R
DS(ON)
DSS
Zero gate voltage drain current
On-state drain current
Static drain-to-source on-state resistance
- - -1.0 mA
- -1.5 -
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
VGS = -4.5V, VDS = -25V
A
- -3.0 - VGS = -10V, VDS = -25V
- - 7.5
- - 9.0 VGS = -5.0V, ID = -1.0A
Ω
VGS = -4.0V, ID = -0.25A
- - 7.0 VGS = -10V, ID = -2.0A
ΔR
C
C
C
t
t
d(OFF)
Notes:
1.
2.
DS(ON)
G
ISS
OSS
RSS
d(ON)
t
t
V
SD
t
rr
Change in R
Forward transconductance 290 - - mmho VDS = -10V, ID = -0.25A
FS
Input capacitance - 127 -
Common source output capacitance - 29 -
Reverse transfer capacitance - 9.0 -
with temperature - - 1.0 %/OC VGS = -5.0V, ID = -0.25A
DS(ON)
VGS = 0V,
pF
VDS = -25V,
f = 1.0MHz
Turn-on delay time - 2.4 -
V
Rise time - 2.3 -
r
Turn-off delay time - 16.2 -
Fall time - 11.1 -
f
ns
= -25V,
DD
ID = -1.0A,
R
GEN
Diode forward voltage drop - - -1.4 V VGS = 0V, ISD = -0.25A
Reverse recovery time - 80 - ns VGS = 0V, ISD = -0.25A
All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
All AC parameters sample tested.
= 25Ω
P-Channel Switching Waveforms and Test Circuit
3
Page 4
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Block Diagram
SN
GN
SP
GP
1
2
3
4
DP
DP
DN
DN
6
7
8
5
N-Channel
P-Channel
P-Channel Output Characteristics
-4.0
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.
0
-5
0-45-40-35-30-25-20-15-10-50
VDS (volts)
I
D
(amperes)
VGS=-10V
VGS=-8V
VGS=-7V
VGS=-6V
VGS=-5V
VGS=-4V
VGS=-3V
VGS=-2V
P-Channel Saturation Characteristics
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
-0.2
0.
0
-1
0-9-8-7-6-5-4-3-2-10
VDS (volts)
I
D
(amperes)
VGS=-10V
VGS=-8V
VGS=-6V
VGS=-5V
VGS=-4V
VGS=-3V
VGS=-2V
N-Channel Output Characteristics
0.0
0.
5
1.
0
1.
5
2.
0
2.
5
3.
0
3.5
4.
0
4.
5
0 5 10 15 20 25 30 35 40 45 50
VDS (volts)
I
D
(amperes)
VGS=10V
VGS=8V
VGS=7V
VGS=6V
VGS=5V
VGS=4V
VGS=3V
VGS=2V
N-Channel Saturation Characteristics
0.0
0.
5
1.
0
1.
5
2.
0
2.
5
3.
0
3.
5
4.
0
0 1 2 3 4 5 6 7 8 9 1
0
VDS (volts)
I
D
(amperes)
VGS=10V
VGS=8V
VGS=6V
VGS=5V
VGS=4V
VGS=3V
VGS=2V
Typical Performance Curves
TC6215
8-Lead SOIC
(top view)
4
Page 5
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com
.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8-Lead SOIC (Narrow Body) Package Outline (TG)
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
E
E1
D
e
b
A
A2
A1
Seating
Plane
A
A
Top View
Side View
View B
View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
TC6215
Note:
This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
1.
an embedded metal marker; or a printed indicator.
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
Dimension
(mm)
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version H101708.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15
information go to http://www.supertex.com/packaging.html.)
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
Doc.# DSFP-TC6215
A122208
5
O
0
O
5
O
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