Page 1
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
TC2320
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YYW W
C2320
L LL L
GP
SP
GN
SN
DP
DP
DN
DN
N- and P-Channel Enhancement-Mode Dual MOSFET
Features
Low threshold
►
Low on-resistance
►
Low input capacitance
►
Fast switching speeds
►
Freedom from secondary breakdown
►
Low input and output leakage
►
Independent, electrically isolated N- and P-channels
►
Applications
Medical ultrasound transmitters
►
High voltage pulsers
►
Amplifiers
►
Buffers
►
Piezoelectric transducer drivers
►
General purpose line drivers
►
► Logic level interface
Ordering Information
8-Lead SOIC (Narrow Body)
Device
4.90x3.90mm body,
1.75mm height (max)
1.27mm pitch
General Description
The Supertex TC2320 consists of a high voltage, low
threshold N- and P-channel MOSFET in an 8-Lead SOIC
package. This low threshold enhancement-mode (normallyoff) transistor utilizes an advanced vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all
MOS structures, this device is free from thermal runaway
and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
R
BV
/BV
DSS
DGS
(V)
N-Channel P-Channel N-Channel P-Channel
DS(ON)
(max)
(Ω)
TC2320 TC2320TG-G 200 -200 7.0 12
-G indicates package is RoHS compliant (‘Green’)
Pin Configuration
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BV
Drain-to-gate voltage BV
Gate-to-source voltage ±20V
Operating and storage temperature -55°C to +150°C
Soldering temperature* +300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
DSS
DGS
8-Lead SOIC (TG)
Product Marking
Package may or may not include the following marks: Si or
8-Lead SOIC (TG)
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TC2320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
90%
10%
90%
90%
10%
10%
PULSE
GENERATO
R
V
DD
R
L
OUTPUT
D.U.T
.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
F
t
r
INPUT
INPUT
OUTPUT
10V
V
DD
R
GEN
0V
0V
N-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
ΔV
GS(th)
GS(th)
I
GSS
Drain-to-source breakdown voltage 200 - - V VGS = 0V, ID = 100µA
DSS
Gate threshold voltage 0.6 - 2.0 V VGS = VDS, ID = 1.0mA
Change in V
with temperature - - -4.5 mV/OC VGS = VDS, ID = 1.0mA
GS(th)
Gate body leakage - - 100 nA VGS = ±20V, VDS = 0V
- - 1.0 µA VGS = 0V, VDS = 100V
I
DSS
Zero gate voltage drain current
- - 10.0 µA
- - 1.0 mA
0.6 - -
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
C
C
OSS
C
RSS
t
d(ON)
t
t
d(OFF)
t
V
t
Notes:
1.
2.
On-state drain current
1.2 - - VGS = 10V, VDS = 25V
Static drain-to-source on-state
resistance
Change in R
Forward transconductance 150 - - mmho VDS = 25V, ID = 200mA
FS
Input capacitance - - 110
ISS
with temperature - - 1.0 %/OC VGS = 4.5V, ID =150mA
DS(ON)
- - 8.0
- - 7.0 VGS = 10V, ID = 1.0A
Common source output capacitance - - 60
Reverse transfer capacitance - - 23
Turn-on delay time - - 20
Rise time - - 15
r
Turn-off delay time - - 25
Fall time - - 25
f
Diode forward voltage drop - - 1.8 V VGS = 0V, ISD = 200mA
SD
Reverse recovery time - 300 - ns VGS = 0V, ISD = 200mA
rr
All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
Ω
pF
ns
VGS = 0V,
VDS = Max rating
VGS = 0V, TA = 125OC
VDS = 0.8 Max Rating
VGS = 4.5V, VDS = 25V
A
VGS = 4.5V, ID = 150mA
VGS = 0V,
VDS = 25V,
f = 1.0MHz
VDD =25V,
ID = 150mA,
R
= 25Ω
GEN
N-Channel Switching Waveforms and Test Circuit
2
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TC2320
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
90%
10%
90%
90%
10%
10%
PULSE
GENERATO
R
V
DD
R
L
Output
D.U.T
.
t
(ON)
t
d(ON)
t
(OFF)
t
d(OFF)
t
F
t
r
INPUT
INPUT
OUTPUT
0V
V
DD
R
GEN
0V
-10V
P-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
ΔV
GS(th)
GS(th)
I
GSS
Drain-to-source breakdown voltage -200 - - V VGS = 0V, ID = -2.0mA
DSS
Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID = -1.0mA
Change in V
with temperature - - 4.5 mV/OC VGS = VDS, ID = -1.0mA
GS(th)
Gate body leakage - - -100 nA VGS = ±20V, VDS = 0V
- - -10 µA VGS = 0V, VDS = Max rating
I
DSS
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
C
C
OSS
C
RSS
t
d(ON)
t
t
d(OFF)
t
V
t
Notes:
1.
2.
Zero gate voltage drain current
- - -1.0 mA
-0.25 -0.7 -
On-state drain current
VGS = 0V, TA = 125OC,
VDS = 0.8 Max Rating
VGS = -4.5V, VDS = -25V
A
-0.75 -2.1 - VGS = -10V, VDS = -25V
Static drain-to-source on-state
resistance
Change in R
Forward transconductance 100 250 - mmho VDS = -25V, ID = -200mA
FS
Input capacitance - 75 125
ISS
with temperature - - 1.7 %/OC VGS = -10V, ID =-200mA
DS(ON)
Common source output capacitance - 20 85
- 10 15
Ω
- 8.0 12 VGS = -10V, ID = -200mA
pF
Reverse transfer capacitance - 10 35
VGS = -4.5V, ID = -100mA
VGS = 0V,
VDS = -25V,
f = 1.0MHz
Turn-on delay time - - 10
Rise time - - 15
r
ns
Turn-on delay time - - 20
Fall time - - 15
f
Diode forward voltage drop - - -1.8 V VGS = 0V, ISD = -0.5A
SD
Reverse recovery time - 300 - ns VGS = 0V, ISD = -0.5A
rr
All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
All A.C. parameters sample tested.
VDD = -25V,
ID = -0.75A,
R
= 25Ω
GEN
P-Channel Switching Waveforms and Test Circuit
3
Page 4
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com
.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8-Lead SOIC (Narrow Body) Package Outline (TG)
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
E
E1
D
e
b
A
A2
A1
Seating
Plane
A
A
Top View
Side View
View B
View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
TC2320
Note:
This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier;
1.
an embedded metal marker; or a printed indicator.
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
Dimension
(mm)
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version H101708.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15
information go to http://www.supertex.com/packaging.html.)
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
Doc.# DSFP-TC2320
B122208
4
O
0
O
5
O
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