Page 1
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
N- and P-Channel
GP
SP
GN
SN
DP
DP
DN
DN
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YY WW
C1550
L L LL
Enhancement-Mode Dual MOSFET
TC1550
Features
500V breakdown voltage
►
Independent N- and P-channels
►
Electrically isolated N- and P-channels
►
Low input capacitance
►
Fast switching speeds
►
Free from secondary breakdowns
►
Low input and output leakage
►
General Description
The Supertex TC1550 consists of a high voltage N-channel and
P-channel MOSFET in an 8-Lead SOIC package. This is an
enhancement-mode (normally-off) transistor utilizing an advanced
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces a device with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inherent
in MOS devices. Characteristic of all MOS structures, this device
Applications
is free from thermal runaway and thermally induced secondary
breakdown.
High voltage pulsers
►
Amplifiers
►
Buffers
►
Piezoelectric transducer drivers
►
General purpose line drivers
►
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Ordering Information
R
DS(ON)
(Max)
Device
Package Option BV
8-Lead SOIC
4.90x3.90mm body
1.75mm height (max)
1.27mm pitch
N-Channel
(V)
DSS
/BV
DGS
P-Channel
(V)
N-Channel
(Ω)
TC1550 TC1550TG-G 500 -500 60 125
-G indicates package is RoHS compliant (‘Green’)
P-Channel
(Ω)
Absolute Maximum Ratings
Parameter Value
Drain-to-source voltage BV
Drain-to-gate voltage BV
Gate-to-source voltage ±20V
Operating and storage temperature -55°C to + 150°C
Soldering temperature
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
*
300°C
DSS
DGS
Pin Configuration
8-Lead SOIC (TG)
(top view)
Product Marking
8-Lead SOIC (TG)
Page 2
TC1550
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
R
GEN
Input
Puls
e
Generato
r
V
DD
R
L
D.U.T.
OUTPUT
10V
0V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON)
t
(OFF)
10%
90
%
90
%
10
%
90%
10%
N-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
ΔV
GS(th)
GS(th)
I
GSS
Drain-to-source breakdown voltage 500 - - V VGS = 0V, ID = 1.0mA
DSS
Gate threshold voltage 2.0 - 4.0 V VGS = VDS, ID =1.0mA
Change in V
with temperature - -3.8 -5.0 mV/OC VGS = VDS, ID = 1.0mA
GS(th)
Gate body leakage current - - 100 nA VGS = ±20V, VDS = 0V
- - 10 µA VGS = 0V, VDS = Max Rating
I
I
D(ON)
R
ΔR
G
C
C
C
t
t
d(OFF)
V
Notes:
1.
2.
DSS
DS(ON)
DS(ON)
ISS
OSS
RSS
d(ON)
t
t
SD
t
rr
Zero gate voltage drain current
On-state drain current
- - 1.0 mA
- 100 mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
VGS = 5.0V, VDS = 25V
150 350 - VGS = 10V, VDS = 25V
Static drain-to-source
on-state resistance
Change in R
Forward transconductance 50 100 - mmho VDS = 25V, ID =50mA
FS
with temperature - 1.0 1.7 %/OC VGS = 10V, ID = 50mA
DS(ON)
- 45 -
Ω
- 40 60 VGS = 10V, ID = 50mA
Input capacitance - 45 55
Common source output capacitance - 8.0 10
pF
Reverse transfer capacitance - 2.0 5.0
VGS = 5.0V, ID = 50mA
VGS = 0V,
VDS = 25V,
f = 1.0MHz
Turn-on delay time - - 10
Rise time - - 15
r
Turn-off delay time - - 10
Fall time - - 10
f
ns
V
DD
ID = 150mA,
R
GEN
Diode forward voltage drop - 0.8 - V VGS = 0V, ISD = 500mA
Reverse recovery time - 300 - ns VGS = 0V, ISD = 500mA
All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
All AC parameters sample tested.
= 25V,
= 25Ω
N-Channel Switching Waveforms and Test Circuit
2
Page 3
TC1550
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
R
GEN
Input
Puls
e
Generato
r
V
DD
R
L
D.U.T.
OUTPUT
0V
-10V
0V
V
DD
t
d(OFF)
Input
Output
t
r
t
f
t
d(ON)
t
(ON
)
t
(OFF)
90%
10
%
90
%
10
%
10
%
90
%
P-Channel Electrical Characteristics (T
= 25°C unless otherwise specified)
A
Sym Parameter Min Typ Max Units Conditions
BV
V
ΔV
GS(th)
I
GSS
GS(th)
Drain-to-source breakdown voltage -500 - - V VGS = 0V, ID = -1.0mA
DSS
Gate threshold voltage -2.0 - -4.5 V VGS = VDS, ID = -1.0mA
Change in V
with temperature - 3.5 6.0 mV/OC VGS = VDS, ID = -1.0mA
GS(th)
Gate body leakage current - - 100 nA VGS = ±20V, VDS = 0V
- - -10 µA VGS = 0V, VDS = Max Rating
I
I
D(ON)
R
DS(ON)
ΔR
G
C
C
C
t
t
d(OFF)
V
Notes:
1.
2.
DSS
DS(ON)
ISS
OSS
RSS
d(ON)
t
t
SD
t
rr
Zero gate voltage drain current
On-state drain current
- - -1.0 mA
- -90 mA
VDS = 0.8 Max Rating,
VGS = 0V, TA = 125°C
VGS = -5.0V, VDS = -25V
-100 -240 - VGS = -10V, VDS = -25V
Static drain-to-source
on-state resistance
Change in R
Forward transconductance 25 40 - mmho VDS = -25V, ID = -10mA
FS
with temperature - 0.85 - %/OC VGS = -10V, ID = -10mA
DS(ON)
- 85 -
Ω
- 80 125 VGS = -10V, ID = -10mA
Input capacitance - 40 70
Common source output capacitance - 10 20
pF
Reverse transfer capacitance - 3.0 10
VGS = -5.0V, ID = -5.0mA
VGS = 0V,
VDS = -25V,
f = 1.0MHz
Turn-on delay time - 5.0 10
V
Rise time - 8.0 10
r
Turn-off delay time - 8.0 15
Fall time - 5.0 16
f
ns
= -25V,
DD
ID = -100mA,
R
GEN
Diode forward voltage drop - -0.8 -1.5 V VGS = 0V, ISD = -100mA
Reverse recovery time - 200 - ns VGS = 0V, ISD = -100mA
All DC parameters 100% tested at 25°C unless otherwise stated. (Pulsed test: 300µs pulse at 2% duty cycle.)
All AC parameters sample tested.
= 25Ω
P-Channel Switching Waveforms and Test Circuit
3
Page 4
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
Typical Application Circuit
VDD2
V
H
VDD1
Supertex
MD1213K
6
V
L
VSS2VSS1GND
OUTA
OUTB
INA
INB
OE
0.47µF
+12V
3.3V CMOS
Logic Input
s
Supertex
TC1550TG
+250
V
-250
V
Piezoelectri
c
Transducer
10n
F
250V
10nF
250V
15V
15V
SN
GN
SP
GP
1
2
3
4
DP
DP
DN
DN
6
7
8
5
N-Channel
P-Channel
TC1550
Block Diagram
4
Page 5
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com
.
©2008 All rights reserved. Unauthorized use or reproduction is prohibited.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
8-Lead SOIC (Narrow Body) Package Outline (TG)
1
8
Seating
Plane
Gauge
Plane
L
L1
L2
E
E1
D
e
b
A
A2
A1
Seating
Plane
A
A
Top View
Side View
View B
View B
θ1
θ
Note 1
(Index Area
D/2 x E1/2)
View A-A
h
h
Note 1
4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
TC1550
Note:
This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 Identifier can be:
1.
a molded mark/identifier; an embedded metal marker; or a printed indicator.
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
MIN 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80*
Dimension
(mm)
JEDEC Registration MS-012, Variation AA, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
Drawings are not to scale.
Supertex Doc. #: DSPD-8SOLGTG, Version G090808.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
NOM - - - - 4.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8O15
information go to http://www.supertex.com/packaging.html.)
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
Doc.# DSFP-TC1550
A091608
5
O
0
O
5
O
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