Datasheet TAS5261DKDRG4, TAS5261 Datasheet (Texas Instruments)

TM

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PVDD Supply Voltage − V

0

30

60

90

120

150

180

210

240

270

300

330

0 5 10 15 20 25 30 35 40 45 50

TC = 75°C
THD+N at 10%

P

O

− Output Power − W

G001

8 Ω

6 Ω

4 Ω

315-W Mono BTL Digital Amplifier Power Stage

FEATURES

• Total Output Power
– 125 W Into 8 Ω at <0.09% THD+N
– 220 W Into 6 Ω at 10% THD+N
– 315 W Into 4 Ω at 10% THD+N

• 110-dB SNR (A-Weighted with TAS5518
modulator)

• Supports Pulse-Width Modulation (PWM)
Frame Rates of 192 kHz to 384 kHz

• Resistor-Programmable Current Limit

• Integrated Self-Protection Circuit Including:

– Under Voltage Protection
– Over Temperature Warning and Error
– Over Load Protection
– Short Circuit (OC) Protection
– PWM Activity Dectector

• Power-On Reset (POR) to Eliminate System
Power-Supply Sequencing

• Thermally-Enhanced Package DKD (36-pin
PSOP3)

• EMI Compliant When Used With
Recommended System Design

• Error Reporting 3.3-V and 5-V Compliant

TAS5261

SLES188 – AUGUST 2006

The TAS5261 has complete protection circuitry
integrated on chip, safeguarding the device and
speakers against fault conditions that could damage
the system. These protection features are
short-circuit protection, overcurrent protection,
undervoltage protection, and a loss of pulse-width
modulation (PWM) input signal (PWM Activity
Detector).

A power-on reset (POR) circuit is used to eliminate
power-supply sequencing that is normally required
for most H-bridge designs.

OUTPUT POWER

vs

PVDD_x SUPPLY VOLTAGE

APPLICATIONS

• AV Receivers

• DVD Receivers

• Mini/Micro Component Systems

• Home Theater Systems

DESCRIPTION

The TAS5261 is a high-performance, integrated
mono digital amplifier power stage designed to drive
4- Ω to 8- Ω speakers with low harmonic distortion.
This system requires only a simple, passive
demodulation filter to deliver high-quality,
high-efficiency audio amplification.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2006, Texas Instruments Incorporated

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18

36
35
34
33
32

31
30
29
28
27
26
25
24
23
22

21
20
19

BST_A

GVDD_A

OTW

SD

RESET

PWM_A

OC_ADJ

GND
AGND
VREG

M3
M2

M1

PWM_B

VDD

GND

GVDD_B

BST_B

PVDD_A
PVDD_A
PVDD_A
PGND
PGND
PGND
OUT_A
OUT_A
OUT_A
OUT_B
OUT_B
OUT_B
PGND
PGND
PGND
PVDD_B
PVDD_B
PVDD_B

DKDPACKAGE

(TOP VIEW)

P0018-02

TAS5261

SLES188 – AUGUST 2006

DEVICE INFORMATION

The TAS5261 is available in a thermally-enhanced 36-pin PSOP3 PowerPAD™ package. The heat slug is
located on the top side of the device for convenient thermal coupling to a heat sink.

2

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DISSIPATION RATINGS

PARAMETER CONDITION TYPICAL (DKD)

R

θ JC

R

θ JC

BTL channel (four transistors) 0.6 ° C/W

One transistor 2.38 ° C/W

Pad area 80 mm

Protection Mode

Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.

Table 1. Protection Modes

MODE PINS

(1)

M3

M2 M1

0 0 0 Full protection (default)
0 0 1 Reserved
0 1 0 OC latching mode
0 1 1 Reserved

(1) M3 is reserved and always should be connected to board GND.

PROTECTION MODE

TAS5261

SLES188 – AUGUST 2006

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TAS5261

SLES188 – AUGUST 2006

TERMINAL FUNCTIONS

TERMINAL

NAME PIN NO.

AGND 9 I Analog ground
BST_A 1 P Bootstrap, A side
BST_B 18 I Bootstrap, B side
GND 8, 16 I Power ground
GVDD_A 2 P Gate-drive voltage supply, A side
GVDD_B 17 I Gate-drive voltage supply, B side
M1 13 I Mode-selection 1 (LSB)
M2 12 I Mode-selection 2 (MSB)
M3 11 I Reserved
OC_ADJ 7 I Overcurrent threshold programming
OTW 3 O Overtemperature warning. Open drain, active low.
OUT_A 28, 29, 30 O Output, half-bridge A
OUT_B 25, 26, 27 O Output, half-bridge B

PGND P Power ground
PWM_A 6 I PWM for half-bridge A

PWM_B 14 I PWM Input for half-bridge B
PVDD_A 34, 35, 36 P PVDD supply for half-bridge A
PVDD_B 19, 20, 21 P PVDD supply for half-bridge B
RESET 5 I Reset. Active low.
SD 4 O Shutdown. Open drain, active low.
VDD 15 I Input power supply
VREG 10 O Internal voltage regulator

22, 23, 24, 31,

32, 33

I/O DESCRIPTION

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B0101-01

PVDD(0–50V)

Mono

BTL

H-Bridge

Hardwire

Mode

Control

Hardwire

Mode

Control

M1

M1

M2

M2

M3

M3

System

Microcontroller

RESET_H-Bridge

SD

OTW

OTW

SD

RESET

Hardwire

Over-

current

Limit

Hardwire

Over-

current

Limit

PVDD

Power-Supply

Decoupling

PVDD

Power-Supply

Decoupling

GVDD,VDD,

andVREG

Power-Supply

Decoupling

GVDD,VDD,

andVREG

Power-Supply

Decoupling

6

6

6

6

2

2

GVDD(12V)andVDD(12V)

GVDD(12V)andVDD(12V)

GND

GND

PVDD(0–50V)

System

Power

Supplies

50V

12V

GND

AC

Bootstrap

Capacitors

Bootstrap

Capacitors

BST_A

BST_A

BST_B

BST_B

R2

L2

PWM_B

RESET

Shutdown

Overtemp_warning

R1

L1

TAS55XX

Left

Output

Right

Output

PWM_A

H-Bridge

Output

H-Bridge

Output

PVDD_A,B

VDD

VREG

GND

GND

GVDD_A,B

GND_A,B

OC_ADJ

Mono

BTL

H-Bridge

PWM_B

RESET

Shutdown

Overtemp_warning

PWM_A

PVDD_A,B

VDD

VREG

GND

GND

GVDD_A,B

GND_A,B

OC_ADJ

2nd-Order

L-COutput

Filterfor

Each

H-Bridge

2nd-Order

L-COutput

Filterfor

Each

H-Bridge

OUT_A

OUT_A

OUT_B

OUT_B

4–8

(3 Min)

W

W

4–8

(3 Min)

W

W

TAS5261

SLES188 – AUGUST 2006

Figure 1. Typical System Block Diagram

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TEMP

SENSE

M1

M2

AGND

OC_

ADJ

VREG VREG

VDD

GVDD

_B

M3

P

OWER-UP

R

ESET

U

VP

GND

PWM

_B

OUT_B

(x3)

PGND

(x3)

PVDD_B

(x3)

BST_B

TIMING

CONTROL

GATE-DRIVECONTROL

PWM

RECEIVER

OVER-LOAD

PROT

.

GVDD

_A

PWM

ACTIVITY

DETECTOR

CB

3C

GVDD

_B

CURRENT

SENSE

GVDD

_A

PWM

_A

OUT_A(

x3)

PGND

(x3)

PVDD_A(

x3)

BST_A

TIMING

CONTROL

CONTROL GATE-DRIVE

PWM

RECEIVER

PROTECTION & I/O LOGIC

OTW

SD

RESET

TAS5261

SLES188 – AUGUST 2006

Figure 2. Functional Block Diagram

6

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ORDERING INFORMATION

T

A

0 ° C to 70 ° C TAS5261DKD 36-pin PSOP3

PACKAGE DESCRIPTION

TAS5261

SLES188 – AUGUST 2006

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

VDD to AGND –0.3 13.2 V
GVDD_x to AGND –0.3 13.2 V
PVDD_x to PGND_x
OUT_x to PGND_x
BST_x to PGND_x
BST_x to GVDD_x
VREG to AGND –0.3 4.2 V
PGND_x to GND –0.3 0.3 V
PGND_x to AGND –0.3 0.3 V
GND to AGND –0.3 0.3 V
PWM_x, OC_ADJ, M1, M2, M3 to AGND –0.3 4.2 V
RESET, SD, OTW to AGND –0.3 7 V
Maximum continuous sink current ( SD, OTW) 9 mA
Maximum operating junction temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260 ° C
Minimum pulse duration, low – minimum pulse width must be ensured by the PWM processor 50 ns

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are only stress

ratings, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.

(2)

(2)
(2)
(2)

J

stg

–0.3 71 V
–0.3 71 V
–0.3 79.7 V
–0.3 66.5 V

0 150 ° C

–65 150 ° C

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TAS5261

SLES188 – AUGUST 2006

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

PVDD_x Half-bridge supply voltage 0 50 52.5 V
GVDD_x Gate-drive power supply 10.8
VDD Digital regulator supply voltage 10.8
R

L

R

L

L

DEM

f

S

t

(low)

C

BS

R

BS

RC

D

CLMP

D

TVS

C

PVDD

R

AGND

Resistive load impedance, bridge-tied load (BTL) 4-16 Ω
Resistive load impedance, BTL, R

= 22k Ω , PVDD = 50V, (no current limiting) 3 Ω

OC

Minimum output filter inductance under both operating and short-circuit conditions,
with appropriate OC_ADJ resistor value

PWM frame rate 192 384 kHz
Minimum low-state pulse duration per PWM frame, noise shaper enabled 50 ns
Bootstrap capacitor, selected value supports fs= 192 kHz to 384 kHz 33 nF
Bootstrap series resistor - 1/4 W 1.5 Ω

Bootstrap snubber - 1/4 W

BS

Ultra-Fast Recovery Clamping Diode, Average forward current = 1A, Maximum
repetitive reverse voltage = 200V (ES1D, mfg:Fairchild)

Transient Voltage Suppressor, 600W @ 1mS (P6SMB62AT3, mfg: ON Semiconductor) 62 V
PVDD Close Decoupling Capacitor, two capacitors 100 nF

AGND resistor - 1/4 W 3.3 Ω
R Optional external pullup resistor to +3.3V or +5 V for SD and OTW 3.3 4.7 k Ω
T

J

Junction temperature 0 125 ° C

(1) GVDD operation below 10.8 V significantly reduces efficiency of the output MOSFET stage and requires a larger heatsink. For the

purpose of noise margin, the UVP level is set lower to provide an increased noise margin, however, TI recommends a nominal dc
voltage of 12 V for GVDD.

(1)
(1)

12 13.2 V
12 13.2 V

5 10 µ H

4.7 Ω

470 pF

15 nS

AUDIO CHARACTERISTICS

Audio frequency = 1 kHz, PVDD_x = 50 V, GVDD_x = 12 V, VDD = 12 V, RL= 8 Ω , fs= 384 kHz, OC_ADJ = 22 k Ω ,
TC= 75 ° C, output filter is L
TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system
configuration are in accordance with recommended design guidelines.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

P

O

P

O

THD+N 0.09 %

SNR Signal-to-noise ratio
DNR Dynamic range –60-dBFS input, A-weighted filter 110 dB
VOO Output offset voltage –15 15 mV

P

idle

(1) SNR is calculated relative to the 0 dBFS input level.
(2) Actual system idle losses are also affected by core losses of output inductors.

Unclipped power output RL= 6 Ω , f = 1 kHz 165 W

Maximum power output W

Total harmonic distortion + noise, 1 W to 125 W, RL=8 Ω , AES17 filter,
AES 17 filter Unclipped

Power dissipation due to idle losses
(I

)

PVDD_X

= 10 µ H, CL= 1 µ F (unless otherwise noted). Audio performance is recorded as a chipset,

DEM

RL= 8 Ω , f = 1 kHz 125

RL= 4 Ω , f = 1 kHz 235
RL= 8 Ω , f = 1 kHz, THD = 10% 165
RL= 6 Ω , f = 1 kHz, THD = 10% 220
RL= 4 Ω , f = 1 kHz, THD = 10% 315
RL= 3 Ω , f = 1 kHz, CBC allowed 400

(1)

Ratio of 1-FFS to 0-FFS input,
A-weighted filter

PWM switching frequency 384 kHz,
Measured on speaker terminals

PO= 0 W, Output switching

(2)

110 dB

2 W

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TAS5261

SLES188 – AUGUST 2006

ELECTRICAL CHARACTERISTICS

Audio frequency = 1 kHz, PVDD_x = 50 V, GVDDx = 12 V, VDD = 12 V, RL= 8 Ω , fs= 384 kHz, OC_ADJ = 22 k Ω ,
TC= 75 ° C, output filter is L
TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system
configuration are in accordance with recommended design guidelines.

PARAMETER CONDITIONS MIN TYP MAX UNIT

Internal Voltage Regulator and Current Consumption

VREG 3.3 V

I

VDD

I

GVDD_x

I

PVDD_x

Output-Stage MOSFETs

R

DSON,LS

R

DSON,HS

I/O Protection

V

UVP,POS

OTW Overtemperature warning 125 ° C
OTW

hys

OTE Overtemperature error threshold 155 ° C
OTE

hys

OTE-OTW
differential

OLPC Overload protection time constant f
I

OC

R

OC

R

PD

PWM PWM Activity Detector Lack of transition of any PWM input 13 µ s

(1) DC measurement with 1-ms pulse

Voltage regulator,
only used as reference node

VDD supply current mA

GVDD_x gate-supply current
per half bridge

Half-bridge idle current

Drain-to-source resistance, low side TJ= 25 ° C, LDMOS only 40 m Ω
Drain-to-source resistance, high side TJ= 25 ° C, LDMOS only 40 m Ω

Undervoltage protection limit, GVDD_x 8.5 V

OTW hysteresis 25 ° C

OTE hysteresis 30 ° C
Temperature delta between OTW and OTE 30 ° C

Overcurrent limit response
Programming resistor 22 100 k Ω
Pulldown resistor at the output of each

half-bridge

= 10 µ H, CL= 1 µ F (unless otherwise noted). AC performance is recorded as a chipset,

DEM

Operating, 50% duty cycle 7.7
Idle, reset mode 6.7
50% duty cycle 15
Idle, reset mode 1.5
50% duty cycle 23 mA
Reset mode ( RESET = 1),

No switching

= 384 kHz 20 ms

PWM

(1)

Resistor programmable high end
with OC_ADJ = 22 k Ω

(1)

Connected when RESET is high to
provide a charge path for the 2.5 k Ω
bootstrap capacitor

100 µ A

15 16 17 A

mA

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TAS5261

SLES188 – AUGUST 2006

ELECTRICAL CHARACTERISTICS

GVDD_x = 12 V ± 10%, VDD = 12 V ± 10%, TJ= 25 ° C (unless otherwise noted)

PARAMETER CONDITIONS MIN TYP MAX UNIT

Logic-Level and Open-Drain Outputs

V

IH

V

IL

(1)

I

lkg

R

INT-PD

R

INT-PU

V

OH

V

OL

FANOUT Device fanout ( OTW, SD) External pullup to 5 V 10 Devices

High-level input voltage Static 2 V
Low-level input voltage Static 0.8 V

Static, High PWM_A, High PWM_B,
High M1, High M2, High M3

Input leakage current µ A

Static, Low PWM_A, Low PWM_B,
Low M1, Low M2, Low M3

45 65

–10 10

Static, High RESET 20 40
Static, Low RESET –70 –50

Internal pulldown to AGND
for PWM_A and PWM_B inputs

50 k Ω

Internal pullup resistance on OTW and SD Resistor to VREG 20 28 33 k Ω

High-level output voltage V

Internal pullup resistor 2.4 VREG
External pullup of 3.3 k Ω to 5 V 2.5 4.9

Low-level output voltage IO= 4 mA 0.4 V

(1) Pullup and pulldown resistors affect the leakage current.

10

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TYPICAL CHARACTERISTICS

Red - 4 Ohm
Blue - 6 Ohm
Magenta - 8 Ohm

0.01

10

0.02

0.05

0.1

0.2

0.5

1

2

5

T
H
D
+
N

%

80m 300200m 500m 1 2 5 10 20 50 100 200

Output Power W

PVDD Supply Voltage − V

0

30

60

90

120

150

180

210

240

270

300

330

0 5 10 15 20 25 30 35 40 45 50

TC = 75°C
THD+N at 10%

P

O

− Output Power − W

G001

8 Ω

6 Ω

4 Ω

PVDD Supply Voltage − V

0

25

50

75

100

125

150

175

200

225

250

0 5 10 15 20 25 30 35 40 45 50

TC = 75°C

P

O

− Output Power − W

G003

8 Ω

6 Ω

4 Ω

blk

TOTAL HARMONIC DISTORTION + NOISE

vs

OUTPUT POWER

TAS5261

SLES188 – AUGUST 2006

Figure 3.

OUTPUT POWER UNCLIPPED OUTPUT POWER

vs vs

PVDD_x SUPPLY VOLTAGE PVDD_x SUPPLY VOLTAGE

Figure 4. Figure 5.

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PO − Output Power − W

0

20

40

60

80

100

0 20 40 60 80 100 120

TC = 25°C
Two Channels

Efficiency − %

G004

PO − Output Power − W

0

1

2

3

4

5

6

7

8

9

10

11

12

0 25 50 75 100 125

Power Loss − W

G005

TC = 25°C

TC − Case Temperature − °C

0

50

100

150

200

250

300

350

0 25 50 75 100 125

THD+N at 10%

P

O

− Output Power − W

G006

8 Ω

6 Ω

4 Ω

TAS5261

SLES188 – AUGUST 2006

TYPICAL CHARACTERISTICS

blk (continued)

SYSTEM EFFICIENCY SYSTEM POWER LOSS

vs vs

OUTPUT POWER OUTPUT POWER

Figure 6. Figure 7.

SYSTEM OUTPUT POWER

vs

CASE TEMPERATURE

12

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Figure 8.

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-150

+0

-145

-140

-135

-130

-125

-120

-115

-110

-105

-100

-95

-90

-85

-80

-75

-70

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

N
o

i
s
e

A
m
p

l

i

t
u
d
e

-

d
B

r

0 22k1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 13k 14k 15k 16k 17k 18k 19k 20k 21k

f - Frequency - kHz

TAS5261

SLES188 – AUGUST 2006

TYPICAL CHARACTERISTICS

blk (continued)

NOISE AMPLITUDE

vs

FREQUENCY

Figure 9.

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TAS5261

SLES188 – AUGUST 2006

Typical Application Schematic

APPLICATION INFORMATION

14

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APPLICATION INFORMATION (continued)

Recommended Printed Circuit Board (PCB) Layout

PCB Requirements

• 2-oz copper (FR-4) recommended

• PVDD voltage and capacitor selection in accordance with the data sheet

TAS5261

SLES188 – AUGUST 2006

Figure 10. PCB (Top Layer)

Figure 11. PCB (Bottom Layer)

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TAS5261

SLES188 – AUGUST 2006

THEORY OF OPERATION

PCB placement, and routing. As indicated, each half

Power Supplies

To facilitate system design, the TAS5261 needs only
a 12-V supply in addition to a typical 50-V
power-stage supply. An internal voltage regulator
provides suitable voltage levels for the digital and
low-voltage analog circuitry. Additionally, all circuitry
requiring a floating voltage supply, e.g., the high-side
gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.

To provide outstanding electrical and acoustic
characteristics, the PWM signal path, including gate
drive and output stage, is designed as identical,
independent half bridges. For this reason, each half
bridge has separated gate-drive supply (GVDD_x),
bootstrap pins (BST_x) and power-stage supply pins
(PVDD_x). Furthermore, an additional pin (VDD) is
provided as power supply for all common circuits.
Although supplied from the same 12-V source, it is
highly recommended to separate GVDD_x and VDD
on the printed circuit board (PCB) by RC filters (see
application diagram for details). These RC filters
provide the recommended high-frequency isolation.
Special attention should be paid to placing all
decoupling capacitors as close to their associated
pins as possible. In general, inductance between the
power-supply pins and decoupling capacitors must
be avoided. (See reference board documentation for There is no power-up sequence is required for the
additional information.) TAS5261. The outputs of the H-bridge remain in a

For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_x) to the power-stage output pin
(OUT_x). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
diode connected between the gate-drive
power-supply pin (GVDD_x) and the bootstrap pin.
When the power-stage output voltage is high, the
bootstrap capacitor voltage is shifted above the
output voltage potential and, thus, provides a While powering up the TAS5261, RESET should be
suitable voltage supply for the high-side gate driver. held low.
In an application with PWM switching frequencies in
the range of 352 kHz to 384 kHz, it is recommended
to use 33-nF ceramic capacitors, size 0603 or 0805,
for the bootstrap capacitor. These 33-nF capacitors
ensure sufficient energy storage, even during
minimal PWM duty cycles, to keep the high-side
power-stage FET (LDMOS) fully started during all of
the remaining part of the PWM cycle. In an
application running at a reduced switching frequency,
generally 250 kHz to 192 kHz, the bootstrap
capacitor might need to be increased in value.
Special attention should be paid to the power-stage
power supply – this includes component selection,

bridge has independent power-stage supply pins
(PVDD_x). For optimal electrical performance, EMI
compliance, and system reliability, it is important that
each PVDD_x pin is decoupled with two 100-nF
ceramic capacitors placed as close as possible to
each supply pin on the same side of the PCB as the
TAS5261 location. It is recommended to follow the
PCB layout of the TAS5261 reference design. For
additional information on the recommended power
supply and required components, see the application
diagrams given in this data sheet.

The 12-V supply should be powered from a
low-noise, low-output-impedance voltage regulator.
Likewise, the 50-V power-stage supply is assumed to
have low output impedance and low noise. The
internal POR circuit eliminates the need for
power-supply sequencing. Moreover, the TAS5261 is
fully protected against erroneous power-stage turn
on due to parasitic gate charging. Thus,
voltage-supply ramp rates (dv/dt) are noncritical
within the specified range (see the Recommended
Operating Conditions section of this data sheet).

System Power-Up/Power-Down Sequence

Powering Up

high-impedance state until the gate-drive supply
voltage (GVDD_x) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, it is
recommended to hold RESET in a low state while
powering up the device. This allows an internal
circuit to charge the external bootstrap capacitors by
enabling a weak pulldown of the half-bridge output.

Powering Down

There is no power-down sequence is required for the
TAS5261. The device remains fully operational as
long as the gate-drive supply (GVDD_x) voltage and
VDD voltage are above the undervoltage protection
(UVP) threshold level (see the Electrical
Characteristics section of this data sheet). Although
not specifically required, it is a good practice to hold
RESET low during power down, thus, preventing
audible artifacts including pops and clicks.

16

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TAS5261

SLES188 – AUGUST 2006

Error Reporting Over Current (OC) Protection With Current

The SD and OTW pins are both active-low,
open-drain outputs. Their function is for The device has independent, fast-reacting current
protection-mode signaling to a PWM controller or detectors with programmable trip threshold (OC
other system-control device. Any fault resulting in threshold) on all high-side and low-side power-stage
device shutdown is signaled by the SD pin going low. FETs. See Table 3 for OC-adjust resistor values. The
Likewise, OTW goes low when the device junction detector outputs are closely monitored by two
temperature exceeds 115 ° C. (see Table 2 ). protection systems. The first protection system

Table 2. Error Reporting output current from further increasing. For instance, it

SD OTW DESCRIPTION

0 0

0 1

1 0

1 1

Over Temperature (OTE) or Over
Load (OLP) or Under Voltage (UVP)

Over Load (OLP), PWM Activity
Dectector, or Under Voltage (UVP)

Over Temperature Warning. Junction
temperature higher than 125 ° C.

Normal operation. Junction
temperature lower than 125 ° C.

It should be noted that asserting RESET low forces
the SD and OTW signals high, independent of faults
being present. It is recommended to monitor the
OTW signal using the system microcontroller and
respond to an overtemperature warning signal by, for
example, turning down the volume to prevent further
heating of the device resulting in device shutdown
( OTW). To reduce external component count, an
internal pullup resistor to 3.3 V is provided on both
the SD and OTW outputs. Level compliance for 5-V
logic can be obtained by adding external pullup
resistors to 5 V (see the Electrical Characteristics
section of this data sheet for further specifications).

Device Protection System

The TAS5261 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as safeguarding the device from
permanent failure due to a wide range of fault
conditions, such as short circuit, overload, and
undervoltage. The TAS5261 responds to a fault by
immediately setting the power stage in a
high-impedance state (Hi-Z) and asserting the SD
pin low. In situations other than overload, the device
automatically recovers when the fault condition has
been removed (e.g., the voltage supply has
increased). For highest possible reliability, recovering
from an overload fault requires external reset of the
device no sooner than 1 s after the shutdown (see
the Device Reset section of this data sheet).

Limiting and Overload Detection

controls the power stage in order to prevent the
performs a current-limiting function rather than

prematurely shutting down during combinations of
high-level music transients and extreme speaker
load impedance drops. If the high-current situation
persists, i.e., the power stage is being overloaded, a
second protection system triggers a latching
shutdown, resulting in the power stage being set in
the high-impedance (Hi-Z) state.

Table 3. OC-Adjust Resistor Values

OC-ADJUST

RESISTOR VALUES

(1) Resistor tolerance is ± 5%.

(1)

(k Ω )

22 15 16 17
27 12 13 14
47 7 8 8
68 5 5 6

100 3 4 4

For lowest-cost bill of materials in terms of
component selection, the OC threshold current
should be limited, considering the power output
requirement and minimum load impedance.
Higher-impedance loads require a lower OC
threshold.

The demodulation filter inductor must retain a
minimum of 5-H inductance at twice the selected OC
threshold current.

Most inductors have decreasing inductance with
increasing temperature and increasing current
(saturation). To some degree, an increase in
temperature naturally occurs when operating at high
output currents, due to inductor core losses and the
dc resistance of the inductor copper winding. A
thorough analysis of inductor saturation and thermal
properties is strongly recommended.

Setting the OC threshold too low might cause issues,
such as lack of enough output power and/or
unexpected shutdowns due to sensitive overload
detection.

In general, it is recommended to follow closely the
external component selection and PCB layout as
given in the Application Information section of this
data sheet.

CURRENT BEFORE OC OCCURS

(A)

MIN TYP MAX

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17

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TAS5261

SLES188 – AUGUST 2006

For added flexibility, the OC threshold is VDD or GVDD_x pin results in all half-bridge outputs
programmable within a limited range using a single immediately being set in the high-impedance state
external resistor connected between the OC_ADJ pin (Hi-Z) and SD being asserted low. The device
and AGND. It should be noted that a properly automatically resumes operation when all supply
functioning overcurrent detector assumes the voltages have increased above the UVP threshold.
presence of a properly designed demodulation filter
at the power-stage output. Short-circuit protection is
not provided directly at the output pins of the power
stage but only on the speaker terminals (after the
demodulation filter). It is required to follow certain
guidelines when selecting the OC threshold and an
appropriate demodulation inductor.

Over Temperature (OTE) Protection

The TAS5261 has a two-level,
temperature-protection system that asserts an
active-low warning signal ( OTW) when the device
junction temperature exceeds the OTW level stated
in the parametric table. If the device junction
temperature exceeds the OTE level stated in the
parametric table, the device is put into thermal
shutdown, resulting in all half-bridge outputs being
set in the high-impedance state (Hi-Z) and SD being
asserted low. OTE is latched in this case. To clear
the OTE latch, reset must be asserted. Thereafter,
the device resumes normal operation.

Under Voltage Protection (UVP) and Power-On Reset (POR)

The UVP and POR circuits of the TAS5261 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_x and VDD supply voltages reach the UVP
level stated in the parametric table. Although
GVDD_x and VDD are independently monitored, a
supply-voltage drop below the UVP threshold on any

Device Reset

When RESET is asserted low, the output FETs in all
half bridges are forced into a high-impedance state
(Hi-Z). During this reset time, a resistor is connected
between OUT_x and PGND pins, in order to charge
the bootstrap capacitor.

Asserting RESET input low removes fault
information. A rising-edge transition on the reset
input allows the device to resume operation after an
overload fault.

PWM Activity Detector

The PWM Activity Detector logic monitors individual
PWM inputs. If one or more inputs are stuck in either
a high state or a low state for more than a defined
length of time, the entire device is shut down.

The PWM Activity Detector is not latched and normal
operation resumes when PWM activity is present on
the PWM inputs. When an invalid PWM frame is
detected, the PWM Activity Detector responds
immediately (no delay). The TAS5261 resumes
operation as soon as valid PWM signals are present.

The PWM Activity Detector is reported as a low on
the SD pin.

Modulation Index Setting

96.1% is the recommended setting for the
modulation index limit of the PWM when driving the
TAS5261. The following shows modulation index
limit registers and setting value in hexadecimal for TI
modulators.

TAS5508/TAS5518: 0x16h at 04h
TAS5086: 0x10h at 04h

18

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6-Dec-2006

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

TAS5261DKD ACTIVE SSOP DKD 36 29 Green (RoHS &

no Sb/Br)

TAS5261DKDG4 ACTIVE SSOP DKD 36 29 Green (RoHS &

no Sb/Br)

TAS5261DKDR ACTIVE SSOP DKD 36 500 Green (RoHS &

no Sb/Br)

TAS5261DKDRG4 ACTIVE SSOP DKD 36 500 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-4-260C-72 HR

CU NIPDAU Level-4-260C-72 HR

CU NIPDAU Level-4-260C-72 HR

CU NIPDAU Level-4-260C-72 HR

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

6-Jun-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

Device Package Pins Site Reel

Diameter

(mm)

TAS5261DKDR DKD 36 AP3 330 24 14.7 16.4 4.0 20 24 NONE

Reel

Width

(mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

6-Jun-2007

Pin1

Quadrant

TAPE AND REEL BOX INFORMATION

Device Package Pins Site Length (mm) Width (mm) Height (mm)

TAS5261DKDR DKD 36 AP3 337.0 343.0 41.0

Pack Materials-Page 2

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