Datasheet TA2020-020 Datasheet (TRIPATH TECHNOLOGY)

TECHNICAL INFORMATION

Stereo 20W (4ΩΩΩΩ) Class-T Digital Audio Amplifier using
Digital Power Processing

September, 2000

General Description

The TA2020-020 is a 20W continuous average two-channel Class-T Digital Audio Power
Amplifier IC using Tripath’s proprietary Digital Power Processing
amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D
amplifiers.

Applications

¾DVD Players
¾Mini/Micro Component Systems
¾Automotive Audio
¾Computer / PC Multimedia
¾Cable Set-Top Products
¾Televisions
¾Battery Powered Systems

Benefits

¾Fully integrated solution with FETs

Easier to design-in than Class-D

¾

Reduced system cost with no heat sink

¾

¾Dramatically improves efficiency versus

Class-AB

¾Signal fidelity equal to high quality linear

amplifiers

¾High dynamic range compatible with

digital media such as CD, DVD, and
internet audio

Typical Performance

THD+N versus Output Power

10

VDD = 13.5V

5

Av = 12
f = 1kHz
BW = 22Hz - 22kHz

2

1

0.5

TM

Technology TA2020-020

TM

technology. Class-T

Features

¾Class-T architecture
¾Single Supply Operation
¾“Audiophile” Quality Sound

¾0.03% THD+N @ 10W 4Ω
¾0.1% THD+N @12W 4Ω
¾0.18% IHF-IM @ 1W 4Ω

¾High Power

¾13W @ 8Ω, 10% THD+N
¾23W @ 4Ω, 10% THD+N
¾38W EIAJ* VDD=14.4V @

*saturated square wave output

¾High Efficiency

¾88% @ 12W 8Ω
¾81% @ 20W 4Ω

¾Dynamic Range = 103 dB

X

¾Up to 2
¾Mute and Sleep inputs
¾Turn-on & turn-off pop suppression
¾Over-current protection
¾Over-temperature protection
¾Bridged outputs
¾32-pin SSIP package

25Wrms @ 4Ω, VDD=14.6V

4

Ω

0.2

THD+N (%)

0.1

0.05

0.02

0.01

RL= 8

Ω

1 2 3 4 5 6 7 8 9 10 20500m

Output Power (W)

RL= 4

Ω

1 of 13 TA2020-020, Rev. 4.0, 09.00

TECHNICAL INFORMATION

Absolute Maximum Ratings

(Note 1)

SYMBOL PARAMETER Value UNITS

V

DD

T

STORE

T

A

T

J

Supply Voltage 16 V

Storage Temperature Range

Operating Free-air Temperature Range

Junction Temperature

-40

-40

°

to 150°

to 85°

°

150

°

C

C

C

Note 1:

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

Operating Conditions

SYMBOL PARAMETER MIN. TYP. MAX. UNITS

V

DD

V

IH

V

IL

Note 2: Recommended Operating Conditions indicate conditions for which the device is functional.
See Electrical Characteristics for guaranteed specific performance limits.

Supply Voltage 8.5 13.5 14.6 V

High-level Input Voltage (MUTE, SLEEP) 3.5 V

Low-level Input Voltage (MUTE, SLEEP) 1 V

(Note 2)

Thermal Characteristics

SYMBOL PARAMETER Value UNITS

θ

JC

θ

JA

Junction-to-case Thermal Resistance

Junction-to-ambient Thermal Resistance

3.5

15

°

°

C/W

C/W

2 of 13 TA2020-020, Rev. 4.0, 09.00

TECHNICAL INFORMATION

Electrical Characteristics

(Note 1, 2)

See Test/Application Circuit. Unless otherwise specified, VDD = 13.5V, f = 1kHz, Measurement
Bandwidth = 22kHz, R

= 4Ω, TA = 25 °C.

L

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITS

P

O

I

DD,MUTE

I

DD, SLEEP

I

q

THD + N Total Harmonic Distortion Plus

IHF-IM IHF Intermodulation Distortion 19kHz, 20kHz, 1:1 (IHF) 0.18 %

SNR Signal-to-Noise Ratio

CS Channel Separation

PSRR Power Supply Rejection Ratio Vripple = 100mV 60 80 dB

η

V

OFFSET

VOH High-level output voltage

VOL Low-level output voltage

e

OUT

Output Power
(Continuous Average/Channel)

Mute Supply Current MUTE = VIH 5.5 7 mA

Sleep Supply Current SLEEP = VIH 0.25 2 mA

Quiescent Current VIN = 0 V 60 mA

Noise

Power Efficiency

Output Offset Voltage No Load, MUTE = Logic low 50 150 mV

(FAULT & OVERLOADB)

(FAULT & OVERLOADB)

Output Noise Voltage A-Weighted, input AC grounded 100

THD+N = 0.1% R
R
THD+N = 10% R
R

PO = 10W/Channel 0.03 %

A-Weighted, P

0dBr = 1W, R

= 12W/Channel, RL = 8Ω

P

OUT

3.5 V

1 V

L

= 4Ω

L

= 8Ω

L

= 4Ω

L

= 8Ω

L

= 1W, RL = 8Ω

OUT

= 4Ω, f = kHz

13

8
22
12

89 dB

74 80 dB

88 %

W

W
W
W

V

µ

Notes:

1) Minimum and maximum limits are guaranteed but may not be 100% tested.

2) For operation in ambient temperatures greater than 25°C, the device must be derated based on
the maximum junction temperature and the thermal resistance determined by the mounting
technique.

TA2020-020, Rev. 4.0, 09.00 3 of 13

TECHNICAL INFORMATION

Pin Description

Pin

Function

2, 8 V5D, V5A Digital 5VDC, Analog 5VDC

3, 7,

16

AGND1, AGND2,

AGND3
4 REF Internal reference voltage; approximately 1.0VDC
6 OVERLOADB A logic low output indicates the input signal has overloaded the amplifier.

9, 12 VP1, VP2 Input stage output pins

10, 13 IN1, IN2 Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with

11 MUTE When set to logic high, both amplifiers are muted and in idle mode. W hen low

14 BIASCAP Input stage bias voltage (approximately 2.4VDC).
17 SLEEP When set to logic high, device goes into low power mode. If not used this pin

18 FAULT A logic high output indicates thermal overload, or an output is shorted to ground,

19, 28 PGND2, PGND1 Power Ground (high current)

20 DGND Digital Ground

21, 23,

26, 24

OUTP2 & OUTM2;

OUTP1 & OUTM1

22, 25 VDD2, VDD1 Supply pin for high current H-bridges, nominally 13.5VDC.

1, 5, 15 NC Not connected

27 VDDA Analog 13.5VDC
29 CPUMP Charge pump output (nominally 10V above VDDA)
30 5VGEN Regulated 5VDC source used to supply power to the input section (pins 2 & 8).

31, 32 DCAP2, DCAP1 Charge pump switching pins. DCAP1 (pin 32) is a free running 300kHz square

Description

Analog Ground

approximately 2.4VDC bias.

(grounded), both amplifiers are fully operational. If left floating, the device stays in
the mute mode. Ground if not used.

should be grounded.

or another output.

Bridged outputs

wave between VDDA and DGND (13.5Vpp nominal). DCAP2 (pin 31) is level
shifted 10 volts above DCAP1 (pin 32) with the same amplitude (13.5Vpp
nominal), frequency, and phase as DCAP1.

AGND1

OVERLOADB

AGND2

BIASCAP

AGND3

PGND2

OUTP2

OUTM2
OUTM1

OUTP1

PGND1
CPUMP

5VGEN
DCAP2
DCAP1

V5D

REF

V5A
VP1

MUTE

VP2

SLEEP
FAULT

DGND

VDD2

VDD1

VDDA

32-pin SSIP Package

NC

NC

IN1

IN2

NC

(Front View)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

4 of 13 TA2020-020, Rev. 4.0, 09.00

TECHNICAL INFORMATION

Application/Test Circuit

TA2020-020

CPUMP

VDDA

DGND

5VGEN

VDD1

PGND1

VDD2

PGND2

VDD1

PGND1

VDD1

PGND1

VDD2

PGND2

VDD2

PGND2

29

22

19

26

24

18

6

21

23

27

20

30

25

28

OUTP1

D

(Pin 28)

OUTM1

D

(Pin 28)

FAULT

OVERLOADB

OUTP2

D

(Pin 19)

OUTM2

D

(Pin 19)

+

C

1uF

0.1uF

0.1uF

C

0.1uF

C

0.1uF

O

O

O

O

P

C

S

C

S

SW

SW

L

o

10uH, 3A

(Pin 28)

L

o

10uH, 3A

L

o

10uH, 3A

(Pin 19)

L

o

10uH, 3A

To Pin 2,8

+

180uF, 16V

+

C

180uF, 16V

C

SW

SW

2.2uF

(Pin 7)

2.2uF

(Pin 3)

+12V

To Pin 30

1

NC

9

VP1

R

+

20K

C

0.1uF

R

A

20K

I

5V

Ω

F

Ω

IN1

BIASCAP

10

Processing

&

Modulation

14

5V

C

I

11

MUTE

12

VP2

R

F

20K

I

+

1meg

0.1uF

R

I

20K

Ω

8.25KΩ, 1%

Ω

0.1uF

0.1uF

Ω

R

0.1uF

C

C

S

IN2

13

4

REF

C

D

S

REF

32

DCAP1

31

DCAP2

SLEEP

17

5

NC

2

V5D

3

AGND1

8

V5A

7

AGND2

15

NC

16

AGND3

Processing

&

Modulation

5V

C

*C

o

0.47uF

*C

o

0.47uF

*C

o

0.47uF

*C

o

0.47uF

C

Z

0.47uF

R

Z

10

C

Z

0.47uF

R

Z

10

Ω,

VDD

1/2W

Ω,

1/2W

(+13.5V)

C

CM

0.1uF

C

0.1uF

R

L

4Ω or *8

Ω

CM

R

L

4Ω or *8

Ω

Note: Analog and Digital/Power Grounds must
be connected locally at the TA2020-020

Analog Ground

Digital/Power Ground

All Diodes Motorola MBRS130T3

* Use Co = 0.22µF for 8 Ohm loads

TA2020-020, Rev. 4.0, 09.00 5 of 13

TECHNICAL INFORMATION

External Components Description

Components Description
R

Inverting input resistance to provide AC gain in conjunction with RF. This input is

I

biased at the BIASCAP voltage (approximately 2.4VDC).

RF Feedback resistor to set AC gain in conjunction with RI;

to the Amplifier Gain paragraph, in the Application Information section.

CI AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at

)CR2(1f

π=

IIC

R

Bias resistor. Locate close to pin 4 and ground at pin 7.

REF

CA BIASCAP decoupling capacitor. Should be located close to pin 14 and grounded at

pin 7.

CD Charge pump input capacitor. This capacitor should be connected directly between

pins 31 and 32 and located physically close to the TA2020-020.

CP Charge pump output capacitor that enables efficient high side gate drive for the

internal H-bridges. To maximize performance, this capacitor should be connected
directly between pin 29 (CPUMP) and pin 27 (VDDA). Please observe the polarity
shown in the Application/Test Circuit.

CS Supply decoupling for the low current power supply pins. For optimum performance,

these components should be located close to the pin and returned to their
respective ground as shown in the Application/Test Circuit.

CSW Supply decoupling for the high current H-Bridge supply pins. These components

must be located as close to the device as possible to minimize supply overshoot and
maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk
capacitor (180uF) should have good high frequency performance including low ESR
and low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor.

CZ Zobel capacitor, which in conjunction with RZ, terminates the output filter at high

frequencies

RZ Zobel resistor, which in conjunction with CZ, terminates the output filter at high

frequencies. The combination of R
under both no load conditions or with real world loads, including loudspeakers which
usually exhibit a rising impedance with increasing frequency. Depending on the
program material, the power rating of R
is ½ watt.

DO Schottky diodes that minimize undershoots of the outputs with respect to power

ground during switching transitions. For maximum effectiveness, these diodes must
be located close to the output pins and returned to their respective PGND. Please
see Application/Test Circuit for ground return pin.

LO Output inductor, which in conjunction with CO, demodulates (filters) the switching

waveform into an audio signal. Forms a second order filter with a cutoff frequency
of and a quality factor of

C

O

CCM Common mode capacitor.

Output capacitor which in conjunction with L
waveform into an audio signal. Forms a second order low-pass filter with a cutoff

frequency of

(Refer to the Application/Test Circuit)

and CZ minimizes peaking of the output filter

Z

may need to be adjusted. The typical value

Z

.

=

and a quality factor of

π=

)CL2(1f

OOC

CLCRQ

OOOL

, demodulates (filters) the switching

O

. Please refer

=

=

)R/R(12A

IFV

.

CLCRQ

OOOL

6 of 13 TA2020-020, Rev. 4.0, 09.00

TECHNICAL INFORMATION

Typical Performance Characteristics

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0 5 10 15 20 25 30

Efficiency vers us Output Power

RL = 8

Ω

RL = 4

Ω

Output Power (W)

Intermodulation Performance

+0

VDD = 13.5V

-10
Pout = 1W/Channel

RLoad = 4W
19kHz, 20kHz, 1:1

-20
0dBr = 12Vrms

Av = 12

-30
BW = 10Hz - 80kHz

-40

-50

FFT (dBr)

-60

-70

-80

-90

-100

50 30k

1k

2k 5k

10k

Frequency (Hz)

VDD = 13.5V
f = 1kHz
Av = 12

20k

+0

Channel Separation versus Frequency

-10
VDD = 13.5V

Pout = 1W/Channel
RLoad = 4

-20

-30

-40

-50

-60

-70

Channel Separation (dBr)

-80

-90

-100
20 20k50 100 200 500 1k 2k 5k 10k

+0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Noise FFT (dBV)

-110

-120

-130

-140

-150
20

Ω

Av = 12
BW = 22Hz - 22kHz

Frequency (Hz)

Noise Floor

VDD = 13.5V
Pout = 0W
Av = 12
RLoad = 4

Ω

BW = 20Hz - 22kHz
A-Weighted Filter

50 100 200 500 1k 2k 5k 10k

Frequency (Hz)

20k

10

VDD = 13.5V

5

Pout = 5W/Channel
Av = 12

2

BW = 22Hz - 22kHz

1

0.5

0.2

0.1

THD+N (%)

0.05

RL = 4

0.02

0.01

10 20k20 50 100 200 500 1k 2k 5k 10k

Ω

RL = 8

Ω

Frequency (Hz)

TA2020-020, Rev. 4.0, 09.00 7 of 13

THD+N versus Frequency

Frequency Response

+3

VDD = 13.5V

+2.5

Pout = 1W
RLoad = 4

+2

+1.5

+1

+0.5

+0

-0.5

-1

Output Amplitude (dBr)

-1.5

-2

-2.5

-3
10 20k20 50 100 200 500 1k 2k 5k 10k

Ω

Av = 12
BW = 22Hz - 22kHz

Frequency (Hz)

TECHNICAL INFORMATION

Application Information

Circuit Board Layout

The TA2020-020 is a power (high current) amplifier that operates at relatively high switching
frequencies. The outputs of the amplifier switch between the supply voltage and ground at high
speeds while driving high currents. This high-frequency digital signal is passed through an LC low­pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC
output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and
below ground by the energy in the output inductance. To avoid subjecting the TA2020-020 to
potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is
recommended that Tripath’s layout and application circuit be used for all applications and only be
deviated from after careful analysis of the effects of any changes.

The figures below are the Tripath TA2020-020 evaluation board. Some of the most critical
components on the board are the power supply decoupling capacitors. C674 and C451 must be
placed right next to pins 22 and 19 as shown. C673 and C451B must be placed right next to pins
25 and 28 as shown. These power supply decoupling capacitors from the output stage not only
help reject power supply noise, but they also absorb voltage spikes on the VDD pins caused by
overshoots of the outputs of the amplifiers. Voltage overshoots can also be caused by output
inductor flyback during high current switching events such as shorted outputs or driving low
impedances at high levels. If these capacitors are not close enough to the pins, electrical
overstress to the part can occur, possibly resulting in permanent damage to the TA2020-020.

8 of 13 TA2020-020, Rev. 4.0, 09.00

TECHNICAL INFORMATION

Amplifier Gain

The gain of the TA2020-020 is set by the ratio of two external resistors, R

and RF, and is given by

I

the following formula:

V

O

V

I

R

F

12

=

R

I

where V

is the input signal level and VO is the differential output signal level across the speaker.

I

20 watts of RMS output power results from an 8.944 V RMS signal across a four-ohm speaker load.
If R

= RI, then 20 Watts will be achieved with 0.745 V RMS of input signal.

F

OLRMS

∗Ω=∗=

)W204()PR(V944.8

Protection Circuits

The TA2020-020 is guarded against over-temperature and over-current conditions. When the
device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH
state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRI­STATED, and will float to 1/2 of V

DD

.

Over-temperature Protection

An over-temperature fault occurs if the junction temperature of the part exceeds approximately
155°C. The thermal hysteresis of the part is approximately 45°C, therefore the fault will
automatically clear when the junction temperature drops below 110°C.

Over-current Protection

An over-current fault occurs if more than approximately 7 amps of current flows from any of the
amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the
speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if
the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is connected to
the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset
the fault condition.

Overload

The OVERLOADB pin is a 5V logic output. When low, it indicates that the level of the input signal
has overloaded the amplifier resulting in increased distortion at the output. The OVERLOADB
signal can be used to control a distortion indicator light or LED through a simple buffer circuit.

Sleep Pin

The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent
current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the

TA2020-020, Rev. 4.0, 09.00 9 of 13

(

)

(

)

TECHNICAL INFORMATION

pin to be pulled up through a large valued resistor (1MΩ recommended) to V

. To disable SLEEP

DD

mode, the sleep pin should be grounded.

Fault Pin

The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These
conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over
current at any output, and junction temperature greater than approximately 155°C. The FAULT
output is capable of directly driving an LED through a series 200Ω. The FAULT output is capable of
directly driving an LED through a series 200Ω resistor. If the FAULT pin is connected directly to the
MUTE input an automatic reset will occur in the event of an over-current condition.

Heat Sink Requirements

In some applications it may be necessary to fasten the TA2020-020 to a heat sink. The determining
factor is that the 150°C maximum junction temperature, T

(max) cannot be exceeded, as specified

J

by the following equation:

TT

−

P

DISS

=

θ

A)MAX(J

JA

where…
P

= maximum power dissipation

DISS

T

= maximum junction temperature of TA2020-020

JMAX

T

= operating ambient temperature

A

= junction-to-case thermal resistance of TA2020-020

θ

JC

Example:

What size heat sink is required to operate the TA2020-020 at 20W per channel continuously in a
70ºC ambient temperature?

P

is determined by:

DISS

P

η

Efficiency =

=

OUT

P

IN

=

P

OUT

−

PP

DISSOUT

(per channel) =

P

DISS

P

OUT

P

η

OUT

20

W520

=−=−

8.0

Thus, P

for two channels = 10W

DISS

TT

−

DISS

A)MAX(J

=

=

θ

JA

P

10

70150

−

= 8°C/W

10 of 13 TA2020-020, Rev. 4.0, 09.00

TECHNICAL INFORMATION

The

of the TA2020-020 in free air is 15°C/W. The

θ

JA

of the TA2020-020 is 3.5°C/W, so a heat

θ

JC

sink of 4.5°C/W is required for this example. In actual applications, other factors such as the
average P

with a music source (as opposed to a continuous sine wave) and regulatory agency

DISS

testing requirements will determine the size of the heat sink required.

Performance Measurements of the TA2020-020

The TA2020-020 operates by generating a high frequency switching signal based on the audio
input. This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an
amplified version of the audio input. The frequency of the switching pattern is spread spectrum in
nature and typically varies between 100kHz and 1MHz, which is well above the 20Hz – 20kHz
audio band. The pattern itself does not alter or distort the audio input signal, but it does introduce
some inaudible components.

The measurements of certain performance parameters, particularly noise related specifications
such as THD+N, are significantly affected by the design of the low-pass filter used on the output as
well as the bandwidth setting of the measurement instrument used. Unless the filter has a very
sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited,
some of the inaudible noise components introduced by the TA2020-020 amplifier switching pattern
will degrade the measurement.

One feature of the TA2020-020 is that it does not require large multi-pole filters to achieve excellent
performance in listening tests, usually a more critical factor than performance measurements.
Though using a multi-pole filter may remove high-frequency noise and improve THD+N type
measurements (when they are made with wide-bandwidth measuring equipment), these same
filters degrade frequency response. The TA2020-020 Evaluation Board uses the Application/Test
Circuit of this data sheet, which has a simple two-pole output filter and excellent performance in
listening tests. Measurements in this data sheet were taken using this same circuit with a limited
bandwidth setting in the measurement instrument.

TA2020-020, Rev. 4.0, 09.00 11 of 13

TECHNICAL INFORMATION

Package Information

32-pin SSIP Package:

12 of 13 TA2020-020, Rev. 4.0, 09.00

TECHNICAL INFORMATION

ADVANCED INFORMATION – This is a product in development. Tripath Technology Inc. reserves
the right to make any changes without further notice to improve reliability, function or design.

Tripath and Digital Power Processing are trademarks of Tripath Technology Inc. Other trademarks
referenced in this document are owned by their respective companies

Tripath Technology Inc. reserves the right to make changes without further notice to any products
herein to improve reliability, function or design. Tripath does not assume any liability arising out of
the application or use of any product or circuit described herein; neither does it convey any license
under its patent rights, nor the rights of others.

TRIPATH’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN
LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF
THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical
implant into the body, or (b) support or sustain life, and whose failure to perform, when properly
used in accordance with instructions for use provided in this labeling, can be reasonably
expected to result in significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to
perform can be reasonably expected to cause the failure of the life support device or system, or
to affect its safety or effectiveness.

For more information on Tripath products, visit our web site at:

World Wide Sales Offices
Western United States: Jim Hauer [e-mail] 408-567-3089
Taiwan, HK, China: Jim Hauer [e-mail] 408-567-3089
Japan: Osamu Ito [e-mail] 81-42-334-2433
Europe: Steve Tomlinson [e-mail] 44-1672-86-1020

www.tripath.com

.

B

TRIPATH TECHNOLOGY, INC.

3900 Freedom Circle, Suite 200
Santa Clara, California 95054
408-567-3000

TA2020-020, Rev. 4.0, 09.00 13 of 13