Datasheet TA2020 Datasheet

Tripath Technology, Inc. - Technical Information

TA2020-020

STEREO 20W (4Ω) CLASS-T™ DIGITAL AUDIO AMPLIFIER DRIVER
USING DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY

Technical Information Revision 7.1 – March 2005

GENERAL DESCRIPTION

The TA2020-020 is a 20W (4Ω) continuous average per channel Class-T Digital Audio Power Amplifier IC
using Tripath’s proprietary Digital Power Processing (DPP
audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.

TM

) technology. Class-T amplifiers offer both the

APPLICATIONS

 DVD Players
 Mini/Micro Component Systems
 Computer / PC Multimedia
 Cable Set-Top Products
 Televisions
 Battery Powered Systems

BENEFITS

 Fully integrated solution with internal FETs
 Easier to design-in than Class-D
 Reduced system cost with minimal heat sink

requirement

 Dramatically improves efficiency versus Class-AB

amplifiers

 Signal fidelity equal to high quality linear

amplifiers

 High dynamic range compatible with digital media

such as CD and DVD, and internet audio

TYPICAL PERFORMANCE

FEATURES

 Class-T architecture
 Single Supply Operation

 “Audiophile” Quality Sound

0.03% THD+N @ 10W 4Ω



 0.1% THD+N @12W 4Ω

 0.18% IHF-IM @ 1W 4Ω

 High Power

 25W @ 4Ω, 10% THD+N, V
 22W @ 4Ω, 10% THD+N, V
 13W @ 8Ω, 10% THD+N, V

DD=14.6V
DD=13.5V
DD=13.5V

 High Efficiency

 88% @ 12W 8Ω

 81% @ 20W 4Ω
 Dynamic Range = 99dB
 Mute and Sleep inputs
 Turn-on & turn-off pop suppression
 Over-current protection
 Over-temperature protection

 Bridged outputs

 32-pin SSIP package

THD+N versus Output Power

10

VDD = 13.5V

5

Av = 12V/V
f = 1kHz
BW = 22Hz - 22kHz

2

1

0.5

0.2

THD+N (%)

0.1

0.05

0.02

0.01
1 2 3 4 5 6 7 8 9 10 20500m

Output Power (W)

1 TA2020 – KL/7.1/03.05

RL= 8Ω

RL= 4Ω

Tripath Technology, Inc. - Technical Information

ABSOLUTE MAXIMUM RATINGS

(Note 1)

SYMBOL PARAMETER Value UNITS

V

DD

V5 Input Section Supply Voltage 6.0 V

SLEEP SLEEP Input Voltage -0.3 to 6.0 V

MUTE MUTE Input Voltage -0.3 to V5+0.3 V

ESD

HBM

ESDMM ESD Susceptibility, Machine Model (Note 3) 200 V

T

STORE

T

A

T

J

Supply Voltage 16 V

ESD Susceptibility, All pins except 2, 30

Human Body Model (Note2) Pins 2, 30

Storage Temperature Range -40 to 150

Operating Free-air Temperature Range -40 to 85

Junction Temperature 150

2000
1000

V
V

C

°

C

°

C

°

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

See the table below for Operating Conditions.
Note 2: Human body model, 100pF discharged through a 1.5KΩ resistor.
Note 3: Machine model, 220pF discharged through all pins.

OPERATING CONDITIONS (Note 4)

SYMBOL PARAMETER MIN. TYP. MAX. UNITS

V

V

V

Supply Voltage 8.5 13.5 14.6 V

DD

High-level Input Voltage (MUTE, SLEEP) 3.5 V

IH

Low-level Input Voltage (MUTE, SLEEP) 1 V

IL

Note 4: Recommended Operating Conditions indicate conditions for which the device is functional.

See Electrical Characteristics for guaranteed specific performance limits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNITS

θ

θ

Junction-to-case Thermal Resistance 3.5

JC

Junction-to-ambient Thermal Resistance 15

JA

C/W

°

C/W

°

2 TA2020 – KL/7.1/03.05

Tripath Technology, Inc. - Technical Information

ELECTRICAL CHARACTERISTICS (Notes 6, 7)

See Test/Application Circuit. Unless otherwise specified, VDD = 13.5V, f = 1kHz,
Measurement Bandwidth = 22kHz, R

= 4Ω, TA = 25 °C.

L

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITS

P

O

Output Power
(Continuous Average/Channel)

P

O

Output Power (VDD=14.6V)
(Continuous Average/Channel)

I

DD,MUTE

I

DD, SLEEP

I

q

Mute Supply Current MUTE = VIH 5.5 7 mA

Sleep Supply Current SLEEP = VIH 0.25 2 mA

Quiescent Current VIN = 0 V 64 75 mA

THD + N Total Harmonic Distortion Plus

THD+N = 0.1% R
R
THD+N = 10% R
R
THD+N = 0.1% R
R
THD+N = 10% R
R

= 4Ω

L

= 8Ω

L

= 4Ω

L

= 8Ω

L

= 4Ω

L

= 8Ω

L

= 4Ω

L

= 8Ω

L

PO = 10W/Channel 0.03 %

11

7
18
10

16.5

9.5
25

14.8

Noise

IHF-IM IHF Intermodulation Distortion 19kHz, 20kHz, 1:1 (IHF) 0.1 0.5 %

SNR Signal-to-Noise Ratio

CS Channel Separation

A-Weighted, P

0dBr = 1W, R

= 20W, RL = 4Ω

OUT

= 4Ω, f = 1 kHz

L

PSRR Power Supply Rejection Ratio VDD = 9V to 13.2V

Vripple = 100mV, f=1kHz

η

V

OFFSET

VOH High-level output voltage

Power Efficiency

P

= 12W/Channel, RL = 8Ω

OUT

Output Offset Voltage No Load, MUTE = Logic low 50 150 mV

3.5 V

99 dB

70 80 dB

65 75

65

88 %

(FAULT & OVERLOADB)

VOL Low-level output voltage

1 V

(FAULT & OVERLOADB)

e

Output Noise Voltage A-Weighted, input AC grounded 100

OUT

Note 6: Minimum and maximum limits are guaranteed but may not be 100% tested.
Note 7: For operation in ambient temperatures greater than 25°C, the device must be derated based on the

maximum junction temperature and the thermal resistance determined by the mounting technique.

W

W
W
W

W

W
W
W

dB

dB

V

µ

3 TA2020 – KL/7.1/03.05

Tripath Technology, Inc. - Technical Information

PIN DESCRIPTION

Pin Function Description
2, 8 V5D, V5A Digital 5VDC, Analog 5VDC

3, 7,

16

AGND1, AGND2,

AGND3

Analog Ground

4 REF Internal reference voltage; approximately 1.0VDC
6 OVERLOADB A logic low output indicates the input signal has overloaded the amplifier.

9, 12 OAOUT1, OAOUT2 Input stage output pins

10, 13 INV1, INV2 Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with

approximately 2.4VDC bias.

11 MUTE When set to logic high, both amplifiers are muted and in idle mode. When low

(grounded), both amplifiers are fully operational. If left floating, the device stays in

the mute mode. Ground if not used.
14 BIASCAP Input stage bias voltage (approximately 2.4VDC).
17 SLEEP When set to logic high, device goes into low power mode. If not used this pin

should be grounded. Can be pulled-up to V

DD with a 1MΩ resistor (100KΩ

minimum).
18 FAULT A logic high output indicates thermal overload, or an output is shorted to ground,

or another output.

19, 28 PGND2, PGND1 Power Ground (high current)

20 DGND Digital Ground. Should be connected to AGND locally at TA2020-020.

21, 23,

26, 24

OUTP2 & OUTM2;

OUTP1 & OUTM1

Bridged output pairs

22, 25 VDD2, VDD1 Supply pin for high current H-bridges, nominally 13.5VDC.

1, 5, 15 NC Not connected

27 VDDA Analog 13.5VDC
29 CPUMP Charge pump output (nominally 10V above VDDA)
30 5VGEN Regulated 5VDC source used to supply power to the input section (pins 2 & 8).

31, 32 DCAP2, DCAP1 Charge pump switching pins. DCAP1 (pin 32) is a free running 300kHz square

wave between VDDA and DGND (13.5Vpp nominal). DCAP2 (pin 31) is level

shifted 10 volts above DCAP1 (pin 32) with the same amplitude (13.5Vpp

nominal), frequency, and phase as DCAP1.

TA2020 PINOUT

AGND1

OVERLOADB

AGND2

OAOUT1

OAOUT2

BIASCAP

AGND3

PGND2

OUTP2

OUTM2
OUTM1

OUTP1

PGND1
CPUMP

5VGEN
DCAP2
DCAP1

V5D

REF

V5A

INV1

MUTE

INV2

SLEEP
FAULT

DGND

VDD2

VDD1

VDDA

32-pin SSIP Package

NC

NC

NC

(Front View)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

4 TA2020 – KL/7.1/03.05

APPLICATION / TEST CIRCUIT

TA2020-020

1

NC

2.2uF

(Pin 7)

2.2uF

(Pin 3)

+12V

To Pin 30

OAOUT1

R

20KΩ

F

C

I

+

R

I

20KΩ

C

A

BIASCAP

0.1uF

5V

OAOUT2

R

F

20KΩ

C

I

+

R

I

20KΩ

R

8.25KΩ, 1%

0.1uF

1M

Ω

0.1uF

C

0.1uF

C

S

0.1uF

INV1

INV2

REF

C

D

SLEEP

S

9

10

Processing

&

Modulation

14

5V

11

MUTE

12

13

4

REF

32

DCAP1

31

DCAP2

Processing

&

Modulation

17

5

15

16

2

3

8

7

NC

V5D

AGND1

V5A

AGND2

NC

AGND3

5V

CPUMP

VDDA

DGND

5VGEN

VDD1

PGND1

VDD2

PGND2

VDD1

26

PGND1

VDD1

24

PGND1

18

VDD2

21

PGND2

VDD2

23

PGND2

29

27

20

30

25

28

22

19

VDD1 (pin 25)

(Pin 28)

VDD1 (pin 25)

(Pin 28)

6

VDD2 (pin 22)

(Pin 19)

VDD2 (pin 22)

(Pin 19)

Tripath Technology, Inc. - Technical Information

D

H

OUTP1

L

o

10uH, 3A

D

O

(Pin 28)

D

H

OUTM1

10uH, 3A

D

O

FAULT

OVERLOADB

D

H

OUTP2

10uH, 3A

D

O

(Pin 19)

D

H

OUTM2

10uH, 3A

D

O

+

C

P

1uF

C

S

0.1uF

C

S

0.1uF

C

SW

0.1uF

C

SW

0.1uF

L

o

L

o

L

o

To Pin 2,8

+

C

SW

180uF, 16V

+

C

SW

180uF, 16V

*C

o

0.47uF

*C

o

0.47uF

*C

o

0.47uF

*C

o

0.47uF

C

0.22uF

R
10Ω,
1/2W

C

0.22uF

VDD

Z

Z

Z

R

Z

10Ω,
1/2W

(+13.5V)

C

DO

0.01uF

C

DO

0.01uF

R

L

4Ω or *8Ω

R

L

4Ω or *8Ω

Note: Analog and Digital/Power Grounds must
be connected locally at the TA2020-020

Analog Ground

Digital/Power Ground

Diodes (DO and DH) are Motorola MBRS130T3 (the DH diodes are required for VDD>13.5V)

* Use Co = 0.22µF and Cz=0.22uF for 8 Ohm loads

5 TA2020 – KL/7.1/03.05

=

Tripath Technology, Inc. - Technical Information

EXTERNAL COMPONENTS DESCRIPTION (Refer to the Application/Test Circuit)

Components Description

RI

Inverting input resistance to provide AC gain in conjunction with RF. This input is biased
at the BIASCAP voltage (approximately 2.4VDC).

RF

Feedback resistor to set AC gain in conjunction with R

. Please refer to

I

)R/R(12A

IFV

the Amplifier Gain paragraph, in the Application Information section.

CI

R
CA
CD

REF

AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at

.

)CR2(1f

π=

IIC

Bias resistor. Locate close to pin 4 and ground at pin 7.
BIASCAP decoupling capacitor. Should be located close to pin 14 and grounded at pin 7.
Charge pump input capacitor. This capacitor should be connected directly between pins

31 and 32 and located physically close to the TA2020-020.

CP

Charge pump output capacitor that enables efficient high side gate drive for the internal
H-bridges. To maximize performance, this capacitor should be connected directly
between pin 29 (CPUMP) and pin 27 (VDDA). Please observe the polarity shown in the
Application/Test Circuit.

CS

Supply decoupling for the low current power supply pins. For optimum performance,
these components should be located close to the pin and returned to their respective
ground as shown in the Application/Test Circuit.

CSW

Supply decoupling for the high current H-Bridge supply pins. These components must
be located as close to the device as possible to minimize supply overshoot and
maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk
capacitor (180uF) should have good high frequency performance including low ESR and
low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor.

CZ

Zobel capacitor, which in conjunction with RZ, terminates the output filter at high
frequencies

RZ

Zobel resistor, which in conjunction with CZ, terminates the output filter at high
frequencies. The combination of R

and CZ minimizes peaking of the output filter under

Z

both no load conditions or with real world loads, including loudspeakers which usually
exhibit a rising impedance with increasing frequency. Depending on the program

may need to be adjusted. The typical value is ½ watt.

Z

DO

material, the power rating of R
Schottky diodes that minimize undershoots of the outputs with respect to power ground
during switching transitions. For maximum effectiveness, these diodes must be located
close to the output pins and returned to their respective PGND. Please see
Application/Test Circuit for ground return pin.

DH

Schottky diodes that minimize overshoots of the outputs with respect to VDD during
switching transitions (required for applications where V

>13.5V). For maximum

DD

effectiveness, these diodes must be located close to the output pins and returned to their
respective V

pins. Please see Application/Test Circuit for VDD return pin.

DD

LO Output inductor, which in conjunction with CO and CDO, demodulates (filters) the

switching waveform into an audio signal. Forms a second order filter with a cutoff

frequency of

CRQ CL2

=

fπ=

O TOTC

where C

TOTTOTL

O

and a quality factor of

)CL2(1

= CO || 2 * CDO.

TOT

CO Output capacitor.
CDO Differential Output Capacitor. Differential noise decoupling for reduction of

conducted emissions. Must be located near chassis exit point for maximum
effectiveness.

6 TA2020 – KL/7.1/03.05

TYPICAL PERFORMANCE

Tripath Technology, Inc. - Technical Information

100

90

80

70

60

50

40

Efficiency (%)

30

20

10

0

0 5 10 15 20 25 30

Efficienc y ver sus Output Power

RL = 8Ω

RL = 4Ω

Output Power (W)

VDD = 13.5V
f = 1kHz
Av = 12V/V

Intermodulation Performance

+0

VDD = 13.5V

-10
Pout = 1W/Channel

VDD = 13.5V
RLoad = 4W

Pout = 1W/Channel
19kHz, 20kHz, 1:1

-20

RLoad = 4W
0dBr = 12Vrms

19kHz, 20kHz, 1:1
Av = 12

0dBr = 12Vrms

-30
BW = 10Hz - 80kHz

Av = 12V/V
BW = 10Hz - 80kHz

-40

-50

FFT (dBr)

-60

-70

-80

-90

-100

50 30k

1k

2k 5k

10k

Frequency (Hz)

+0

Channel Separation versus Frequency

-10
VDD = 13.5V
Pout = 1W/Channel

-20
RLoad = 4Ω

Av = 12V/V

-30
BW = 22Hz - 22kHz

-40

-50

-60

-70

Channel Separation (dBr)

-80

-90

-100
20 20k50 100 200 500 1k 2k 5k 10k

+0

-10

VDD = 13.5V

-20

Pout = 0W
Av = 12V/V

-30

RLoad = 4Ω

-40

BW = 20Hz - 22kHz
A-Weighted Filter

-50

-60

-70

-80

-90

-100

Noise FFT (dBV)

-110

-120

-130

-140

20k

-150

20

50 100 200 500 1k 2k 5k 10k

Frequency (Hz)

Noise Floor

Frequency (Hz)

20k

10

THD+N versus Frequency

VDD = 13.5V

5

Pout = 5W/Channel
Av = 12V/V

2

BW = 22Hz - 22kHz

1

0.5

0.2

0.1

THD+N (%)

0.05

0.02

0.01

10 20k20 50 100 200 500 1k 2k 5k 10k

RL = 4Ω

RL = 8Ω

Frequency (Hz)

+3

VDD = 13.5V

+2.5

Pout = 1W

+2

RLoad = 4Ω
Av = 12V/V

+1.5

+1

+0.5

+0

-0.5

-1

Output Amplitude (dBr)

-1.5

-2

-2.5

-3
10 20k20 50 100 200 500 1k 2k 5k 10k

Frequency Response

Frequency (Hz)

7 TA2020 – KL/7.1/03.05

Tripath Technology, Inc. - Technical Information

APPLICATION INFORMATION

Circuit Board Layout

The TA2020-020 is a power (high current) amplifier that operates at relatively high switching frequencies.
The outputs of the amplifier switch between the supply voltage and ground at high speeds while driving
high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the
amplified audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the
amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output
inductance. To avoid subjecting the TA2020-020 to potentially damaging voltage stress, it is critical to
have a good printed circuit board layout. It is recommended that Tripath’s layout and application circuit be
used for all applications and only be deviated from after careful analysis of the effects of any changes.

The figure below is the Tripath TA2020-020 evaluation board. The most critical components on the board
are the power supply decoupling capacitors. Capacitors, C674 and C451, must be placed right next to
pins 22 (VDD2) and 19 (PGND2) as shown. Similarly, capacitors, C673 and C451B, must be placed right
next to pins 25 (VDD1) and 28 (PGND1) as shown. These power supply decoupling capacitors not only
help reject power supply noise, but more importantly, absorb voltage spikes on the VDD pins caused by
overshoots of the outputs of the amplifiers.

Similarly, schottky diodes, D1, D2, D3 and D4, minimize overshoots with respect to VDD and schottky
diodes, D702, D703, D704 and D728, minimize undershoots with respect to power ground. For maximum
effectiveness, these diodes must be located close to the output pins and returned to their respective VDD
or PGND pins. Diodes D1, D2, D3 and D4 are only required for applications where VDD>13.5V. Voltage
overshoots can also be caused by output inductor flyback during high current switching events such as
shorted outputs or driving low impedances at high levels. If these capacitors and diodes are not close
enough to the pins, electrical overstress to the part can occur, possibly resulting in permanent damage to
the TA2020-020.

The output inductors, L389, L390, L398 and L399 should be placed close to the TA2020-020 without
compromising the locations of the closely placed supply decoupling capacitors and diodes. The purpose
of placing the output inductors close the TA2020-020 output pins is to reduce the trace length of the
switching outputs. Following this guideline will aid in reducing radiated emissions.

8 TA2020 – KL/7.1/03.05

Tripath Technology, Inc. - Technical Information

TA2020 Amplifier Gain

The gain of the TA2020-020 is set by the ratio of two external resistors, R

and RF, and is given by the

I

following formula:

V

O

V

I

R

F

−=

12

R

I

where V

is the input signal level and VO is the differential output signal level across the speaker. Please

I

note that OUTP1 and OUTP2 are 180° out of phase with their corresponding input signals.

20 watts of RMS output power results from an 8.944 V RMS signal across a four-ohm speaker load. If R
= R

, then 20 Watts will be achieved with 0.745 V RMS of input signal.

I

F

OLRMS

Protection Circuits

∗Ω=∗=

)W204()PR(V944.8

The TA2020-020 is guarded against over-temperature and over-current conditions. When the device goes
into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state indicating a fault
condition. When this occurs, the amplifier is muted, all outputs are TRI-STATED, and will float to 1/2 of
V

.

DD

Over-temperature Protection

An over-temperature fault occurs if the junction temperature of the part exceeds approximately 155°C. The
thermal hysteresis of the part is approximately 45°C, therefore the fault will automatically clear when the
junction temperature drops below 110°C.

Over-current Protection

An over-current fault occurs if more than approximately 7 amps of current flows from any of the amplifier
output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is
shorted to ground. An over-current fault sets an internal latch that can only be cleared if the MUTE pin is
toggled or if the part is powered down. Alternately, if the MUTE pin is connected to the FAULT pin, the
HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset the fault condition.

Overload

The OVERLOADB pin is a 5V logic output. When low, it indicates that the level of the input signal has
overloaded the amplifier resulting in increased distortion at the output. The OVERLOADB signal can be
used to control a distortion indicator light or LED through a simple buffer circuit.

Sleep Pin

The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent current
mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the pin to be
pulled up through a large valued resistor (1MΩ recommended, 100KΩ minimum) to V

. To disable

DD

SLEEP mode, the sleep pin should be grounded

9 TA2020 – KL/7.1/03.05

(

)

−

(

)

−

Tripath Technology, Inc. - Technical Information

Fault Pin

The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These
conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over current at
any output, and junction temperature greater than approximately 155°C. The FAULT output is capable of
directly driving an LED through a series 2KΩ resistor. If the FAULT pin is connected directly to the MUTE
input an automatic reset will occur in the event of an over-current condition.

Heat Sink Requirements

In some applications it may be necessary to fasten the TA2020-020 to a heat sink. The determining factor
is that the 150°C maximum junction temperature, T

(max) cannot be exceeded, as specified by the

J

following equation:

TT

P

DISS

=

θ

A)MAX(J

JA

where…

= maximum power dissipation

P

DISS

T

= maximum junction temperature of TA2020-020

JMAX

T

= operating ambient temperature

A

= junction-to-case thermal resistance of TA2020-020

θ

JC

Example:

What size heat sink is required to operate the TA2020-020 at 20W per channel into a 4Ω load continuously
in a 70ºC ambient temperature?

P

is determined by:

DISS

P

Efficiency =

η =

OUT

P

=

IN

OUT

PPP−

DISSOUT

(per channel) =

P

DISS

P

OUT

P

η

OUT

20

W520

=−=−

8.0

Thus, P

for two channels = 10W

DISS

θ

TT −

DISS

A)MAX(J

=

=

JA

P

10

70150

= 8°C/W

The θ

4.5°C/W is required for this example. In actual applications, other factors such as the average P

of the TA2020-020 in free air is 15°C/W. The θJC of the TA2020-020 is 3.5°C/W, so a heat sink of

JA

with a

DISS

music source (as opposed to a continuous sine wave) and regulatory agency testing requirements will
determine the size of the heat sink required.

10 TA2020 – KL/7.1/03.05

Tripath Technology, Inc. - Technical Information

Performance Measurements of the TA2020-020

The TA2020-020 operates by generating a high frequency switching signal based on the audio input. This
signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an amplified version
of the audio input. The frequency of the switching pattern is spread spectrum in nature and typically varies
between 100kHz and 1MHz, which is well above the 20Hz – 20kHz audio band. The pattern itself does
not alter or distort the audio input signal, but it does introduce some inaudible components.

The measurements of certain performance parameters, particularly noise related specifications such as
THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the
bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just
beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible
noise components introduced by the TA2020-020 amplifier switching pattern will degrade the
measurement.

One feature of the TA2020-020 is that it does not require large multi-pole filters to achieve excellent
performance in listening tests, usually a more critical factor than performance measurements. Though
using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when
they are made with wide-bandwidth measuring equipment), these same filters degrade frequency
response. The TA2020-020 Evaluation Board uses the Application/Test Circuit of this data sheet, which
has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data
sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument.

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PACKAGE INFORMATION

32-pin SSIP Package

Tripath Technology, Inc. - Technical Information

12 TA2020 – KL/7.1/03.05

Tripath Technology, Inc. - Technical Information

Tripath and Digital Power Processing are trademarks of Tripath Technology. Other trademarks referenced in this
document are owned by their respective companies.

Tripath Technology, Inc. reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. Tripath does not assume any liability arising out of the application of use of
any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of
others.

TRIPATH’S PRODUCT ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE PRESIDENT OF TRIPATH
TECHONOLOGY, INC. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance
with instructions for use provided in this labeling, can be reasonably expected to result in significant
injury of the user.

2. A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.

Contact Information

TRIPATH TECHNOLOGY, INC

2560 Orchard Parkway, San Jose, CA 95131

408.750.3000 - P

408.750.3001 - F

For more Sales Information, please visit us @ www.tripath.com/cont_s.htm
For more Technical Information, please visit us @ www.tripath.com/data.htm

13 TA2020 – KL/7.1/03.05