Datasheet TA1101B Datasheet (TRIPATH TECHNOLOGY)

TECHNICAL INFORMATION

Stereo 10W (4ΩΩΩΩ) Class-T™ Digital Audio Amplifier using
Digital Power Processing™ Technology TA1101B

September 2000

General Description

The TA1101B is a 10W continuous average two-channel Class-T Digital Audio Power
Amplifier IC using Tripath’s proprietary Digital Power Processing™ technology. Class-T
amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D
amplifiers.

Applications

!"Computer/PC Multimedia
!"DVD Players
!"Cable Set-Top Products
!"Televisions
!"Video CD Players
!"Battery Powered Systems

Benefits

!"Fully integrated solution with FETs
!"Easier to design-in than Class-D
!"Reduced system cost with no heat sink
!"Dramatically improves efficiency versus

Class-AB

!"Signal fidelity equal to high quality linear

amplifiers

!"High dynamic range compatible with digital

media such as CD, DVD, and Internet audio

Typical Performance

Features

!"Class-T architecture
!"Single Supply Operation
!"“Audiophile” Quality Sound

!"0.04% THD+N @ 9W, 4Ω
!"0.18% IHF-IM @ 1W, 4Ω
!"6W @ 8Ω, 0.1% THD+N
!"11W @ 4Ω, 0.1% THD+N

!"High Power

!"10W @ 8Ω, 10% THD+N
!"15W @ 4Ω, 10% THD+N

!"High Efficiency

!"88% @ 10W, 8Ω

!"81% @ 15W, 4Ω
!"Dynamic Range = 102 dB
!"Mute and Sleep inputs
!"Turn-on & turn-off pop suppression
!"Over-current protection
!"Over-temperature protection
!"Bridged outputs
!"30-pin Power SOP package

10

VDD = 12V
f = 1kHz

5

Av = 12
BW = 22Hz - 22kHz

2

1

0.5

0.2

THD+N (%)

0.1

0.05

0.02

0.01

THD+N versus Output Power

1 2 5 10 20500m

Output Power (W)

RL= 8

RL= 4

Ω

Ω

TA1101B, Rev. 2.2, 08.17.00 1

TECHNICAL INFORMATION

Absolute Maximum Ratings

(Note 1)

SYMBOL PARAMETER Value UNITS

V

DD

T

STORE

T

A

P

DISS

Supply Voltage 16 V
Storage Temperature Range
Operating Free-air Temperature Range
Continuous Total Power Dissipati on Note 2 W

-40

°

0

°

to 150°

to 70°

C
C

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: See Power Dissipation Derating in the Applications Information section.

Operating Conditions

(Note 3)

SYMBOL PARAMETER MIN. TYP. MAX. UNITS

V

DD

V

IH

V

IL

Supply Voltage 8.5 12 13.2 V
High-level Input Voltage (MUTE, SLEEP) 3.5 V
Low-level Input Voltage (MUTE, SLEEP ) 1 V

Note 3: Recommended Operating Conditions indicate conditions for which the device is functional. See
Electrical Characteristics for guaranteed specific performance limits.

Electrical Characteristics

See Test/Application Circuit. Unless otherwise specified, VDD = 12V, f = 1kHz, Measurement
Bandwidth = 22kHz, R

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITS

P

O

I

DD,MUTE

I

DD, SLEEP

I

q

THD + N Total Harmonic Distortion Plus
IHF-IM IHF Intermodulation Dis tortion 19kHz, 20kHz, 1:1 (IHF) 0.18 0.5 %

SNR Signal-to-Noise Ratio
CS Channel Separation 30kHz Bandwidth 50 55 dB
PSRR Power Supply Rejection Ratio Vripple = 100mV. 60 80 dB

η

V

OFFSET

VOH High-level output vol tage
VOL Low-level output voltage
e

OUT

Output Power
(Continuous Average/Channel)

Mute Supply Current MUTE = VIH 5.5 7 mA

Sleep Supply Current SLEEP = VIH 0.25 2 mA

Quiescent Current VIN = 0 V 61 75 mA

Noise

Power Efficiency

Output Offset Voltage No Load, MUTE = Logic Low 50 150 mV

(FAULT & OVERLOAD)
(FAULT & OVERLOAD)

Output Noi se Voltage A-Weighted, input AC grounded 100

Note: Minimum and maximum limits are guaranteed but may not be 100% tested.

= 4Ω, TA = 25 °C, Package heat slug soldered to 2.8 square-inch PC pad.

L

9

THD+N = 0.1% R
R
THD+N = 10% R
R

PO = 9W/Channel 0.04 %

A-Weighted, P

= 10W/Channel, RL = 8Ω

P

OUT

3.5 V
1 V

= 4Ω

L

= 8Ω

L

= 4Ω

L

= 8Ω

L

= 1W, RL = 8Ω

OUT

5.5
12

89 dB

11

6

16

8

10

88 %

W

W
W
W

V

µ

2 TA1101B, Rev. 2.2, 08.17.00

TECHNICAL INFORMATION

Pin Description

Pin

Function

1, 2 DCAP2, DCAP1 Charge pump switchi ng pi ns. DCAP1 (pin 2) is a free running 300kHz square

3, 8 V5D, V5A Digital 5VDC, Analog 5VDC

4, 7,

15

AGND1, AGND2,

AGND3
5 REF Internal reference voltage; approxim at el y 1.0 VDC.
6 OVERLOADB A logic low output indicates t he i nput signal has overloaded the ampl i f i er.

9, 12 VP1, VP2 I nput stage output pins.

10, 13 IN1, IN2 Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with

11 MUTE When set to l ogic high, both amplifiers are muted and in idle mode. When low

14 BIASCAP Input stage bias voltage (approximat el y 2. 4VDC).
16 SLEEP When set to logi c high, device goes into low power mode. I f not used, this pin

17 FAULT A logic hi gh out put indicates thermal overl oad, or an output is shorted to ground,

18, 28 PGND2, PGND1 Power Grounds (hi gh current)

19 DGND Digital Ground

20, 22;

25, 23

OUTP2 & OUTM2;

OUTP1 & OUTM1

21, 24 VDD2, VDD1 Supply pins f or hi gh current H-bridges, nominall y 12V DC.

26 NC Not connected
27 VDDA Analog 12VDC
29 CPUMP Charge pump output (nominally 10V above V DDA)
30 5VGEN Regulated 5VDC source us ed t o supply power to the input section (pins 3 and 8).

Description

wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 1) is level shifted
10 volts above DCAP1 (pin 2) with the same amplitude (12Vpp nom i nal ),
frequency, and phase as DCAP1.

Analog Ground

approximately 2.4VDC bias.
(grounded), both amplifiers are fully operational. If lef t floating, the device s tays in

the mute mode. Ground if not used.

should be grounded
or another output.

Bridged outputs

30-pin Power SOP Package

(Top View)

DCAP2
DCAP1

V5D

AGND1

REF

OVERLOADB

AGND2

V5A
VP1

IN1

MUTE

VP2

IN2

BIASCAP

AGND3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

5VGEN

30

CPUMP

29

PGND1

28

VDDA

27

NC

26

OUTP1

25

VDD1

24

OUTM1

23

OUTM2

22

VDD2

21

OUTP2

20

DGND

19

PGND2

18

FAULT

17

SLEEP

16

TA1101B, Rev. 2.2, 08.17.00 3

TECHNICAL INFORMATION

Application / Test Circuit

4 TA1101B, Rev. 2.2, 08.17.00

TECHNICAL INFORMATION

TA1101B

VDD1

10uH, 2A

D

O

(Pin 28)

D

O

FAULT
OVERLOADB

10uH, 2A

D

O

D

O

+

C

P

1uF
C

S

0.1uF
C

S

0.1uF

C

SW

0.1uF

C

SW

0.1uF

C

2.2uF

(Pin 7)

C

2.2uF

To Pin 30

I

+

I

+

(Pin 7)

+12V

20K

C

0.1uF

1meg

20K

R

I

Ω

A

5V

20K

R

I

20K

8.25KΩ, 1%

0.1uF

Ω

0.1uF

0.1uF

0.1uF

R

F

Ω

BIASCAP

MUTE

R

F

Ω

Ω

R

C

D

C

S

C

S

VP1

IN1

VP2

IN2

REF

10

14

11

12

13

16

9

5

26

15

2

1

3

4
8

7

5V

REF

DCAP1

DCAP2

SLEEP

NC

V5D

AGND1
V5A

AGND2

AGND3

Processing

&

Modulation

Processing

&

Modulation

5V

CPUMP

VDDA

DGND

5VGEN

VDD1

PGND1

VDD2

PGND2

25

PGND1

VDD1

PGND1

17

VDD2

20

PGND2

VDD2

22

PGND2

29

27
19

30

24
28

21

18

23

OUTP1

(Pin 28)

OUTM1

(Pin 28)

6

OUTP2

(Pin 18)

OUTM2

(Pin 18)

L

o

L

o

10uH, 2A

L

o

(Pin 18)

L

o

10uH, 2A

To Pin 3,8

+

C

180uF, 16V

+

180uF, 16V

C

*C

o

0.47uF

*C

o

0.47uF

*C

0.47uF

*C

0.47uF

SW

C

SW

Z

0.47uF
C

CM

0.1uF

R

Z

10

1/2W

Ω,

C

Z

o

0.47uF
C

CM

Ω,

0.1uF

1/2W

(+12V)

R

Z

o

10

VDD

R

L

4Ω or *8

R

L

4Ω or *8

Ω

Ω

Note: Analog and Digital/Power Grounds must
be connected locally at the TA1101B

Analog Ground
Digital/Power Ground
All Diodes Motorola MBRS130T3
* Use Co = 0.22µF for 8 Ohm loads

TA1101B, Rev. 2.2, 08.17.00 5

TECHNICAL INFORMATION

External Components Description

(Refer to the Application/Test Circuit)

Components Description
R

Inverting Input Resistance to provide AC gain in conjunction with RF. This input is biased at

I

the BIASCAP voltage (approximately 2.4VDC).

RF Feedback resistor to set AC gain in conjunction with RI;

=

. Please refer to the

)R/R(12A

IFV

Amplifier Gain paragraph in the Application Information section.

CI AC input coupling capacitor which, in conjunction with RI, forms a highpass filter at

)CR2(1f

π=

IIC

R

Bias resistor. Locate close to pin 5 and ground at pin 7.

REF

CA BIASCAP decoupling capacitor. Should be located close to pin 14.
CD Charge pump input capacitor. This capacitor should be connected directly between pins 1

and 2 and located physically close to the TA1101B.

CP Charge pump output capacitor that enables efficient high side gate drive for the internal H-

bridges. To maximize performance, this capacitor should be connected directly between
pin 29 (CPUMP) and pin 27 (VDDA). Please observe the polarity shown in the Application/
Test Circuit.

CS Supply decoupling for the low current power supply pins. For optimum performance, these

components should be located close to the pin and returned to their respective ground as
shown in the Application/Test Circuit.

CSW Supply decoupling for the high current, high frequency H-Bridge supply pins. These

components must be located as close to the device as possible to minimize supply
overshoot and maximize device reliability. Both the high frequency bypassing (0.1uF) and
bulk capacitor (180uF) should have good high frequency performance including low ESR
and low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor.

CZ

Zobel Capacitor.

RZ Zobel resistor, which in conjunction with CZ, terminates the output filter at high frequencies.

The combination of R

and CZ minimizes peaking of the output filter under both no load

Z

conditions or with real world loads, including loudspeakers which usually exhibit a rising
impedance with frequency.

DO Schottky diodes that minimize undershoots of the outputs with respect to power ground

during switching transitions. For maximum effectiveness, these diodes must be located
close to the output pins and returned to their respective PGND. Please see
Application/Test Circuit for ground return pin.

LO Output inductor, which in conjunction with CO, demodulates (filters) the switching waveform

into an audio signal. Forms a second order filter with a cutoff frequency of

and a quality factor of

π=

)CL2(1f

OOC

=

.

CLCRQ

OOOL

CO Output capacitor.
CCM Common Mode Capacitor.

6 TA1101B, Rev. 2.2, 08.17.00

TECHNICAL INFORMATION

Typical Performance Characteristics

100

90

R

= 8

Ω

80

70

60

50

40

Efficiency (%)

30

20

10

L

RL = 4

Ω

0

0 5 10 15 20

Output Power (W)

Efficiency versus Output Power

+0

VDD = 12V
Pout = 1W/Channel

-10
RLoad = 4

0dBr = 12Vrms

-20

19kHz, 20kHz, 1:1
Av = 11.7
BW = 10Hz - 80kHz

-30

-40

-50

FFT (dBr)

-60

-70

-80

-90

-100
50 30k1k 2k 5k 10k 20k

Intermodulation Performance

Ω

Frequency (Hz)

10

VDD = 12V

5

Pout = 5W/Channel
Av = 12

2

BW = 22Hz - 22kHz

1

0.5

0.2

THD+N (%)

0.1

0.05

0.02

0.01
10 20k20 50 100 200 500 1k 2k 5k 10k

THD+N versus Frequency

RL = 4

Ω

Frequency (Hz)

RL = 8

VDD = 12V
f = 1kHz
Av = 12
THD+N < 10%

Ω

Frequency Response

+3

+2.5

VDD = 12V
Pout = 1W

+2

RLoad = 4

Ω

Av = 12

+1.5

BW = 22Hz - 22kHz

+1

+0.5

+0

-0.5

-1

-1.5

Output Amplitude (dBr)

-2

-2.5

-3
10 20k20 50 100 200 500 1k 2k 5k 10k

Frequency (Hz)

Noise Floor

+0

VDD = 12V
Pout = 0W

-20
RLoad = 4

Ω

Av = 12
BW = 22Hz - 22kHz

-40

A-Weighted Filter

-60

-80

Noise FFT (dBV)

-100

-120

-140

20 20k50

100

200 500 1k 2k 5k 10k

Frequency (Hz)

Channel Separation versus Frequency

+0

-10

VDD = 12V
Pout = 1W/Channel
RLoad = 4

-20

-30

-40

-50

-60

-70

Channel Separation (dBr)

-80

-90

-100
20 20k50 100 200 500 1k 2k 5k 10k

Ω

Av = 12
BW = 22Hz - 22kHz

Frequency (Hz)

TA1101B, Rev. 2.2, 08.17.00 7

TECHNICAL INFORMATION

Application Information

Layout Recommendations
The TA1101B is a power (high curr ent) am plifier that operates at relatively high switching frequencies. The

outputs of the am plifier switch between the supply voltage and ground at high speeds while driving high
currents. This high-f requency digital signal is pass ed through an LC low-pass f ilter to recover the am plified
audio signal. Since the amplifier m ust drive the inductive LC output filter and speak er loads, the amplifier
outputs can be pulled above the supply voltage and below ground by the energy in the output inductance.
To avoid subjecting the T A1101B to potentially damaging voltage stres s, it is critic al to have a good printed
circuit board layout. It is recommended that Tripath’s layout and application circuit be used for all
applications and only be deviated from after careful analysis of the effects of any changes.

The figure below is the Tripath T A1101B evaluation board. Some of the m ost critical com ponents on the
board are the power supply decoupling capacitors. C7 and C18 must be placed right next to pins 24 and
28 as shown. C8 and C19 must be placed right next to pins 21 and 18 as shown. These power supply
decoupling capacitors from the output stage not only help reject power supply noise, but they also absorb
voltage spikes on the VDD pins caused by overshoots of the outputs of the amplifiers . Output overshoots
include those caused by output inductor flyback during high current switching events such as shorted
outputs or driving low im pedances at high levels. If the supply capacitors are not close enough to the
pins, electrical overstress to the part can occur fr om the voltage spikes on the VDD pins. This may result
in permanent damage or destruction to the TA1101B.

The copper slug of the T A1101B must be soldered onto the PC board. T his board uses a 5 x 16 array of

0.013” vias on the copper below the TA1101 that allow the heat to conduct to 4 sq. in. of copper on the
bottom side ground plane of the PC board.

8 TA1101B, Rev. 2.2, 08.17.00

TECHNICAL INFORMATION

Amplifier Gain
The gain of the TA1101B is set by the ratio of two external resistors, R

following formula:

V

O

V

R

F

12

=

I

R

I

where VI is the input signal level and VO is the differential output signal level across the speaker.
9 Watts of RMS output power results from an 8.485V RMS signal across an 8Ω speaker load. If

= RI, then 9 Watts will be achieved with 0.707V RMS of input signal.

R

F

)W98()PR(V485.8

OLRMS

∗Ω=∗=

Protection Circuits
The TA1101B is guarded against over- temperature and over-current conditions. W hen the device goes

into an over-temperature or over- current state, the FAULT pin goes to a logic HIGH state indicating a fault
condition. W hen this occurs, the amplifier is m uted, all outputs are TRI-STATED, and will float to 1/2 of
V

.

DD

Over-temperature Protection
An over-temperature fault occurs if the junction temperature of the part exceeds approximately 155°C.

The thermal hysteresis of the part is approximately 45°C, therefore the fault will automatically clear when
the junction temperature drops below 110°C.

Over-current Protection
An over-current fault occur s if more than approxim ately 7 amps of current flows fr om any of the amplifier

output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is
shorted to ground. An over-current fault sets an internal latch that can only be cleared if the MUT E pin is
toggled or if the part is powered down. Alternately, if the MUTE pin is connected to the FAULT pin, the
HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset the fault condition.

Overload
The OVERLOADB pin is a 5V logic output. W hen low, it indicates that the level of the input signal has

overloaded the amplif ier resulting in increased distor tion at the output. The OVERLOADB signal can be
used to control a distortion indicator light or LED through a simple buffer circuit, as the OVERLOADB
cannot drive an LED directly.

and RF, and is given by the

I

TA1101B, Rev. 2.2, 08.17.00 9

TECHNICAL INFORMATION

Sleep Pin
The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent current

mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the pin to be
pulled up through a large valued resistor (1MΩ recommended) to V

. To disable SLEEP mode, the sleep

DD

pin should be grounded.
Fault Pin
The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These

conditions include: low supply voltage, low char ge pump voltage, low 5V regulator voltage, over c urrent at
any output, and junction temperature gr eater than approximately 155°C. All faults except overcurr ent all
reset upon removal of the c ondition. The FAULT output is capable of directly driving an LED through a
series 200Ω resistor. If the FAULT pin is connected directly to the MUTE input an automatic reset will
occur in the event of an over-current condition.

Power Dissipation Derating
For operating at ambient temperatures above 25°C the device must be derated based on a 150°C

maximum junction temperature, T

)TT(

−

AJMAX

P

DISS

=

θ

JA

as given by the following equation:

JMAX

Where

of the package is determined from the following graph:

θ

JA

vs Copper Ar ea

ΘΘΘΘ

JA

50

40

C/W)

o

30

(

JA

20

10

0123456

Copper Area (square inches)

Pdiss - 1.35W
Pdiss - 2W
Pdiss - 3.4W

In the above graph Copper Area is the size of the copper pad on the PC board to which the heat slug of
the TA1101B is soldered. The heat slug m ust be soldered to the PCB to increase the maximum power
dissipation capability of the TA1101B package. Soldering will minimize the likelihood of an over­temperature fault occurring during continuous heavy load conditions. The vias used for connecting the
heatslug to the copper area on the PCB should be 0.013” diameter.

10 TA1101B, Rev. 2.2, 08.17.00

TECHNICAL INFORMATION

Performance Measurements of the TA1101B
The TA1101B operates by generating a high frequency switching signal based on the audio input. This

signal is sent through a low-pass filter ( external to the Tr ipath amplifier ) that recovers an am plified version
of the audio input. The frequency of the switching pattern is spread spectr um and typically varies between
100kHz and 1.0MHz, which is well above the 20Hz – 20kHz audio band. The pattern itself does not alter
or distort the audio input signal but it does introduce some inaudible components.

The measurements of certain performance parameters, particularly noise related specifications such as
THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the
bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just
beyond the audio band or the bandwidth of the measurement instrum ent is limited, some of the inaudible
noise components introduced by the Tripath amplifier switching pattern will degrade the measurement.

One feature of the TA1101B is that it does not require large multi-pole filters to achieve excellent
performance in listening tests, usually a more critical factor than performance measurements. Though
using a multi-pole filter may remove high-f requency noise and improve T HD+N type measurements (when
they are made with wide-bandwidth measuring equipment), these same filters degrade frequency
response. The TA1101B Evaluation Board us es the Test/Application Circuit in this data sheet, which has a
simple two-pole output filter and excellent per form ance in listening tes ts. Measurem ents in this data sheet
were taken using this same circuit with a limited bandwidth setting in the measurement instrument.

TA1101B, Rev. 2.2, 08.17.00 11

TECHNICAL INFORMATION

Package Information

30-Lead Power Small Outline Package (PSOP),
compliant with JEDEC outline MO-166, variation AD:

E2

2 PLACES

2.24

3 2 1

E

E1

30

E3

3.10

REF.

D2

2 PLACES

TOP VIEW BOTTOM VIEW

SEE DETAIL "A"

D

3.35

REF.

e b

L1

GAUGE PLANE

0.15 REF.

L

1.60 REF

c

4º +/- 4º

D1

3.15 +/- 0.15

END VIEWSIDE VIEW

0.20 +/- 0.10

DETAIL "A"

12 TA1101B, Rev. 2.2, 08.17.00

TECHNICAL INFORMATION

Package Dimensions

Dimension Min. Nom. Max.

b 0.35 --- 0.48

c 0.23 --- 0.32

D 15.80 15.90 16.00
D1 12.60 --- 13.00
D2 --- --- 1.10

E 13.90 14.20 14.50
E1 10.90 11.00 11.10
E2 --- --- 2.90
E3 5.80 --- 6.20

e 0.80 BSC.
L1 0.25 BSC.

L 0.70 --- 1.00

Note: All dimensions are in millimeters.

Tripath, Class T, Combinant Digital, DPP and Digital Power Processing are trademarks of Tripath
Technology Inc. Other trademarks referenced in this document are owned by their respective companies

Tripath Technology Inc. reserves the right to m ak e changes without further notice to any products herein to
improve reliability, function or design. Tripath does not as sume any liability arising out of the application or
use of any product or c ircuit described herein; neither does it convey any license under its patent rights,
nor the rights of others.

TRIPATH’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITOUT THE EXPRESS WRITTEN CONSENT OF THE
PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose failure to perform, when properly used in
accordance with instruc tions for use provided in this labeling, can be reasonably expected to result in
significant injury to the user.

2. A critical component is any com ponent of a life suppor t device or system whose failure to perform can
be reasonably expected to cause the failure of the life support device or s ystem, or to affect its safety
or effectiveness.

For more information on Tripath products, visit our web site at:

www.tripath.com
TRIPATH TECHNOLOGY, INC.

3900 Freedom Circle
Santa Clara, California 95054
408-567-3000

.

TA1101B, Rev. 2.2, 08.17.00 13