Page 1
Advisory
July 2001
T8302 Internet Protocol Telephone Advanced RISC Machine
(
ARM
®
) Ethernet QoS Using
Description
IEEE
®
802.1q
The Agere Systems, Inc. Voice over Internet Protocol (VoIP)
ments a quality of service (QoS) strategy that uses a proprietary voice packet prioritization scheme called
Ethernet Quality of Service using BlackBurst (EQuB). This scheme uses an algorithm (implemented in hard-
ware) to ensure that voice packets transmitted from the device are given the highest priority on their collision
domain.
Phone-On-A-Chip
The
incorporates a software-based
mentation will utilize an
VxWorks
area network (VLAN) tag insertion will be supported on a per-port, per-socket, and global basis.
Note: As a result of migrating to this software/standards-based priority scheme, Agere will no longer support
Customers using the
ment and should structure their application software accordingly (to incorporate the features provided by the
IEEE
It is hoped that this migration will aid customers of Agere in implementing their own systemwide QoS mechanism when designing their end product into an IP network.
Additional information may be obtained at the T8300
®
board support package (BSP) for the T8302 as part of our standard software solution. Virtual local
its current proprietary hardware-based EQuB scheme.
802.1q stack).
solution will now become more standards based by implementing a QoS strategy that
IEEE
802.1q tagging protocol for outgoing Ethernet frames. This QoS imple-
IEEE
802.1q protocol stack from
Phone-On-A-Chip
IP Solution Development Design Kit should be aware of this enhance-
Phone-On-A-Chip
http://www.agere.com/phone_chip
Phone-On-A-Chip
Wind River Systems
website:
™ solution currently imple-
®
and will be integrated into the
Page 2
ARM
is a registered trademark of Advanced RISC Machines Limited.
IEEE
is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Wind River Systems
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET: http://www.agere.com
E-MAIL: docmaster@micro.lucent.com
N. AMERICA:Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
ASIA PACIFIC:Agere Systems Singapore Pte. Ltd., 77 Science Park D rive, #03-18 Cinte ch III, Singa po re 118256
CHINA: Agere Systems (Shanghai) Co., Ltd . , 33/F Jin Mao Tower, 88 Century Boulevard Pudong, Shanghai 200121 PRC
JAPAN: Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
EUROPE: Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Phone-On-A-Chip
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
and
VxWorks
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
Tel. (65) 778 8833, FAX (65) 777 7495
Tel. (86) 21 50471212, FAX (86) 21 50472266
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
Technical Inquiries:GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
is a trademark of Agere Systems, Inc.
are registered trademarks of Wind River Systems, Inc.
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 3507670 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
July 2001
AY01-026IPT (Must accompany DS01-213IPT)
Page 3
Data Sheet
July 2001
T8302 Internet Protocol Telephone
Advanced RISC Machine (ARM *)
1 Introduction
Agere Systems’ Phone-On-A-Chip™ IP Solution is a highly-integrated device set that forms the basic building
blocks for an internet protocol telephone (IPT), residing on a local area network (LAN).
At this time, the IPT consists of two individual ICs, the T8302 IPT_ARM (advanced RISC machine) and the com-
panion T8301 IPT_DSP (digital signal processor). This two-device solution comprises the basis for a single-IC
integration of the system in the near future. The single-IC implementation will contain the functions of both IPT ICs.
For conceptual objectives, features for both ICs are listed in this document.
The general-purpose processor IC (IPT_ARM ) controls the system I/O (Ethernet, USB, IrDA, etc.) and provides
general telephone control features (LED control, keypad button scanning, LCD module interface, etc.).
A block diagram of the IPT_ARM can be found in Figure 2 on page 27.
At the heart of the IPT_DSP integrated circuit is Agere Systems’ DS P 1627 digital signal processor core. The
DSP1627’s high-performance (80 MIPS) and single-cycle multiply accumulate instruction provide excellent support
for execution of voice compression/decompression and echo cancellation algor ithm s. The DSP1627 core and the
digital-to-analog (D/A), analog-to-digital converters (A/D), low-pass filters, and audio amplifier circuitry drive standard business telephone handsets and speakerphone hardware.
This document describes the gene ral-purpose processor IC T8302 for the IP phone. Throughout this discussion
the IC will be referred to simply as IPT_ARM.
* ARM is a registered trademark of Advanced RISC Machines Limited.
Page 4
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
Table of Contents
Contents Page
1 I ntroduction ...........................................................................................................................................................1
1.1 PT_ARM Features ........................................................................................................................................15
1.2 IPT_DSP Featur e s ..... .................................................................................................................................. 16
2 Pinout Information ...............................................................................................................................................17
2.1 272-Pin PBG A Pin Diag r a m .........................................................................................................................17
2.2 Pin List ..... ..................................................................................................................................................... 18
3 Overview .............................................................................................................................................................26
3.1 ARM 940T and AMBA Bridge .......................................................................................................................28
3.2 IPT_ARM Memory and I/O Map ...................................................................................................................28
4 Reset/Clock Management ..................................................................................................................................29
4.1 Reset/Clock Management Controller Theory of Operation ...........................................................................31
4.1.1 Reset Operation ..................................................................................................................................31
4.1.2 Operation of the Clock Switching Logic ..............................................................................................32
4.1.2.1 PLL Operation .........................................................................................................................32
4.1.3 Latency ................................................................................................................................................33
4.1.4 Real-Time Clock (RTC) ....................................................................................................................... 33
4.2 Reset/Clock Management Registers ..................................... ............ ..... ....... ....... ....... ....... ....... ...................35
4.2.1 Pause Register .................................................................................................................................... 35
4.2.2 Version ID Register .............................................................................................................................36
4.2.3 Clock Management Register ...............................................................................................................36
4.2.4 Clock Status Register ..........................................................................................................................37
4.2.5 System Clock Source Encoding ..........................................................................................................38
4.2.6 Clock Control Register ........................................................................................................................38
4.2.7 Soft Reset Register ............................................................................................................................. 38
4.2.8 PLL Control Register ...........................................................................................................................39
4.2.9 Reset Status (Control/Clear) Registers ...............................................................................................40
4.2.10 Reset Peripheral Control (Read, Clear, Set) Registers .....................................................................40
4.2.11 RTC External Divider Register ........................................................... ...............................................41
4.2.12 RTC Clock Prescale Registers ....... ..................................................................... ..............................42
4.2.13 RTC Control Register ......... ........................................................................................ .......................43
4.2.14 RTC Seconds Alarm Register ......................................... ..... .. ..... .. ....... ..... ..... .. ..... .. ..... .. ..... ..............44
4.2.15 RTC Seconds Count Register ...................... ..... .. ....... ..... ..... ....... .. ..... ....... ..... .. ..... ....... .. ..... ..............44
4.2.16 RTC Divider Regi ster .................................................... ....................................................................44
4.2.17 RTC Interrupt Status Register .......... .................................................................................................45
4.2.18 RTC Interrupt Enable Register ........................................ ..... .. ..... .. ..... .. ..... ..... .. ..... .. ..... .. ................... 45
4.3 Operation on Reset ......................................................................................................................................46
5 Programmable Interrupt Controller (PIC) ............................................................................................................ 47
5.1 Interrupt Controller Operation .......................................................................................................................47
5.1.1 Interrupt Registers ............................................................................................................................... 48
5.2 Programmable Interrupt Controller Registers ...............................................................................................50
5.2.1 Interrupt Request Status Register IRSR .............................................................................................51
5.2.2 Interrupt Request Enable Registers IRER (Set, Clear) .. .....................................................................51
5.2.3 Interrupt Request Soft Register IRQSR ..............................................................................................52
5.2.4 Interrupt Priority Control Registers IPCR[15:1] ................................................................................... 52
5.2.5 Interrupt In-Service Registers ISR (ISRI, ISRF) ..................................................................................53
5.2.6 Interrupt Request Source Clear Register IRQESCR ...........................................................................53
5.2.7 Interrupt Priority Enable Registers IPER (Set, Clear) .........................................................................54
5.2.8 External Interrupt Control Registers ....................................................................................................55
6 Programmable Direct Memory Access (DMA) Controller ........ ................................................. .......................... 56
6.1 DMA Operation ............................................................................................................................................. 56
2 Agere Systems Inc.
Page 5
Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
Table of Contents
(continued)
Contents Page
6.1.1 DMA Transfer Setup Procedure ..........................................................................................................57
6.1.2 DMA Mode 0. Memory-to-Memory in Blocks of Burst Count Size ............... ... .. .. ..... ... .. .. ..... .. ..... ... .. .. .58
6.1.3 Mode 1. Peripheral-to-Memory in Blocks of Burst Count Size ............................................................58
6.1.4 Mode 2. Memory-to-Peripheral in Blocks of Burst Count Size ............................................................59
6.1.4.1 Software-Triggered DMA Mode ..............................................................................................60
6.2 DMA Registers ..............................................................................................................................................61
6.2.1 DMA Control Registers for Channels [0:3] ..........................................................................................62
6.2.2 DMA Source Address Registers for Channels [0:3] . ........................................................................... 63
6.2.3 DMA Preload Destination Start Address Registers for Channels [0:3] ...............................................64
6.2.4 DMA Preload Transfer Count Registers for Channels [0:3] ................................................................65
6.2.5 DMA Transfer Count Registers for Channels [0:3] ..............................................................................65
6.2.6 DMA Burst and Hold Count Registers .................................................................................................65
6.2.7 DMA Status Register ...........................................................................................................................66
6.2.8 DMA Interrupt Register .......................................................................................................................68
6.2.9 DMA Interrupt Enable Register ...........................................................................................................68
7 Programmable Timers ........................................................................................................................................70
7.1 Timers Operation ............ ..............................................................................................................................70
7.2 Interv al Ti mer ( IT ) .........................................................................................................................................70
7.3 Watchdog Timer ........................... ................................................................................................................71
7.4 Timer Regist e r s ............................................................................................................................................73
7.4.1 Count Rate Register ............................................................................................................................74
7.4.2 Encoding of Interval Timer Count Rates (ITR) and Watchdog Timer Count Rates (WTR) .................74
7.4.3 WT Timer Count Regis te r ..... ..............................................................................................................75
7.4.4 Timer Status Register .........................................................................................................................75
7.4.5 Timer Interrupt Mask Register .............................................................................................................75
7.4.6 Timer Control Register ........................................................................................................................76
7.4.7 IT Count Registers ..............................................................................................................................77
8 External Memory Interface (EMI) ........................................................................................................................78
8.1 IPT_ARM Processor Memory Map ........ ................................................................................................. ......78
8.2 External FLASH/SRAM Memory Interface (EMI FLASH) ..... ........................................................................ 78
8.3 EMI FLASH Memory Access ........................................................................................................................78
8.3.1 External Write ......................................................................................................................................78
8.3.2 External Read .....................................................................................................................................79
8.3.3 Wait-States ..........................................................................................................................................79
8.3.4 Hold State ...........................................................................................................................................79
8.3.5 Hold Disable ........................................................................................................................................79
8.3.6 Error Conditions ..................................................................................................................................79
8.4 ROM/RAM Remapping .................................... .. ..... ....... ..... .. ..... .. ..... ....... ..... .. ..... .. ..... ....... ... ........................83
8.4.1 Programmable Addresses ...................................................................................................................83
8.5 EMI FLASH Registers ...................................................................................................................................84
8.5.1 Chip Sele ct Configuration Registe r FLASH_CS .................................................................................84
8.5.2 Chip Sele ct Configuration Registe rs CS1 , CS2 , CS 3 .................................................................... .....85
8.5.3 Hold and Wait-States Encoding ........ ..................................................................................................87
8.5.4 Chip Sele ct Ba se Addre ss Regi sters FLASH_CS, CS1, CS2, CS3, Intern a l SRAM ..................... .....87
8.5.5 Block Size Field Encoding ................................................................................................................... 88
8.5.6 Status Register ....................................................................................................................................88
8.5.7 Options Register .................................................................................................................................89
8.6 External SDRAM Memory Interface ..............................................................................................................89
8.6.1 Exter n a l SDRAM Memory Map ...........................................................................................................89
8.6.2 SDRAM Memory Range Base Address Register ................................................................................ 90
Agere Systems Inc. 3
Page 6
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
Table of Contents
(continued)
Contents Page
8.6.3 SDRAM Control Register ....................................................................................................................90
8.6.4 SDRAM Timing and Configuration Register ........................................................................................90
8.6.5 SDRAM Manual Access Register .......................................................................................................91
8.7 SDRAM Timing ....... ......................................................................................................................................92
8.8 Signals ..........................................................................................................................................................94
8.8.1 Address, A[23:0] .................................................................................................................................. 94
8.8.2 Data, D[15:0] ....................................................................................................................................... 94
8.8.3 Byte Enable, BE1N .............................................................................................................................94
8.8.4 Read/Write Signals, RDN, WRN .........................................................................................................94
8.8.5 Chip Sele cts, FLASH_CS, CS1, CS2, CS3 ........................................................................................94
8.8.6 External WAIT, EXWAIT .....................................................................................................................94
8.8.7 EMI SDRAM, Synchronous DRAM Memory Interface ........................................................................95
8.8.8 SDRAM Address Functionality ............................................................................................................95
8.8.9 SDRAM Clock, SDRCK .......................................................................................................................95
8.8.10 SDRASN, SDCASN, SDWEN .......... ............................................................ ............................ .........95
8.8.11 SDUDQM, SDLDQM ................................................................... ......................................................95
9 DSP Communications Controller (DCC) ........................................... ..................... ...................... ....................... 96
9.1 ARM Processor Memory a nd I/O Ma p .........................................................................................................96
9.2 DCC Token Register ............ .............................. ......................................... .................................................97
9.3 DCC Interrupt Registers ...............................................................................................................................97
9.3.1 DSP2ARM Interrupt Register ..............................................................................................................98
9.3.2 ARM 2DSP Interrupt Regist e r .............................................................................................................98
9.4 DCC Controller I/O Signals ...........................................................................................................................99
9.5 DSP Read/Write Ti mi n g Diag ra ms ........................................... ....................................................................99
10 Ethernet 10/100 MAC ....................................................................................................................................101
10.1 Features .................................................................................................................................................102
10.2 General MAC Information ............................................... .. .......... .. ....... ..... .. .......... .. ....... ........................102
10.3 MAC Transmitter ....................................................................................................................................1 03
10.4 MAC Receiver ........................................................................................................................................ 1 03
10.4.1 Addre ss Match ing Registers .......................................................................................................103
10.5 MAC Controller, Regi sters, and Counters ...... ..................................................................... ...................1 04
10.6 Control Frame Operation .......................................................................................................................104
10.7 Register Descriptions .............................................................................................................................106
10.7.1 MAC Controller Setup Register ...................................................................................................106
10.7.2 MAC Packet Delay Al a r m Value Register ............ .......................................................................108
10.7.3 MAC Controller Interrupt Enable Register .......................... ..... .. ..... ....... ..... .. ..... .. ..... ....... ..... .. .....108
10.7.4 MAC Control Frame Destination Address Registers ................................................................... 1 09
10.7.5 MAC Control Frame Source Address Registers ..........................................................................1 09
10.7.6 MAC Control Frame Length/Type Register ................................................................................. 110
10.7.7 MAC Control Frame Opcode Register ........ .................................................................... ............110
10.7.8 MAC Control Frame Data Register ..... ............................................................ ............................1 11
10.7.9 VLAN Type1 Type/Length Field Register ....................................................................................111
10.7.10 VLAN Type2 Type/Length Field Register ..................................................................................111
10.7.11 MAC Transmit FIFO Register ....................................................................................................111
10.7.12 MAC Receive FIFO Register ................................................................................ .....................112
10.7.13 MAC Receive Control FIFO Register ........................................................................................112
10.7.14 MDIO Address Register ............................................................................................................1 14
10.7.15 MDIO Data Reg ister ........ ..........................................................................................................114
10.7.16 MAC PHY Powerdown Regi ste r ........................................................ ........................................115
10.7.17 MAC Contro ll e r Tra n smi t Control Register ................................................................................115
4 Agere Systems Inc.
Page 7
Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
Table of Contents
(continued)
Contents Page
10.7.18 MAC Contro ll e r Tran smi t Start Register ....................................................................................116
10.7.19 MAC Transmi t Status Register ..................................................................................................116
10.7.20 MAC Collision Counter ..............................................................................................................118
10.7.21 MAC Packet Delay Coun ter ................................................. .....................................................118
10.7.22 MAC Transmitted Packet Counter .............................................................................................118
10.7.23 MAC Transmitted Single Collision Counter ...............................................................................118
10.7.24 MAC Transmitted Multiple Collision Counter .............................................................................119
10.7.25 MAC Excess Collision Counter ...... .............................................................................. .............119
10.7.26 MAC Packet Deferred Counter ............................................................. ....... ..... ..... .. ....... ...........1 19
10.7.27 MAC Contro ll e r Receive Control Register ........................................................... ......................119
10.7.28 MAC FIFO Sta tu s Register ........ ................................................................................................120
10.7.29 MAC Contro ll e r Inte r r u p t Status Register ........................................... .......................................120
10.8 Signal Information ..................................................................................................................................121
10.8.1 MII MAC I/O Signals ....................................................................................................................121
11 10/100 2-Port Repeater and Backplane Segment Controller .........................................................................123
11.1 MII Transmit and Rec eive In te r face .......................................................................................................124
11.1.1 Repeater Slice Interface ..............................................................................................................1 24
11.1.2 PHY Interface ..............................................................................................................................124
11.1.3 Backpl a n e Interface ....... ..............................................................................................................125
11.1.3.1 MAC Interface ............................................................................................................... 1 25
11.1.4 Receiv e Path ...............................................................................................................................1 26
11.1.5 Transm it Path .............................................................................................................................. 1 26
11.2 Input Clocks ...........................................................................................................................................126
11.3 Repeater Slice Theory of Operation .......................................................................................................126
11.3.1 Repeat er Core .............................................................................................................................126
11.3.2 10/100 Mbits/s Operation ............................................................................................................ 1 26
11.3.3 Colli sions ......................................................................................... ............................................1 27
11.3.4 Partition and Isolate .................................................................................................. ...................127
11.3.4.1 Partitioning ....................................................................................................................1 27
11.3.4.2 MAU Jabber Lockup Protection (MJLP) ........................................................................1 27
11.3.4.3 Receive Jabber ............................................................................................................. 1 27
11.3.4.4 Isolate on an Incorrect Clock Frequency ... ....................................................................128
11.3.4.5 Automatic Speed Mismatch Protectio n .........................................................................1 28
11.3.5 Carrier Integrity Monitor ...............................................................................................................128
11.4 Repeater Slice Interfaces . ...................................................................................................................... 1 29
11.4.1 Repeater Slice ARM Interface .....................................................................................................129
11.4.2 Repeater Slice Interface .............................................................................................................129
11.4.3 Repeater Slice Input Clocks ........................................................................................................1 31
11.4.4 Backplane Segment 10/100 Mbits/s Serial Mac Interface Port B ................................................ 1 32
11.5 Repeater Slice Register Map ................................................................................................................. 1 33
11.5.1 Global Maximum Frame Size Register ........................................................................................134
11.5.2 Global Configuration Register .................................................. ....... ....... ....... .......... .. ....... ...........135
11.5.3 Port Control Registers, for Port 0, 1 ............................................................................................1 36
11.5.4 Port Configuration Register 0 for Port 0, 1 .................................................................................. 1 36
11.5.5 Port Configuration Registe r 1, for Po rt 0, 1 ................................... ..............................................1 38
11.5.6 Global Interrupt Enable Register .................................................................................................139
11.5.7 Global Interrupt Status Register ..................................................................................................140
11.5.8 Global Port Status Register, for Port 0, 1 ....................................................................................141
12 Ethernet 10/100 PHY(s) .................................................................................................................................142
12.1 10 Mbits Transceive r Fea tu r e s ...............................................................................................................142
Agere Systems Inc. 5
Page 8
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
Table of Contents
(continued)
Contents Page
12.2 100 Mbits/s Transceiver Features ..........................................................................................................1 42
12.3 General Features ...................................................................................................................................1 43
12.4 Signal Information ..................................................................................................................................143
12.4.1 MII/5-Bit Serial Interface Signals .................................................................................................143
12.4.2 10/100 Mbits/s Twisted Pair (TP) Interface Signals ....................................................................145
12.4.3 Status Signals .............................................................................................................................146
12.4.4 Clock and Reset Signals .............................................................................................................146
12.5 MII Station Management . ....................................................................................................................... 1 46
12.5.1 MII Management Frame Format ..................................................................................................147
12.5.2 Summary of Management Registers ................................................................. ......... .......... .......148
12.5.3 MR0 Contr ol Regi ster Bit Description ......................................................................... .................1 49
12.5.4 MR1 Status Register Bit Description ...........................................................................................150
12.5.5 MR2 MR3 PHY Identifier Registers (1 and 2) Bit Description .....................................................150
12.5.6 MR4 Autonegotiation Advertisement Register Bit Description ....................................................1 51
12.5.7 MR 5 Au ton egotiati o n L ink Par t n er Ability (Bas e Page) Re gis ter Bit Descr iption ......... .. .. . .... .. . .. .151
12.5.8 MR5 Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Description .................152
12.5.9 MR6 Autonegotiation Expansion Register Bit Description ..........................................................152
12.5.10 MR7 Next Page Transmit Register Bit Description ..................................................................1 53
12.5.11 MR16 PCS Control Register Bit Description .............................................................................153
12.5.12 MR17 Autonegotiation (Read Register A) .................................................................................154
12.5.13 MR18 Autonegotiation (Read Register B) .................................................................................154
12.5.14 MR21 RXER Count e r ................................................................................................................155
12.5.15 MR28 Device-Specific Register 1 (Status Register) Bit Description .........................................155
12.5.16 MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description ...................................156
12.5.17 MR30 Device-Specific Register 3 (10 Mbits/s Control) Bit Description ..................................... 1 57
12.5.18 MR31 Device-Specific Register 4 (Quick Status) Bit Description ..............................................158
13 USB Host Controller .......................................................................................................................................161
13.1 Description ............................................................................................................................................. 1 61
13.2 USB Registers .......................................................................................................................................162
13.2.1 USB Operational Registers Summary .................................................................................... .....163
13.3 The Control and Status Partition ............................................................................................................163
13.3.1 Hc Revision Register ...................................................................................................................1 63
13.3.2 Hc Control Regi ster ........................................................................ ............................ .................164
13.3.3 Hc Command Stat u s Regi ste r .....................................................................................................1 66
13.3.4 Hc Interr u p t Sta tus Register ......... ...............................................................................................167
13.3.5 Hc Interrupt Enable Register ................................................... ....... .. ............ ..... ....... ....... ............169
13.3.6 Hc Interr u p t Dis able Register .......... ............................................................................................1 70
13.4 Memory Pointer Partition .......................................................................................................................1 71
13.4.1 Hc HCCA Register ...................................... ................................................. ...............................171
13.4.2 Hc Period Current ED Register ...................................................................................................171
13.4.3 Hc Control Head ED Register ............................ ......................................................................... 1 72
13.4.4 Hc Control Cur r e nt ED Regist e r .................. ................................................................................172
13.4.5 Hc Bulk Head ED Register ................................................................................ .......................... 1 73
13.4.6 Hc Bulk Current ED Register ....................................................................................................... 1 73
13.4.7 Hc Done Head Register ..............................................................................................................174
13.5 Frame Counter Partition .........................................................................................................................1 74
13.5.1 Hc Fm Interv al Register ....... ........................................................................................................1 74
13.5.2 Hc Fm Remaining Register .......... ...............................................................................................175
13.5.3 Hc Fm Number Register ..............................................................................................................1 76
13.5.4 Hc Periodic Start Register ...........................................................................................................176
6 Agere Systems Inc.
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
Table of Contents
(continued)
Contents Page
13.5.5 Hc LS Threshol d Regi ste r ...........................................................................................................176
13.6 Root Hub Partition ..................................................................................................................................177
13.6.1 Hc Rh Descriptor A Register .......................................................................................................177
13.6.2 Hc Rh Descriptor B Register .......................................................................................................180
13.6.3 Hc Rh Status Regis te r ............................................................................................... ..................181
13.6.4 Hc Rh Port Stat us [1: NDP] Regi ster .......... ..................................................................................182
14 IrDA_ACC and UART_ACC ...........................................................................................................................187
14.1 ACC Operation .......................................................................................................................................187
14.1.1 Transmit and Receive Operation ................................................................................................. 1 88
14.1.2 Transfer Operating Modes ........................ ............ ............ .............. ....... ....... ............ ..................188
14.1.3 Programming the Baud Rate .......................................................................................................188
14.1.4 Extended Characters ...................................................................................................................1 89
14.2 ACC Registers .......................................................................................................................................189
14.2.1 Baud Rate Register .............................................................................. ......... ............ .................. 1 90
14.2.2 Baud Rate Counter Register .................................................................. ....... .......... .. ....... ...........190
14.2.3 FIFO Statu s Re gister ............ .......................................................................................................191
14.2.4 Receiver Control Register ........................................................................................................... 1 92
14.2.5 ACC Parity Bit Encoding .............................................................................................................192
14.2.6 Transm itter Control Register .......................................................................................................192
14.2.7 Mode Control Register ................................................................................................................1 93
14.2.8 Tx/Rx FI FO Register ...................................................................................................................194
14.2.9 IrDA Feature Register .................................................................................................................194
14.3 IrDA Formatter .......................................................................................................................................197
14.3.1 IrDA Formatter Operation ............................................................................................................ 1 97
14.4 DMA Support for ACC I/O Data .............................................................................................................199
14.5 Operation on Reset ................................................................................................................................ 1 99
15 Synchronous Serial Interface (SSI) ............................ ....... ..... .. ..... .. ..... ....... ..... .. ..... .. ..... ....... ... ......................200
15.1 Description .............................................................................................................................................200
15.1.1 Clocks ..........................................................................................................................................200
15.1.2 Date Tran sfe r ..............................................................................................................................201
15.1.3 Pin Configuration ........... ............................ .................................................................................. 2 01
15.1.4 SSN Input ....................................................................................................................................201
15.1.5 Confi g urations .............................................................................................................................201
15.1.6 Slave Chip Select ........................................................................................................................202
15.2 SSI Registers .........................................................................................................................................203
15.2.1 SSI Data Regi ster .......... ..............................................................................................................203
15.2.2 SSI Control Register 1 ................................................................................................................. 2 04
15.2.3 SSI Control Register 2 Bit Descriptions .......................................................................................205
15.2.3.1 SSN ...............................................................................................................................2 05
15.2.3.2 FASTCLEAR .................................................................................................................2 05
15.2.3.3 MDOD ...........................................................................................................................205
15.2.3.4 SCOD ............................................................................................................................206
15.3 SSI Operation ......................................................................................................................................... 2 07
15.3.1 SPHA = 0 Format .......... .............................................................................................................. 2 08
15.3.1.1 Master Operation ...........................................................................................................209
15.3.1.2 Slave Operation .............................................................................................................209
15.3.2 SPHA = 1 Format .......... .............................................................................................................. 2 09
15.3.2.1 Master ...........................................................................................................................210
15.3.2.2 Slave .............................................................................................................................211
15.3.3 Transfer Start ....... ....................................................................................................................... 2 11
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T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
Table of Contents
(continued)
Contents Page
15.3.4 Transfer End ...............................................................................................................................211
15.3.4.1 Master Operation ...........................................................................................................211
15.3.4.2 Slave Operation .............................................................................................................211
15.3.5 Int errupt Generation ....................................................................................................................2 12
15.3.6 Stat u s Fl ags a n d Error Conditions ..............................................................................................212
15.3.6.1 SDONE ..........................................................................................................................212
15.3.6.2 WCOLL Flag ..................................................................................................................212
15.3.6.3 MODF ............................................................................................................................212
15.3.6.4 RD_ORUN .....................................................................................................................213
15.3.7 SSI Tra n sfe r Ab or t .......... .............................................................................................................213
15.3.8 SSNEN Contro l Register Bit ............ ............................................................................................ 2 14
16 Parallel Peripheral Inte r face (PPI) .................................................................................................................2 15
16.1 PPI Operation ........................................................................................................................................ 2 15
16.1.1 PPI Pin Configuration on Reset ...................................................................................................216
16.1.2 Procedure for Writing to an Output Pin .......................................................................................216
16.1.3 Procedure for Reading from an Input Pin ....................................................................................216
16.1.3.1 Additional Read/Write Notes .......................................................... ....... ....... .......... .......216
16.1.4 PPI Port Interrupts .......................................................................................................................217
16.2 PPI Registers .........................................................................................................................................218
16.2.1 PPI Data Direction Register ........................................ ................................................................218
16.3 PPI Port Data Register ...........................................................................................................................218
16.3.1 PPI Interrupt Enable Register ......................................................................................................219
16.3.2 PPI Port Sense Register .............................................................................................................219
16.3.3 PPI Port Polarity Register ............................................................................................................220
16.3.4 PPI Pull-Up Enable Register ....................................................................................................... 2 21
16.3.5 PPI Port Data Clea r Regi ster ..................................................................... .................................221
16.3.6 PPI Port Data Set Register .......................................................................................................... 2 21
16.4 Summary of Programming Modes ................................................................... ............ ....... ....... ............222
17 Key and Lamp Controller (KLC) .....................................................................................................................223
17.1 KLC Operation .......................................................................................................................................224
17.1.1 LED Drive Matrix Operation ............ ............................................................................................224
17.1.2 Key Scan Matr i x Oper at ion .........................................................................................................224
17.1.3 KLC Inter r u p ts ......................................................................................................... ....................226
17.1.4 Timing and Reset ........................................................................................................................2 26
17.2 KLC LED Drive and Key Scan Matrix Pins ............................................................................................226
17.3 KLC Register ..........................................................................................................................................2 27
17.3.1 Lamp Rate Registers ........................... ........................................................................................227
17.3.2 KLC Noscan Cont r ol Re gister .............................. .......................................................................228
17.3.3 Key Scan Sta tu s Regi ste r ...........................................................................................................229
17.3.4 KLC Inter r u p t Regi ster ......... ........................................................................................................2 30
17.3.5 KLC Inter r u p t En a ble Regi ste r ....................................................................................................230
18 JTAG/Boundary Scan ....................................................................................................................................231
18.1 Debug Support .. ..................................................................................................................................... 2 31
18.2 The Principle of Boundary Scan Architecture ........................................................................................231
18.2.1 Inst r u cti o n Register ........ .............................................................................................................233
18.3 Boundary Scan Register ........................................................................................................................234
19 Elect r i c a l Spe cifications .................................................................................................................................242
19.1 Absolute Maximum Ratings ................................................................................................................... 2 42
19.2 Handling Precautions .............................................................................................................................242
19.3 Crystal Specifications .............................................................................................................................242
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
Table of Contents
(continued)
Contents Page
19.3.1 Syste m Clock Crystal ................................................................................................... ............... 2 42
19.4 PHY Clock Crystal ..................................................................................................................................243
19.5 Real-Time Clock Crystal ........................................................................................................................2 43
19.6 dc Electrical Characteristics ...................................................................................................................243
19.7 Power Consumption ...............................................................................................................................2 44
20 Change History ................................................... .. ....... ..... ..... .. ....... ..... .. ..... ....... ..... .. ..... ................................245
21 Contact Us ......................................................................................................................................................245
Figures Page
Figure 1. 272-Pin PBGA Pin Diagram . . ...................................................................................................................17
Figure 2. IPT_ARM Block Diagram.........................................................................................................................27
Figure 3. Reset/Clock Management Controller Block Diagram............................................. .. ..... ..... .. ..... ...............29
Figure 4. Real- Time Clock Block Diagram .......... ....................................................................................................34
Figure 5. Inte rr u p t Controller Block Diagr a m......... ..................................................................................................48
Figure 6. DMA Controller Block Diagram 1 .............................................................................................................56
Figure 7. DMA Controller Block Diagram 2 .............................................................................................................60
Figure 8. Programmable Timer Architecture Block Diagram......... ..........................................................................70
Figure 9. Interval Timer Block Diagram...................................................................................................................71
Figure 10. Watchdog Timer Block Diagram.............................................................................................................72
Figure 11. EMI FLASH/SRAM Read Interface Timing Diag r a m......... .....................................................................81
Figure 12. EMI FLASH/SRAM Write Interface Ti mi n g Diagram..............................................................................82
Figure 13. ROM/RAM Remapping. ..........................................................................................................................83
Figure 14. SDRAM Read Timing Diagram ..............................................................................................................92
Figure 15. SDRAM Write Timing Diagram...............................................................................................................93
Figure 16. DSP Communications Controller Block Diagram...................................................................................96
Figure 17. DSP Read Interface Timing Diagram.....................................................................................................99
Figure 18. DSP Write Interface Timing Diagram...................................................................................................100
Figure 19. Ethernet 10/100 MAC Block Diagram ..................................................................................................101
Figure 20. Repeater Slice and Backplane Segment Block. ...................................................................................123
Figure 21. USB Block Diagram..............................................................................................................................162
Figure 22. ACC Block Diag r a m ................................................... ..........................................................................1 87
Figure 23. IrDA Tra n smi t Da ta Ti mi ng Diag ra m a nd Width Pr o g ra mmab i lity........................................................198
Figure 24. IrDA Receive Data Timing Diagram, Minimum Pulse Width ................................................................199
Figure 25. SSI Functional Block Diagram..............................................................................................................2 02
Figure 26. SSI Transfer Timing Diagram, (SPHA = 0)...........................................................................................2 08
Figure 27. SSI Transfer Timing Diagram, (SPHA = 1)...........................................................................................2 10
Figure 28. Parallel Peripheral Interface (PPI) Block Diagram ...............................................................................215
Figure 29. Minimum Data Input Pulse Width.........................................................................................................2 17
Figure 30. KLC Inter face Matrix............................................................................................................................. 2 23
Figure 31. Boundary Scan Architecture.................................................................................................................232
Figure 32. JTAG Interface Timing Diagram...........................................................................................................233
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T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
Table of Contents
Tables Page
Table 1. PBGA-272 Package .......................................................... ............ .............. .............................................18
Table 2. ARM Processor Memory and I/O Map ......................................................................................................28
Table 3. Reset/Clock Management Controller Signals ........................................................................................... 30
Table 4. Reset/Clock Controller Register Map .......................................................................................................35
Table 5. Pause Regi ster .........................................................................................................................................36
Table 6. Version ID Register 0xE000 0010 ............................................................................................................36
Table 7. Clock Managemen t Re g ister........... ..........................................................................................................37
Table 8. Clock Status Regi ster........................ ........................................................................................................37
Table 9. System Clock Source Encoding ...............................................................................................................38
Table 10. Clock Control Register ............................................................................................................................38
Table 11. Soft Reset Register ................................................................................................................................39
Table 12. PLL Control Register ..............................................................................................................................39
Table 13. Reset Status (Control/Clear) Registers ..................................................................................................40
Table 14. Reset Peripheral Control (Read, Clear, Set) Registers ..........................................................................41
Table 15. RTC Extern al Divi d e r Regi ste r ............ ................................................................................................... 42
Table 16. RTC Clock Pres ca le Regi sters ................... ..................................................................... ....................... 42
Table 17. RTC Control Register .............................................................................................................................43
Table 18. RTC Seconds Alarm Register ................................................................................................................44
Table 19. RTC Seconds Count Register .............................................. ..... .. ....... ..... .. .......... .. ..... .. ..........................44
Table 20. RTC Divider Re gister .......... ............................................................................... .....................................45
Table 21. RTC Inter r u pt Sta tu s Regi ster ................................................................................................................45
Table 22. RTC Interrupt Enable Register ...............................................................................................................45
Table 23. Interrupt Registers ..................................................................................................................................48
Table 24. Interrupt Request Signals (IRQ) ........................................... ..... ....... .. ....... ..... ..... ....... .. ..........................49
Table 25. Progra mm a ble In te r ru p t Co nt r o l le r Regi ster Map ...................................................................................50
Table 26. Interrupt Request Status Register IRSR .................................................................................................51
Table 27. Interrupt Request Enable Registers IRER (Set = IRESR, Clear = IRECR) ............................................51
Table 28. Interrupt Request Soft Register IRQSR ..................................................................................................52
Table 29. Interrupt Priority Control Registers IPCR[15:1] ....................................................................................... 52
Table 30. Inte r ru p t In - Se rvice Registers ISR (ISRI, ISRF) .....................................................................................53
Table 31. Inte r ru p t Source Encoding for Interru p t In -Se r vice Registers ........... ......................................................53
Table 32. Interrupt Request Source Clear Register IRQESCR .. ............................................................................ 54
Table 33. Interrupt Priority Enable Registers IPER (Set = IPESR, Clear = IPECR) ............................ ..... ..... .. .......54
Table 34. External Interrupt Control Registers ....................................................................................................... 55
Table 35. DMA Controller Register Map ................................................................................................................. 61
Table 36. DMA Control Registers for Channels [0:3] .............................................................................................62
Table 37. DMA Source Address Registers for Channels [0:3] ...............................................................................64
Table 38. DMA Preload Destination Start Address Registers for DMA Channels [0:3] .... ......................................64
Table 39. DMA Destination Address Registers for DMA Channels [0:3] ................................................................64
Table 40. DMA Preload Transfer Count Registers for Channels [0:3] ....................................................................65
Table 41. DMA Transfer Count Registers for Channels [0:3] ................................................................................. 65
Table 42. DMA Burst and Hold Count Registers for Channel [0:3] ........................................................................66
Table 43. DMA Status Register ..............................................................................................................................66
Table 44. DMA Interrupt Register ...........................................................................................................................68
Table 45. DMA Interrupt Enable Register ...............................................................................................................69
Table 46. Timer Controller Register Map ...............................................................................................................73
Table 47. Count Rate Register ...............................................................................................................................74
Table 48. Encoding of Interval Timer and Watchdog Timer Count Rates ..............................................................74
Table 49. WT Count Regis te r .................................................................................................................................75
Table 50. Timer Status Register .............................................................................................................................75
10 Agere Systems Inc.
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
Table of Contents
(continued)
Tables Page
Table 51. Timer Interrupt Mask Register ................................................................................................................76
Table 52. Timer Control Register ...........................................................................................................................76
Table 53. IT Count Registers ..................................................................................................................................77
Table 54. IPT_ARM Processor Memory Map .........................................................................................................78
Table 55. EMI FLASH/ SRAM Read Acce ss Timing Parameters ............................................................................81
Table 56. EMI FLASH/SRAM Write Access Timing Parameters ............................................................................82
Table 57. EMI FLASH Register Map ......................................................................................................................84
Table 58. Chip Sel e ct Configuration Registe r FLASH_CS ........... ..........................................................................84
Table 59. Chip Sele ct Configuration Registe r s CS1 , CS2 , CS3 ............................................. ................................85
Table 60. Hold States Encoding ............................................................................... ..............................................87
Table 61. Wait-States Encoding .............................................................................................................................87
Table 62. Chip Sele ct Ba se Address Regi sters FLASH_CS, CS1, CS2, CS3, Intern a l SRAM ........ ..................... .87
Table 63. Block Size Field Encoding ......................................................................................................................88
Table 64. Status Register .......................................................................................................................................88
Table 65. Options Register .....................................................................................................................................89
Table 66. Exter n a l SDRAM Memory Map ....... .......................................................................................................89
Table 67. SDRAM Memory Range Base Address Register ...................................................................................90
Table 68. SDRAM Control Register ........................................................................................................................90
Table 69. SDRAM Timing and Configuration Regi ste r ...........................................................................................90
Table 70. SDRAM Manual Access Register ...........................................................................................................91
Table 71. SDRAM Access Cycles, Using a 64 Mbit SDRAM ................................................................................. 95
Table 72. ARM Processor Memory and I/O Map ....... ................... ..........................................................................96
Table 73. Token Register .......................................................................................................................................97
Table 74. DSP2ARM Interrupt Register ................................................................................................................98
Table 75. ARM 2DSP Interrupt Register ................................................................................................. ............... 98
Table 76. DCC Controller I/O Signals .....................................................................................................................99
Table 77. MAC Register Map ...............................................................................................................................105
Table 78. MAC Controller Setup Register ............................................................................................................106
Table 79. MAC Packet Delay Alarm Value Register ............................................................................................108
Table 80. MAC Controller Interrupt Enable Register ............................................................................................1 08
Table 81. MAC Control Frame Destination Address Registers ............................................................................ 1 09
Table 82. MAC Control Frame Source Address Registers ................................................................................... 1 09
Table 83. MAC Control Frame Length/Type Register ..........................................................................................110
Table 84. MAC Control Frame Opcode Register ..................................................................................................110
Table 85. MAC Control Frame Data Register .......................................................................................................1 11
Table 86. VLAN Type1 Type/Length Field Register .............................................................................................111
Table 87. VLAN Type2 Type/Length Field Register .............................................................................................111
Table 88. MAC Transmit FIFO Register ...............................................................................................................1 11
Table 89. MAC Receive FIFO Register ................................................................................................................1 12
Table 90. MAC Receive Control FIFO Register ...................................................................................................112
Table 91. MDIO Addr e ss Regi ste r ........................................................................................................................114
Table 92. MDIO Data Regi ste r .............................................................................................................................114
Table 93. MAC PHY Powerdown Register ...........................................................................................................115
Table 94. MAC Controller Transmit Control Register ...........................................................................................115
Table 95. MAC Controller Transmit Start Register ...............................................................................................116
Table 96. MAC Transmit Status Register ............................................................................................................. 1 16
Table 97. MAC Collision Counter .........................................................................................................................1 18
Table 98. MAC Packet Delay Counter ..................................................................................................................118
Table 99. MAC Transmi tte d Pa cke t Counter ........... .............................................................................................1 18
Table 100. MAC Transmitted Single Collision Counter .......................................................... ............ ..................118
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T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
Table of Contents
(continued)
Tables Page
Table 101. MAC Transmitted Multiple Collision Counter ..................................................................... .................119
Table 102. MAC Excess Collision Counter ................................................ .. ....... ..... .. .......... .. ....... ........................119
Table 103. MAC Packet Deferred Counter ............................. .. ..... ....... ..... .. ..... ....... .. ..... ....... ..... .. ........................1 19
Table 104. MAC Controller Receive Control Regist e r ........................................ ..................................................119
Table 105. MAC FIFO Status Regi ster ......... ........................................................................................................ 1 20
Table 106. MAC Controller Interrupt Sta tu s Register ...... .....................................................................................1 20
Table 107. MII MAC I/O Signals ...........................................................................................................................121
Table 108. DMA Interface Signals ............................. .. .......... ....... .. .......... ....... .. ....... ..... ....... ..... ..........................122
Table 109. Repeater Slice ARM Interface ............................................................................................................129
Table 110. Repeater Slice Interface ..................................................................................................................... 1 29
Table 111. Repeater Slice Input Clocks ...............................................................................................................131
Table 112. Backpl a n e Seg men t 10/100 Mbits/s Serial Mac Int erface Port B ..... ..................................................132
Table 113. Repeater Slice Register Map ..............................................................................................................133
Table 114. Global Maximum Frame Size Register ..............................................................................................134
Table 115. Global Configuration Register ............................... ....... .......... ....... .. ....... .......... ....... ..........................135
Table 116. Port Control Registers for Por t 0, 1 ............................................................................... .....................136
Table 117. Port Configuration Register 0 for Port 0, 1 .........................................................................................136
Table 118. Port Configuration Regist e r 1, for Po r t 0, 1 ........ ................................................................................ 1 38
Table 119. Global Interrupt Enable Register ........................................................................................................1 39
Table 120. Global Interrupt Status Register ........................................................................................................140
Table 121. Global Port Status Register, for Port 0, 1 ...........................................................................................141
Table 122. MII/5 -Bit Serial Inter fa ce Signals ........................................................................................................1 43
Table 123. 10/100 Mbits/s Twisted Pair (TP) Interface Signals ............................................................................145
Table 124. Status Signals .....................................................................................................................................1 46
Table 125. Clock and Reset Signals ............................................... ............ ..... ....... ....... ....... ....... ........................ 1 46
Table 126. MII Management Frame Format .........................................................................................................147
Table 127. Summary of Management Registers (MR) ........................................................ .. ....... ....... ..... ............148
Table 128. MR0 Contr ol Regi ster Bit Description .................................................................................................149
Table 129. MR1 Status Re gi ster Bit Description ..................................................................................................150
Table 130. MR2 MR3 PHY Identifier Registers (1 and 2) Bit Description ............................. ....... ..... ....... ....... .....150
Table 131. MR4 Auton egotiation Adverti se men t Regi ster Bit Description ............ ...............................................1 51
Table 132. MR5 Autonegotiati o n L ink Par t n er Ability (Bas e Page) Reg is te r B it Desc r ip t ion ......... .. .... . .. ............ .151
Table 133. MR5 Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Description ........................152
Table 134. MR6 Auton ego tiation Expansion Regi ste r Bit Description ..... .............................................................152
Table 135. MR7 Next Page Transmit Register Bit Description .............................................................................1 53
Table 136. MR16 PCS Control Register Bit Description ......................................................................................153
Table 137. MR17 Autonegotiation (Read Register A) ..........................................................................................1 54
Table 138. MR18 Autonegotiation (Read Register B) ..........................................................................................1 54
Table 139. MR21 RXER Counte r ....... ..................................................................................................................155
Table 140. MR28 Device-Specific Register 1 (Status Register) Bit Description ...................................................155
Table 141. MR29 Device-Specific Register 2 (100 Mbits/s Control) Bit Description ............................................1 56
Table 142. MR30 Device-Specific Register 3 (10 Mbits/s Control) Bit Description ..............................................1 57
Table 143. MR31 Device-Specific Register 4 (Quick Status) Bit Description .......................................................1 58
Table 144. USB Operational Register Map ................................................................................ ....... ...................1 63
Table 145. Hc Revisio n Register ...... ....................................................................................................................163
Table 146. Hc Control Regi ster ............................................................................................................................1 64
Table 147. Hc Command Stat u s Regi ste r ............................................................................................................ 1 66
Table 148. Hc Interr u p t Sta tus Register ..............................................................................................................1 67
Table 149. Hc Interrupt Enable Register ............................................................ ....... .......... ....... ..........................169
Table 150. Hc Interr u p t Disable Register .................................................................................... . .......................170
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
Table of Contents
(continued)
Tables Page
Table 151. Hc HCCA Register ............. .............................. .................................................. ................................ 1 71
Table 152. Hc Period Current ED Register .........................................................................................................171
Table 153. Hc Control Head ED Regis te r ................................................................... .................... ..................... 1 72
Table 154. Hc Control Current ED Register ........................................................... ..............................................172
Table 155. Hc Bulk Head ED Register .................................................................................................................173
Table 156. Hc Bulk Current ED Register ............................................................................................................. 1 73
Table 157. Hc Done Head Register ..................................................................................................................... 1 74
Table 158. Hc Fm Interval Register ............................ .........................................................................................175
Table 159. Hc Fm Remaining Register ................................................... ....................................... .....................175
Table 160. Hc Fm Number Regis ter ....................................................................................................................176
Table 161. Hc Periodic Start Register ................................................ .................................................................176
Table 162. Hc LS Threshol d Register ......................................... ................................................. ....................... 1 77
Table 163. Hc Rh Descriptor A Register ............................................................................................................. 1 78
Table 164. Hc Rh Descriptor B Register ............................................................................................................. 1 80
Table 165. Hc Rh Status Regis te r .......................................................................................................................181
Table 166. Hc Rh Port Stat us Register [1:NDP] ......... .........................................................................................182
Table 167. ACC Transfer Modes ........................................ ..... ....... ..... .. ....... ..... ....... ..... ....... .. ..... .........................1 88
Table 168. Extended Characters ......................................................... ......... .......... ....... ......... ..............................189
Table 169. IrDA_ACC and UART_ACC Communi ca ti o n Contro l ler Register Map ............................... ...............189
Table 170. Baud Rate Register .............................................................................................. ..............................1 90
Table 171. Baud Rate Counter Register .................................................................. ....... ....... ..............................190
Table 172. FIFO Sta tu s Re gister ............ ..............................................................................................................191
Table 173. Receiver Control Register ............................................ ......................................................................192
Table 174. ACC Parity Bit Encoding .....................................................................................................................192
Table 175. Transm itter Control Registe r ..............................................................................................................193
Table 176. Mode Control Register .................................................. ....... ....... ..... ....... ....... ....... .............................. 1 93
Table 177. Tx/Rx FI FO Regi ste r ........................................................................................................................... 1 94
Table 178. IrDA Feat u re Regist e r .........................................................................................................................194
Table 179. ACC Interr u p t Re gister .......................................... .............................................................................195
Table 180. ACC Interr u p t En a ble Register ...... .....................................................................................................196
Table 181. SSI Register Map ............ ....................................................................................... ............................203
Table 182. SSI Data Regi ster ........... ...................................................................................................................203
Table 183. SSI Contro l Register 1 ........ ..................................................................................... ...........................2 04
Table 184. SSI Clock Divide Bit Encoding ............................................................................................................205
Table 185. SSI Contro l Register 2 ........ ..................................................................................... ...........................2 06
Table 186. SSI Int e r r u p t Regi ste r ........................................................................................................................2 06
Table 187. SSI Int e r r u p t En abl e Regi ste r ............................................................................................................207
Table 188. PPI Parallel I/O Controlle r Regi ster Map ........ ....................................................................................218
Table 189. PPI Data Direction Register ....... .........................................................................................................218
Table 190. PPI Port Data Register ....................................................................................... ................................219
Table 191. PPI Int e r r u p t En abl e Regi ste r ...................................................................................... .......................219
Table 192. PPI Port Sense Register ....................................................................................................................220
Table 193. PPI Port Polarity Register ......................................................................................... ..........................220
Table 194. PPI Pull-Up Enable Register ........................................ ..... ....... ....... ....... ..... ....... .. ..............................221
Table 195. PPI Port Data Clear Register ..............................................................................................................2 21
Table 196. PPI Port Data Set Register .................................................................................................................222
Table 197. PPI Programming Modes ...................................................................................................................222
Table 198. KLC Matrix Pins ..................................................................................................................................2 26
Table 199. KLC Registe r Map ..............................................................................................................................2 27
Table 200. Lamp Rate Registers ..................... .....................................................................................................2 28
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T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
Table of Contents
(continued)
Tables Page
Table 201. Lamp Rate Bi t En co din g ............................................................................................. ........................228
Table 202. Noscan Control Register .......... .............................................................................. ............................229
Table 203. Noscan Delay Interval Encoding ........................................................................................................229
Table 204. Key Scan Sta tu s Regi ste r.. ..................................................................................................................230
Table 205. KLC Inte rr u p t Regi ster ......... ...............................................................................................................230
Table 206. KLC Inte rr u p t En a ble Register ......... ............................................................................. ......................230
Table 207. Boundary Scan Pin Functions ............................................................... .............. ....... ........................231
Table 208. Inst r u ction Register .......................... ................................................................................................... 2 33
Table 209. Boundary Scan Register Description ........................................................................ ....... .. .................234
Table 210. Absolute Maximum Ratings .......... ...................................................................................................... 2 42
Table 211. Syste m Clock (XTAL0, XTAL1) Specifi ca tions ...................................................................................242
Table 212. PHY Clock (XLO, XHI) Cr ystal Specificati o n s ....................................................................................243
Table 213. Real-T i me Clock (XRTC0, XRTC1) Specificatio n s ....................................... ......................................2 43
Table 214. Reset Pu lse ...... .................................................................................................................................. 2 43
Table 215. dc Electrical Characteristics ......................................................... ............................. .........................243
Table 216. Power Consu mption ...........................................................................................................................244
Table 217. Change History of DS01-213IPT.........................................................................................................2 45
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
1 Introduction
(continued)
1.1 PT_ARM Features
The IPT_ARM is a high-performance communications processor; it supports 100 Mbits/s Ethernet, USB, and IrDA,
and provides all general system processing functions. The features of the IPT_ARM are as follows:
ARM 940T with ARM 9TDMI 32-bit core processor.
■
Processor clock speeds up to 57.6 MHz.
■
Instruction cache, 1K x 32.
■
Data cache, 1K x 32.
■
Internal SRAM, 1K x 32.
■
Two 10/100Base-T Ethernet PHYs.
■
Ethernet 10/100 repeater capabilities for in-line Ethernet connection from network to PC.
■
USB host bus interface including isochronous support.
■
IrDA infrared communications interface.
■
Asynchronous communications interface.
■
Serial communications controller and interface.
■
Para llel I/O up to 16 bits.
■
LED control interface.
■
Ke yb oard scan circui try.
■
DMA control for up to four channels.
■
Four general-purpose timer counters for flexible timing control.
■
Real-time clock.
■
SDRAM external memory interface.
■
FLASH external memory interface.
■
Interprocessor communication memories for data transfer to the IPT_DSP.
■
Interprocessor token and interrupt registers for control and communication between the IPT_ARM and the
■
IPT_DSP.
JTAG control for test and debugging.
■
Implementation in 0.25 µm, 3 V silicon technology.
■
Packaged in a 272-pin PBGA.
■
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Page 18
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
1 Introduction
(continued)
1.2 IPT_ DS P F ea tu r es
The IPT_ARM is intended to be used with its companion IC, the audio digital signal-processor integrated circuit
(IPT_DSP). The combination of the IPT_ARM and the IPT_DSP provides a powerful solution for the implementation of the IP exchange business phone. The features of the IPT_DSP are as follows:
DSP1627 core with bit manipulation unit.
■
DSP clock speeds up to 80 MHz.
■
Instruction ROM, 32K x 16 (zero wait-state at 80 MHz).
■
Dual-port RAM, 6K x 16 (zero wait-state at 80 MHz).
■
Internal SRAM, 16K x 16 (single wait-state at 80 MHz).
■
16-bit analog-to-digital converter.
■
Programmable gain amplifier on audio input.
■
Fixed gain differential microphone input.
■
Analog input SRAM buffer , 512 x 16.
■
Timed DMA for analog input SRAM.
■
Two 16-bit digital-to-analog converters.
■
Independent simultaneous speaker and handset outputs.
■
Two integrated differential speaker driver outputs.
■
Two analog output SRAM buffers, 512 x 16 each.
■
Two timed DMA outputs for simultaneous handset and speaker audio output.
■
Low-pass filtering on audio inputs and outputs.
■
Serial I/O interface.
■
General-purpose timer counter.
■
Bit I/O inter face.
■
JTAG test and debugging control.
■
Implementation in 0.35 µm, 5 V silicon technology.
■
Packaged in 100-pin TQFP.
■
16 Agere Systems Inc.
Page 19
Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
2 Pinout Information
2.1 272-Pin PBGA Pin Diagram
27.00 ± 0.20
+0.70
IDENTIFIER ZO NE
A1 BALL
24.00
–0.00
MOLD
COMPOUND
PWB
CENTER ARRAY
FOR THERMAL
ENHANCEMENT
A1 BALL
CORNER
0.36 ± 0.0 4
0.60 ± 0.10
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1.17 ± 0.05
SOLDER BALL
19 SPACES @ 1.27 = 24.13
123456789101112131415161718 20
19
+0.70
24.00
–0.00
0.75 ± 0.15
19 SPACES
@ 1.27 = 24 .13
TOP VIEW
27.00
± 0.20
2.13 ± 0.19
SEATING PLANE
BOTTOM VIEW
0.20
Figure 1. 272-Pin PBGA Pin D i agram
5-4406 (F).b
Agere Systems Inc. 17
Page 20
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
2 Pinout Infor m ation
(continued)
2.2 Pin Li s t
Table 1. PBGA-272 Package
Ball Signal Description I/O Pull-Up/Down Source/Sink
Current
ARM to DSP Communications Interface
H1 DSP_A[0] DSP interface address bus bit 0 (LSB) I — 7 ma/7 ma
J4 DSP_A[1] DSP interface address bus bit 1 I — 7 ma/7 ma
J3 DSP_A[2] DSP interface address bus bit 2 I — 7 ma/7 ma
J2 DSP_A[3] DSP interface address bus bit 3 I — 7 ma/7 ma
J1 DSP_A[4] DSP interface address bus bit 4 I — 7 ma/7 ma
K2 DSP_A[5] DSP interface address bus bit 5 I — 7 ma/7 ma
K3 DSP_A[6] DSP interface address bus bit 6 I — 7 ma/7 ma
K1 DSP_A[7] DSP interface address bus bit 7 I — 7 ma/7 ma
L1 DSP_A[8] DSP interface address bus bit 8 I — 7 ma/7 ma
L2 DSP_A[9] DSP interface address bus bit 9 I — 7 ma/7 ma
L3 DSP_A[10] DSP interface address bus bit 10 (MSB) I — 7 ma/7 ma
B1 DSP_D[0] DSP interface data bus bit 0 (LSB) I/O 50 kΩ pull-up 7 ma/7 ma
C2 DSP_D[1] DSP interface data bus bit 1 I/O 50 kΩ pull-up 7 ma/7 ma
D2 DSP_D[2] DSP interface data bus bit 2 I/O 50 kΩ pull-up 7 ma/7 ma
D3 DSP_D[3] DSP interface data bus bit 3 I /O 5 0 kΩ pull-up 7 ma/7 ma
E4 DSP_D[4] DSP interface data bus bit 4 I/O 50 kΩ pull-up 7 ma/7 ma
C1 DSP_D[5] DSP interface data bus bit 5 I /O 5 0 kΩ pull-up 7 ma/7 ma
D1 DSP_D[6] DSP interface data bus bit 6 I /O 5 0 kΩ pull-up 7 ma/7 ma
E3 DSP_D[7] DSP interface data bus bit 7 I/O 50 kΩ pull-up 7 ma/7 ma
E2 DSP_D[8] DSP interface data bus bit 8 I/O 50 kΩ pull-up 7 ma/7 ma
E1 DSP_D[9] DSP interface data bus bit 9 I/O 50 kΩ pull-up 7 ma/7 ma
F3 DS P _D[10] DSP interface data bus bit 10 I/O 50 kΩ pull-up 7 ma/7 ma
G4 DSP_D[11] DSP interface data bus bit 11 I/O 50 kΩ pull-up 7 ma/7 ma
F2 DS P _D[12] DSP interface data bus bit 12 I/O 50 kΩ pull-up 7 ma/7 ma
F1 DS P _D[13] DSP interface data bus bit 13 I/O 50 kΩ pull-up 7 ma/7 ma
G3 DSP_D[14] DSP interface data bus bit 14 I/O 50 kΩ pull-up 7 ma/7 ma
G2 DSP_D[15] DSP interface data bus bit 15 (MSB) I/O 50 kΩ pull-up 7 ma/7 ma
G1 DSP_RWN Read high wr ite low memor y signal I — 7 ma/7 ma
H3 DSP_MCSN Chip select interprocessor memory I — 7 ma/7 ma
H2 DSP_ICSN Chip select interprocessor semaphores and interrupt I /O — 7 ma/7 ma
L4 DSP_INTN0 DSP interrupt I/O — 7 ma/7 ma
Crystal for Main Clock and Real-Time Clock
P4 XRTC0 Inpu t pin to connect 32.768 kHz crystal I — —
T1 XRTC1 Output pin to connect 32.768 kHz crystal O — —
T4 XTAL0 Output pin to connect 11.52 MHz crystal O — —
V1 XTAL1 Input pin to connect 11.52 MHz crystal I — —
M1 TSTCLK Test mode clock input O — 4 ma/4 ma
N2 RTS0N Reset output O — 4 ma/4 ma
18 Agere Systems Inc.
Page 21
Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
2 Pinout Infor m ation
Table 1. PBGA-272 Package (continued)
Ball Signal Description I/O Pull-Up/Down Source/Sink
B11 FLASH_CS FLASH chip select O — 7 ma/7 ma
A10 CS1 Chip select 1 for SRAM O — 7 ma/7 ma
B10 CS2 Chip select 2 for SRAM O — 7 ma/7 ma
C10 CS3 Chip selec t 3 for SRAM O — 7 ma /7 ma
D9 SDRASN Row address strobe, active-low O — 7 ma/7 ma
A8 SDC ASN Column address strobe, active-low O — 7 ma/7 ma
A9 EXWAIT External WAIT pin I — 7 ma/7 ma
B9 EXINT1 External interrupt input #1 I* ——
C9 EXINT2 External interrupt input #2 I* ——
B8 SDWEN Write enable O — 7 ma/7 ma
C8 SDRCK SDRAM clock O — 7 ma/7 ma
A7 SDLDQM S DLDQM is lower data byte enable O — 7 ma/7 ma
B7 SDUDQM SDUDQM is upper byte enable O — 7 ma/7 ma
C11 RDN Read strobe O — 7 ma/7 ma
A11 WRN Write strobe O — 7 ma/7 ma
D10 BE1N Byte enable O — 7 ma/7 ma
A6 D [15] EMI data bus bit 15 (MSB) I/O 50 kΩ pull-up 7 ma/7 ma
C7 D [14] EMI data bus bit 14 I/O 50 kΩ pull-up 7 ma/7 ma
B6 D [13] EMI data bus bit 13 I/O 50 kΩ pull-up 7 ma/7 ma
A5 D [12] EMI data bus bit 12 I/O 50 kΩ pull-up 7 ma/7 ma
D7 D [11] EMI data bus bit 11 I/O 50 kΩ pull-up 7 ma/7 ma
C6 D [10] EMI data bus bit 10 I/O 50 kΩ pull-up 7 ma/7 ma
B5 D [9] EMI data bus bit 9 I/O 50 kΩ pull-up 7 ma/7 ma
A4 D [8] EMI data bus bit 8 I/O 50 kΩ pull-up 7 ma/7 ma
C5 D [7] EMI data bu s bit 7 I/O 50 kΩ pull-up 7 ma/7 ma
B4 D [6] EMI data bus bit 6 I/O 50 kΩ pull-up 7 ma/7 ma
A3 D [5] EMI data bus bit 5 I/O 50 kΩ pull-up 7 ma/7 ma
D5 D [4] EMI data bu s bit 4 I/O 50 kΩ pull-up 7 ma/7 ma
C4 D [3] EMI data bu s bit 3 I/O 50 kΩ pull-up 7 ma/7 ma
B3 D [2] EMI data bus bit 2 I/O 50 kΩ pull-up 7 ma/7 ma
B2 D [1] EMI data bus bit 1 I/O 50 kΩ pull-up 7 ma/7 ma
A2 D [0] EMI data bus bit 0 (LSB) I/O 50 kΩ pull-up 7 ma/7 ma
A19 A[23] EMI address bus bit 23 (MSB) O — 7 ma/7 ma
B18 A[22] EMI address bus bit 22 O — 7 ma/7 ma
B17 A[21] EMI address bus bit 21 O — 7 ma/7 ma
C17 A[20] EMI address bus bit 20 O — 7 ma/7 ma
D16 A[19] EMI address bus bit 19 O — 7 ma/7 ma
A18 A[18] EMI address bus bit 18 O — 7 ma/7 ma
*Schmitt trigge r input.
(continued)
Current
External Memory Interface for FLASH and Gen eral Chip Select
External Memory Interface SDRAM Control Signals
Common External Memory Interface
Agere Systems Inc. 19
Page 22
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
2 Pinout Infor m ation
Table 1. PBGA-272 Package (continued)
Ball Signal Description I/O Pull-Up/Down Source/Sink
A17 A[17] EMI address bus bit 17 O — 7 ma/7 ma
C16 A[16] EMI address bus bit 16 O — 7 ma/7 ma
B16 A[15] EMI address bus bit 15 O — 7 ma/7 ma
A16 A[14] EMI address bus bit 14 O — 7 ma/7 ma
C15 A[13] EMI address bus bit 13 O — 7 ma/7 ma
D14 A[12] EMI address bus bit 12 O — 7 ma/7 ma
B15 A[11] EMI address bus bit 11 O — 7 ma/7 ma
A15 A[10] EMI address bus bit 10 O — 7 ma/7 ma
C14 A[9] EMI address bus bit 9 O — 7 ma/7 ma
B14 A[8] EMI address bus bit 8 O — 7 ma /7 ma
A14 A[7] EMI address bus bit 7 O — 7 ma /7 ma
C13 A[6] EMI address bus bit 6 O — 7 ma/7 ma
B13 A[5] EMI address bus bit 5 O — 7 ma /7 ma
A13 A[4] EMI address bus bit 4 O — 7 ma /7 ma
D12 A[3] EMI address bus bit 3 O — 7 ma/7 ma
C12 A[2] EMI address bus bit 2 O — 7 ma/7 ma
B12 A[1] EMI address bus bit 1 O — 7 ma/7 ma
A12 A[ 0] EMI address bus bit 0 (LSB) O — 7 ma/7 ma
E18 PRTPWR Bidirectional port power I/O* —4 ma/4 ma
D19 PWRFLTN Input port power fault I 5 0 kΩ pull-up —
E17 DPLS Bidirectional differential USB port signal I/O — —
D18 DMNS Bidirectional differential USB port signal I/O — —
Y1 USBALTCK Universal serial bus alternate clock I* 50 k Ω pull-up 4 ma/4 ma
W1 MDOSDI Master data output, slave data input I/O* 50 kΩ pull-up 4 ma/4 ma
V3 MDISDO Master data input, slave data output I/O* —4 ma/4 ma
W2 SSN Synchronous serial select I/O* —4 ma/4 ma
V2 SCK Clock signal I/O* —4 ma/4 ma
J19 PPI[15] Parallel peripheral interface bit 15 I/O* —4 ma/4 ma
J18 PPI[14] Parallel peripheral interface bit 14 I/O* —4 ma/4 ma
J17 PPI[13] Parallel peripheral interface bit 13 I/O* —4 ma/4 ma
H20 PP I[12] Parallel peripheral interface bit 12 I/O* —4 ma/4 ma
H19 PP I[11] Parallel peripheral interface bit 11 I/O* —4 ma/4 ma
H18 PP I[10] Parallel peripheral interface bit 10 I/O* —4 ma/4 ma
G20 PPI[9] Parallel peripheral interface bit 9 I/O* —4 ma/4 ma
G19 PPI[8] Parallel peripheral interface bit 8 I/O* —4 ma/4 ma
F20 PPI[7] Parallel peripheral interface bit 7 I/O* —4 ma/4 ma
G18 PPI[6] Parallel peripheral interface bit 6 I/O* —4 ma/4 ma
*Sch m itt trigger input.
(continued)
Current
Common External Memory Interface (continued)
USB Interface
Synchronous Serial Interface
Parallel Port Interface
20 Agere Systems Inc.
Page 23
Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
2 Pinout Infor m ation
Table 1. PBGA-272 Package (continued)
Ball Signal Description I/O Pull-Up/Down Source/Sink
F19 PPI[5] Parallel peripheral interface bit 5 I/O* — 4 ma/4 ma
E20 PPI[4] Parallel peripheral interface bit 4 I/O* — 4 ma/4 ma
G17 PPI[3] Parallel peripheral interface bit 3 I/O* — 4 ma/4 ma
F18 PPI[2] Parallel peripheral interface bit 2 I/O* — 4 ma/4 ma
E19 PPI[1] Parallel peripheral interface bit 1 I/O* — 4 ma/4 ma
D20 PPI [0] Parallel peripheral interface bit 0 I/O* — 4 ma/4 ma
W3 K_ROW[6] Row 6—0. Row outputs for the LED drive matrix and
Y2 K_ROW[5 ] I/O — 8 m a /8 ma
W4 K_ROW[4 ] I/O — 8 ma/8 ma
V4 K_ROW[3 ] I/O — 8 m a /8 ma
U5 K_ROW[2] I/O — 8 ma/8 ma
Y3 K_ROW[1 ] I/O — 8 m a /8 ma
Y4 K_ROW[0 ] I/O — 8 m a /8 ma
V5 K_COL[7] Column 7—0. Column output s for LED drive matrix
W5 K_COL[6] I/O* 50 kΩ pull-down 4 ma/4 ma
Y5 K_COL[5] I/O* 50 kΩ pull-down 4 ma/4 ma
V6 K_COL[4] I/O* 50 kΩ pull-down 4 ma/4 ma
U7 K_COL[3] I/O* 50 kΩ pull-down 4 ma/4 ma
W6 K_COL[2] I/O* 50 kΩ pull-down 4 ma/4 ma
Y6 K_COL[1] I/O* 50 kΩ pull-down 4 ma/4 ma
V7 K_COL[0] I/O* 50 kΩ pull-down 4 ma/4 ma
W7 LCNTRL High active output used to enable LED drive matrix O — 8 ma/8 ma
Y7 MSGL ED Message LED direct drive output pin O — 8 ma/8 ma
V8 SPKRLED Speaker LED direct drive output pin O — 8 ma/8 ma
W8 SWHOOK Switch-hook I* — 8 ma/8 ma
M19 TPOB[ 1] Transmit data, negative differential O — —
M20 TPO[1] Transmit data, positive differential O — —
V20 TPI[1] Rec eived data, positive differential I — —
U20 TPIB[1] Received data, negative differential I — —
L19 TPOB[0] Transmit data, negative differential O — —
L20 T P O[0] Transmit data, positive differential O — —
T19 TPI[0] Received data, positive differential I — —
T20 TPIB[0] Received data, negative differential I — —
*Schmitt trigge r input.
key scan matrix
and inputs for key scan matrix
(continued)
Current
Parallel Port Interface (continued)
Key and Lamp Cont rolle r
I/O — 8 m a /8 ma
I/O* 50 kΩ pull-down 4 ma/4 ma
Ethernet Port to the PC
Ethernet Por t to the Network
Agere Systems Inc. 21
Page 24
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
2 Pinout Infor m ation
Table 1. PBGA-272 Package (continued)
Ball Signal Description I/O Pull-Up/Down Source/Sink
Y11 ECLP Analog factory test points (PHY section) O — —
W11 ECLN O — —
V11 ATBOP O — —
U11 ATBON O — —
P18 RMCLK 32 MHz bypass for PHY clock I — —
P19 XLO Crystal oscillator input, PHY clock I — —
P20 XHI Crystal oscillator output, PHY clock O — —
K17 LS10_OK [0] Link10, status PHY 1 O — 8 ma/8 ma
K19 LS100_OK [0] Link100, status PHY 1 O — 8 ma/8 ma
W19 XS [0] Transmit status PHY 1 O — 8 ma /8 ma
J20 LS10_OK [1] Link10, status PHY 2 O — 8 ma/8 ma
K18 LS100_OK [1] Link100, status PHY 2 O — 8 ma/8 ma
Y20 XS [1] Transmit status PHY 2 O — 8 ma/8 ma
P17 REXTBS Band gap reference for the receive channel O — —
M18 REXT10 Current setting 10 Mbits/s O — —
M17 REXT100 Current setting 100 Mbits/s O — —
W12 Testpt[19] Factory test points I/O* —4 ma/4 ma
V12 Testpt[18] I/O* —4 ma/4 ma
U12 Testpt[17] I/O* —4 ma/4 ma
Y13 Testpt[16] I/O* —4 ma/4 ma
W13 Testpt[15] I/O* —4 ma/4 ma
V13 Testpt[14] I/O* —4 ma/4 ma
Y14 Testpt[13] I/O* —4 ma/4 ma
W14 Testpt[12] I/O* —4 ma/4 ma
Y15 Testpt[11] I/O* —4 ma/4 ma
V14 Testpt[10] I/O* —4 ma/4 ma
W15 Testpt[9] I/O* —4 ma/4 ma
Y16 Testpt[8] I/O* —4 ma/4 ma
U14 Testpt[7] I/O* —4 ma/4 ma
V15 Testpt[6] I/O* —4 ma/4 ma
W16 Testpt[5] I/O* —4 ma/4 ma
Y17 Testpt[4] I/O* —4 ma/4 ma
V16 Testpt[3] I/O* —4 ma/4 ma
W17 Testpt[2] I/O* —4 ma/4 ma
Y18 Testpt[1] I/O* —4 ma/4 ma
U16 Testpt[0] I/O* —4 ma/4 ma
M2 CLK RE F Test mode clock output O — 4 ma /4 ma
Y9 S C_M ODE N Scan mode s elect I/O* 50 kΩ pull-up 4 ma/4 ma
W10 SC_ENAN Scan mode enable I/O* 50 kΩ pull-up 4 ma/4 ma
*Sch m itt trigger input.
(continued)
Current
Ethernet 10/100 PHY Port 1
Ethernet 10/100 PHY Port 2
Test Points
22 Agere Systems Inc.
Page 25
Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
2 Pinout Infor m ation
(continued)
Table 1. PBGA-272 Package (continued)
Ball Signal Description I/O Pull-Up/Down Source/Sink
Current
Test Interface Controller (TIC)
T2 T_ACK Test mode acknowledge O — 4 ma/4 ma
U1 T_REQB Factory test inputs I 50 kΩ pull-down —
T3 T_REQ A I 50 kΩ pull-down —
Y8 TMODE[0] Test mode input I 50 kΩ pull-up —
U9 TMO DE[1] Test mode input I 50 kΩ pull-up —
V9 TMODE[2] Test mode input I 50 kΩ pull-up —
W9 TMODE[3] Test mode input I 50 k Ω pull-up —
JTAG and Test
N3 JTDO JTAG test data output O — 4 m a/4 ma
P1 JTRSTN JTAG test reset input I* 50 kΩ pull-up —
P2 JTMS JTAG test mode select I* 50 kΩ pull-up —
R1 JT DI JTAG test data input I* 50 kΩ pull-up —
P3 JTCK JTAG test clock I* 50 kΩ pull-up —
V18 JMODE JMODE select I* 50 kΩ pull-up —
IrDA
B19 IRDATX0 IrDA ACC tran smit O — 4 ma/4 m a
A20 IRDARX0 IrDA ACC receive I* ——
B20 TX1 UART transmit O — 4 ma/4 ma
C18 RX1 UART receive I* ——
Miscellaneous
N1 RE SETN Chip reset input I* ——
V17 OMUXSEL[0] Test mode MUX I 50 kΩ pull-up —
W18 O MUXSEL[1] I 50 kΩ pull-up —
Y19 OMUXSE L [2] I 50 k Ω pull-up —
C3 VRE F Output buffer voltage reference for DCC and EMI inter-
I— —
faces
Ball Power Power and Ground
M3 V
M4 VDDPLL PLL V
PLL PLL V
SS
SS
DD
R2 VSSX2 32 kHz crystal ground
R3 V
U2 V
U3 V
Y10 V
Y12 VSSA Analog V
W20 VDDA Analog V
T18 VDDA Analog V
R18 VDDA Analog V
R19 VDDMMoat V
R20 VDDA Analog V
N18 VDDA Analog V
*Schmitt trigge r input.
X2 32 kHz crystal power
DD
X1 11.52 MHz cry stal ground
SS
X1 11.52 MHz crystal power
DD
A Analog V
DD
DD
SS
DD
DD
DD
DD
DD
DD
Agere Systems Inc. 23
Page 26
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
2 Pinout Infor m ation
(continued)
Table 1. PBGA-272 Package (continued)
Ball Power Power and Ground (continued)
U USB ground
C19 V
C20 V
D11 V
D15 V
D6 V
F17 V
F4 V
K4 V
L17 V
R17 V
R4 V
U10 V
U15 V
U6 V
A1 V
D13 V
D17 V
D4 V
D8 V
H17 V
H4 V
J10 V
J11 V
J12 V
J9 V
K10 V
K11 V
K12 V
K9 V
L10 V
L11 V
L12 V
L9 V
M10 V
M11 V
M12 V
M9 V
N17 V
N4 V
U13 V
U17 V
U4 V
U8 V
SS
UUSB power
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power (thermal)
Power
Power
Power
Power
Power
Power
24 Agere Systems Inc.
Page 27
Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
2 Pinout Infor m ation
Table 1. PBGA-272 Package (continued)
Ball No Connects
V10 NC No connect
V19 NC No connect
U18 NC No connect
U19 NC No connect
T17 NC No connect
N19 NC No connect
N20 NC No connect
L18 NC No connect
K20 NC No connect
(continued)
Agere Systems Inc. 25
Page 28
T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
3 Overview
The IPT_ARM contains several system-level functions that would typically require separate ICs. The following functions are implemented on a single IC: a full 32-bit microprocessor with integrated cache, a complete two-port Ethernet subsystem including a two-port repeater, a host USB, IrDA, UAR T, and SSI communications controllers. In
addition, there are general peripheral controllers including parallel I/O, key scanning, and LED control circuitry.
The IPT_ARM processor communicates with memory through the AMBA* ASB bus. This bus supports 32-bit word
accesses as well as half-word and byte accesses. The AMBA APB bridge provides a flexible interface for communicating with the on-chip peripheral devices. The IPT_ARM can be used in a system that meets European Class B
emissions requirements.
The IPT_ARM block diagram in Figure 2 on page 27 shows the following system blocks:
ARM 940T 32-bit CPU.
■
AMBA ASB bus for high-performance memory access.
■
AMBA APB bridge for communication with and control of IPT_ARM peripherals.
■
Four-channel DMA controller to move data from memory to memory or to/from memory from/to IPT_ARM
■
peripherals.
Interrupt controller with programmable priority for efficient system operation.
■
Reset/clock management controller with internal PLL circuitry to provide programmable clock frequencies,
■
including a one-second real time clock.
General timer unit with four interval timers and a watchdog timer.
■
External memory interface with support for SDRAM, FLASH, and SRAM memories.
■
DSP communications controller with interrupts, token registers, and buffer memories for efficient interprocessor
■
communications.
1K x 32 internal SRAM for general-purpose storage.
■
Ethernet MAC.
■
Two-port Ethernet repeater.
■
Tw o Et hernet PHYs.
■
USB host controller.
■
IrDA communications controller.
■
UART communications controller.
■
SSI communications controller.
■
16-bit parallel port interface.
■
Key and lamp controller (KLC).
■
JTAG.
■
* AMBA is a tradem a r k of ARM Limited.
26 Agere Systems Inc.
Page 29
Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
3 Overview
COMMUNICATIONS
DSP_INTN0
DSP_RWN
DSP_MCSN
DSP_ICSN
BE1N
A[23:0]
D[15:0]
WRN
RDN
SDRCK
SDWEN
EXINT1
EXINT2
RD
2-PORT RAM DSP RD
2-PORT RAM ARM RD
WR
EXTERNAL MEMORY
EXTERNAL MEMORY
JTAG TIC
DSP_A[10:0]
DSP_D[15:0 ]
FLASH_CS
CS_[3:1]
EXWAIT
SDLDQM
SDUDQM
SDCASN
SDRASN
(continued)
DSP
INTERFACE
TOKEN
AND INTERRUPT
REGISTERS
512 x 32
512 x 32
FLASH
INTERF ACE
REGISTERS
EMI-FLASH
SDRAM
INTERF ACE
REGISTERS
EMI-SDRAM
RD
WR
APB BUS
ETHERNET
10/100 Mbits/s
Tx FIFO
32 x 32
INTERRUPT
CONTROLLER
PROCESSOR CORE
INSTRUCTION
CACHE
1K x 32
AMBA ASB INTERFACE
AMBA APB BRIDGE
RESET/CLOCK
MANAGEMENT
UNIT
MAC
Rx FIFO
32 x 32
ARM940T
4-bit MII
DATA
CACHE
1K x 32
ASB BUS
DMA
CONTROLLER
APB BUS
TIMER MODULE
4 INTERVAL TIMERS
1 WATCHDOG TIMER
MII MANAGEMENT SIGNA LS
10/100 REP EATER
BACKPLA N E
SEGME N T
10/100
INTERNAL
SRAM
1K x 32
4-bit MII
REPEATER
SLICE 0
REPEATER
SLICE 1
4-bit MII
PPI
PARALLEL
PERIPHERAL
INTERF ACE
16 I/O
XLO
RMCLK
XHI
ECLP
ECLN
ETHERNET
PORT 1 PH Y
10/100
ETHERNET
125 MHz
PORT 2 PH Y
10/100
TEST
SSI
UART A IrDA
UART B
USB
HOST
CONTROLLER
KEY AND LAMP
CONTROLLER
ATBON
ATBOP
4
3
CHANNEL 1
4 WIRE
XS[1,0]
LS100_OK[1,0]
LS10_OK[1,0]
REXT100
REXT10
REXTBS
CHANNEL 2
4 WIRE
TEST PT[19:0]
CLKREF
SC_MODEN
SC_ENAN
TMODE[3:0]
MULTIPLEXED
SIGNALS
TESTPT [19:0]
OMNXS EL[ 2:0]
SCK
SSN
MDISDI
MDISDO
IRDATX0
IRDARX0
TX1
RX1
USBALTCK
DPLS
DMNS
PRTWR
PWRFLTN
K_ROW [6:0]
K_COL[7:0]
LCNTRL
MSG_LED
SPKRLED
SWHOOK
JTDI
JTCK
JTDO
JTMS
JTRSTN
JMODE
TACK
T_REQB
T_REQA
XTAL1
XRTC1
XTAL0
XRTC0
TSTCLK
RTS0N
RESETN
PPI[15:0]
5-8233(F)a
Figure 2. IPT_ARM Block Diagram
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T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
3 Overview
3.1 ARM
The ARM 940T is a full 32-bit microprocessor with integrated instruction and data cache. This processor core contains many high-performance features. The AMBA APB bridge is a flexible interf ace between the high-performance
AMBA ASB bus and the AMBA APB bus. Documentation for the ARM 940T and these buses can be found at the
website: http://www.arm.com
(continued)
T and AMBA Bridge
940
3.2 IPT_ ARM Memory and I/O Map
The buses, along with an external mem ory controller provide the logic and decoding to access and support the
memories and peripherals on and off the IPT_ARM. The IPT_ARM processor memory and I/O map is shown
below.
.
Table 2. ARM Processor Memory and I/O Map
Description Address
This range is shared between ROM (FLASH), external SDRAM, FLASH_CS, CS1,
CS2, CS3, and internal SRAM with programmable base addresses.
Reserved for ARM 940T processor. 0xC000 0000:0xCFFF FFFF
Reserved. 0xD000 0000:0xDFFF FFFF
Reset/clock controller register map (see Table 4 on page 35); includes version ID
register.
Programmable interrupt controller register map (see Table 25 on page 50). 0xE000 1000:0xE000 1FFF
DMA controller register map (see Table 35 on page 61). 0xE000 2000:0xE000 2FFF
EMI FLASH register map (see Table 57 on page 84). 0xE000 3000:0xE000 3FF F
SSI register map (see Ta ble 181 on page 203). 0xE000 4000:0xE000 4FFF
Timer controller register map (see Ta ble 46 on page 73). 0xE000 5000:0xE000 5FFF
PPI parallel I/O controller register map (see Table 188 on page 218). 0xE000 6000:0xE000 6FFF
USB operational register map (see Table 144 on page 163). 0xE000 7000:0xE000 7FFF
IrDA_ACC communications controller register map (see Table 169 on page 189). 0xE 000 8000 : 0xE000 8FFF
UART_ACC communications controller register map (see Table 169 on page 189). 0xE000 9000:0xE000 9FFF
Reserved. 0xE000 A000:0xE000 AFFF
RTC control registers (see Table 17 on page 43). 0xE000 C000:0xE000 CFFF
Key and lamp controller registers (see Table 202 on page 229). 0xE000 D100:0xE000 DFFF
Reserved. 0xE000 E000:0xE000 EFFF
ARM processor memory and I/O map (see Table 72 on page 96). 0xE000 F000:0xE000 FFFF
MAC register map (see Table 77 on page 105). 0xE001 0000:0xE001 0FFF
Reserved. 0xE001 1000:0xE001 1FFF
Repeater slice register map (see Table 113 on page 133). 0xE001 2000:0xE001 2FFF
Reserved. 0xE001 3000:0xE003 FFFF
ARM 2DSP data buffer (512x32) ARM write only (see Table 72 on page 96). 0xE 004 0000 :0xE004 07FF
Reserved. 0xE004 0800:0xE005 FFFF
DSP2ARM data buffer (512x32) read-only (see Tabl e 72 on page 96). 0xE006 0000:0xE006 07FF
Reserved. 0xE008 0000:0xFFFF FFFF
0x0000 0000:0xBFFF FFFF
0xE000 0000:0xE000 0FFF
28 Agere Systems Inc.
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
4 Reset/Clock Management
The reset/clock management controller controls clock generation and clock selection; it maintains a real-time clock,
generates a power-on reset, and identifies the source of a reset condition. The block diagram of the reset/clock
management controller is shown below.
USB_ALT_CLK
PRESCALE_USB_CLK
PLL_CLK
XRTC0
XRTC1
EXT_CLK
RTC EXTERNAL
DIVIDER
REGISTER
*
(0xB0)
32.768 kHz
PLL
VCO FREQUENCY
PRESCALE_EXT_CLK
EXT_PROG_CLK
RTC_OSC_CLK
*
RTC
SWITCH
V
DD
V
SS
EXT_RST
SOFT_RST
POWER_UP
RESET
GENERATOR
WDG_RST
PWR_RST
* Indicates the default position or setting.
Figure 3. Reset/Clock Management Controller Block Diagram
USB
PRESCALER
(6) RST
*
PRESCALE_PLL_CLK
PLL
PRESCALER
(5) RST
*
EXT
PRESCALER
(0) RST
*
*
SLOW
CLK
SWITCH
RTC_CLK
EXTRTC
RESET SOURCE
REGISTER AND
CONTROLLER
*
USB CLK
SWITCH
FAST CLK
SWITCH
*
PLLC/CMEC
SLOW_CLK
ESCE
LOCK
KLC_CLK
INT_RST
RST0N
CLKOFF
PLL LOCK
DETECT
FAST_CLK
*
SYSTEM
SWITCH
CMRT
USB_CLK (48 MHz)
USBEXT/USBPLL
RF
(FROM PLL)
FB
57.6 MHz
SYS_CLK
EN_SDRCK
SDRCK
B_CLK
5-9074(F)
The reset/clock management controller contains the following features:
Clock Sources
EXT_CLK input from an external 11.52 MHz crystal. This provides an input to generate the system FAST_CLK,
■
as well as an input that can be divided for the system slow clock. The crystal is connected to XLO and XHI.
RTC_OSC_CLK input from an external 32.768 kHz crystal. This can provide an input to generate the RTC_CLK,
■
as well as the system SLOW_CLK.
The real-time clock circuit uses the 32 kHz RTC_CLK for maintaining elapsed real time and interrupting the
ARM 940T core at the programmed number of seconds if enabled. This real-time clock implementation does not
have a battery back-up feature so it is reset on all powerup resets. Pseudo real-time clock can be generated by
dividing EXT_CLK, using the RTC external divider regis ter in systems without a 32 kHz crystal.
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T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
4 Reset/Clock M anagement
(continued)
Dividers/Prescalers/PLL
RTC external divider register to generate a slower system clock from EXT_CLK for reduced power dissipation.
■
PLL (phase-locked loop) for generating a programmable PLL_CLK from the EXT_CLK:
■
— PLL prescaler to genera te a system FAST_CLK from PLL_CLK.
—EXT prescaler to generate a system FAST_CLK from EXT_CLK.
USB prescaler for generating the 48 MHz USB_CLK fr o m PLL_CLK.
■
MUX
System switch (please reference Figure 3 on page 29) for selecting SYS_CLK from either the FAST_CLK source
■
or from the SLOW_CLK source.
SLOW_CLK switch for selecting SLOW_CLK from either EXT_PROG_CLK or RTC_OSC_CLK.
■
RTC switch for selecting RTC_CLK from either EXT_PROG_CLK or RTC_OSC_CLK.
■
FAST_CLK switch for selecting FAST_CLK from either PRESCALE_PLL_CLK or PRESCALE_EXT_CLK.
■
USB_CLK switch for selecting USB_CLK from either USB_ALT_CLK or PRESCALE_USB_CLK.
■
Edge and zero/zero detectors on clock switching MUXes to ensure that all clock changes occur without glitching
the system clock.
Reset
Powerup reset generator for Ethernet PHYs. An external powerup reset circuit is required for chipwide
■
powerup.
External reset output RSTN maintained until released by software.
■
Table 3. Reset/Clock Management Controller Signals
Signal Description
Clock Signals
RTC_CLK This is the clock output to real-time clock block.
BCLK This is the main system clock.
KLC_CLK This is the clock th at time s the K L C blo ck .
SDRCK This is the SDRAM clock.
EXT_CLK This signal comes from a crystal oscillator buffer connected to XLO and XHI. It may be used as
a clock source for system and peripheral clocks.
USB_ALT_CLK This is an external clock source for USB_CLK.
USB_CLK Thi s signal goes to the USB block to clock it.
XRTC0
These two signals go to a 32.768 kHz crystal oscillator buffer and generate RTC_OSC_CLK.
XRTC1
MUX
EXTRTC This signal switches between either EXT_PROG_CLK or RTC_OSC_CLK for RTC_CLK.
EN_SDRCK This signal enables the SDRAM clock signal.
CMRT This signal is used to switch between FAST_CLK and SLOW_CLK for SYS_CLK.
ESCE This bit is used to switch between the EXT_PROG_CLK and RTC_OSC_CLK for the
SLOW_CLK sour ce .
USB_EXT/
USB_PLL
These signals switch between USB_ALT_CLK and USB_PRESCALE_CLK for the USB_CLK
source.
30 Agere Systems Inc.
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
4 Reset/Clock M anagement
(continued)
Table 3. Reset/Clock Management Controller Signals (continued)
Signal Description
PLLC/CMEC These signals switch between PRESCALE_PLL_CLK and PRESCALE_EXT_CLK for the
FAST_CLK source.
Reset
SOFT_RST
This is a soft reset input to the reset controller.
WDG_RST T his is the watchdog timer reset coming from the timer block.
EXT_RST This is the external hardware reset.
INT_RST This signal resets internal circuitr y.
RTS0N This signal is used as the external reset output.
Miscellaneous
RF, FB
RF (reference clock) and FB (feedback clock) come from the PLL and are used to determine
when the PLL is locked.
CLKOFF This signal is generated by the reset controller to kill B_CLK. B_CLK is the clock that governs
the ASB and APB inter faces. To kill the B_CLK, set the CLKOFF bit of the clock control reg-
ister to 1. Then write a 1 to the pause register (see T able 5 on page 36), causing CLKOFF to
go high and putting the chip in wait-for-interrupt (WFI) mode. To get out of this mode, one of the
two external interrupts should become active, provided the appropriate settings for the two
external interrupt registers in the PIC (programmable interrupt controller) are made.
.
4.1 Reset/Clock Management Controller Theory of Operation
The reset/clock management controller is governed by the control and status registers descr ibed below. The system powers up using the external 11.52 MHz crystal as the system clock. Although the PLL (phase-locked loop) is
enabled on powerup, the user needs to wait until the PLL stabilizes before switching to it as the system clock
source.
The system clock may be switched to an external, low-frequency 32 kHz oscillator by setting the appropriate bits in
the clock management register (see Table 7 on page 37) and clock control registers (see Table 10 on page 38).
4.1.1 Reset Operation
There are four reset signals that reset the IPT_ARM core and its peripherals.
1.External reset (EXT_RST)
2.Powerup reset (PWR_RST)
3.Watchdog timer reset (WDG_RST)
4. Software reset (SOFT_RST)
Within the reset status (control, clear) register (see Table 13 on page 40), there are four status bits identifying
the cause of the most recent full chip reset. In all cases, the core resumes fetching instruction at memory address
0x00000000.
POR indicates that the device is reset due to assertion of the powerup reset.
■
ER indicates that the exter nal reset pin was activated.
■
WR indicates that a device reset is forced by the watchdog timer (see Watchdog Timer on page 71) in the pro-
■
grammable timer unit.
SFT indicates a software reset (see Table 11 on page 39).
■
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T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
4 Reset/Clock M anagement
(continued)
The four conditions are mutually exclusive, and appropriate actions can be taken within the boot code depending
on which bit is set.
When one of these reset sources becomes active, the appropriate reset source is recorded in the reset status
(control/clear) register (see Table 13 on page 40). A reset signal is sent to the ARM 940T core and all of the
peripheral blocks are reset. The internal resets are deassert ed synchronously with the falling edge of the system
clock after the source of the reset is deasserted. The RTS0N pin is maintained active-low until released by software
via the reset peripheral control (read, clear, set) register (see Table 14 on page 41).
A reset from any of the four sources previously mentioned immediately causes the following:
The clock source is switched to the 11.52 MHz external input with the clock divider set to 1.
■
The PLL is powered up and its programmable registers are preset.
■
The EMI (external memory interface) and the peripheral devices are powered up in their default power-on state.
■
(In general, most register bits in the reset/clock management controller are set to a default on state, whereas
most peripheral registers are reset to 0. Any exceptions to this will be specifically noted when the register bits are
discussed.)
The internal reset signal (INT_RST), as well as the external reset (RTS0N) signal, is asserted immediately when-
■
ever any of the four reset sources are asserted. The external RTS0N signal remains active until cleared in the
reset peripheral control register (read, clear, set); see Table 14 on page 41. Deasserting RTS0N is a ccom-
plished by writing 0 to the ERS bit in the reset peripheral con trol clear register.
4.1.2 Operation of the Clock Switching Logic
The clock switching logic is controlled by software. F or example, when switching from the external clock to the PLL
clock, the PLLE enable bit in the clock control register (see Table 10 on page 38) is set to 1 to enable the PLL,
then the PLLC bit in the clock management register (see Table 7 on page 37) is set to 1. The PLL can be shut
down to conserve power by resetting the enable bit (PLLE).
4.1.2.1 PLL Operation
The PLL oscillator is controlled by PLLE of the clock control register (see Table 10 on page 38). The PLL gener-
ates a clock signal when PLLE is set to 1. It typically takes about 30 µs for the PLL oscillator to resta rt and lock in
from the inactive state (with a maximum of 250 µs).
The input to the PLL comes from the input clock EXT_CLK. The PLL cannot operate without this external input
clock.
To use the PLL cloc k, first stabilize the clock output and then lock it to the programmed frequency. The clock switching logic waits until lock occurs before switching to the PLL clock.
The frequency of the PLL output clock (PLL_CLK) is determine d by the values loaded into the 3-bit N divider and
the 5-bit M divider (see Table 12 on page 39). When the PLL clock is selected and locked (by setting PLLC in the
clock management register) the frequency of PLL_CLK is related to the frequency of EXT_CLK by the following
equation:
PLL_CLK = EXT_CLK x (MBITS + 1)/(NBITS + 1)
The c oding of the Mbits and Nbits is described in Table 12 on page 39.
For example:
The frequency of PLL_CLK is designed to be 288 MHz in this application.
288 MHz = 11.52 MHz x (24 + 1)/(0 + 1)
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
4 Reset/Clock M anagement
(continued)
The default values for MBITS and NBITS in this design are: MBITS = 24 (0x18) and NBITS = 0 (0x0).
To use the PLL clock the following steps should be taken by software:
Program MBITS and NBITS. Choose the MBITS and NBITS values in the PLL control register (see Table 12
■
on page 39) by selecting the lowest value for NBITS and the appropriate value of MBITS required to obtain the
desired frequency of the internal clock.
The clock switching logic waits for the PLL to lock before switching to the PLL as the system clock. Any write to
■
the PLL control register (see Table 12 on page 39) resets the lock flag and causes the clock switching logic to
switch to EXT_CLK.
The lock-in time depends on the operating frequency and the values programmed for MBITS and NBITS.
■
The frequency of the PLL output clock (PLL_CLK) should fall within t he range defined in the data sheet. Change
■
the bits in the PLL control register (see Table 12 on page 39) only while the PLL is not providing the internal
clock source.
To select PLL as the SYS_CLK, set PLLC in the clock man age m ent registe r (see Table 7 on page 37) to 1.
■
To deselect PLL as the SYS_CLK, select another clock in the clock management register by setting either
■
CMRT or CMEC to 1.
When an external interrupt is encountered while in WFI mode (see Section 4.2.1 on page 35), the system automatically switches back to the last fast clock.
4.1.3 Latency
The switch between the EXT_CLK and PLL_CLK is synchronous. This causes the actual switching to take place
several cycles after the PLLC or the CMEC bit is changed. During th is time, actual code is executed. The PLL is
not disabled until the PLLE bit in the clock control register (see Table 10 on page 38) is set to 0. To find out when
the switching is complete, poll the clock status register (see Table 8 on page 37).
4.1.4 Real-Time Clock (RTC) The real-time clock (RTC_CLK) defaults to a 32.768 kHz clock generated by a crystal oscillator c onnect ed at
XRTC0 and XRTC1. The input clock is divided by 32,768 to generate a clock with a one-second period that incre-
ments a 29-bit seconds counter. In addition, it can generate int errupts at a programmed time. Some f eatures of the
RTC are:
17-year time interval with 1 second resolution.
■
Programmed time alarm interrup t.
■
Clock source selectable between RTC_OSC_CLK and EXT_PROG_CLK.
■
To use a real-time alarm interrupt, the following steps have to take place:
1.The clock source is selected. Either RTC_OSC_CLK or EXT_PROG_CLK.
2.The appropriate seconds value is loaded into the RTC seconds alarm register (see Table 18 on page 44).
3.The RTC clock interrupt is enabled in the RTC interrupt enable register (bit 0 AI ENA)
(see Table 22 on page 45).
4.The RTC interrupt status register bit AI (see Table 21 on page 45) is set to 1 when the timer RTC alarm
expires.
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Advanced RISC Machine (ARM ) July 2001
4 Reset/Clock M anagement
(continued)
The RTC circuitry does not have an external uninterruptable power supply, therefore, it will not keep time when
power is turned off to the IPT_ARM.
The RTC seconds alarm register (see Table 18 on page 44) is reset to 0 during powerup reset, or hardware reset,
but this register is not affected by the other reset sources.
A block diagram of the real-time clock is shown in Figure 4 below.
EXTRTC
XRTC0
XRTC1
CRYSTAL
OSCILLATOR
(32.768 kHz)
PERIPHERAL BUS
RTC_CLK
CLOCK
SELECT
SECONDS
COUNTER
SECONDS
ALARM
DIVIDER
RTC INTERRUPT
5-8231 (F)
Figure 4. Real-Time Clock Block Diagram
34 Agere Systems Inc.
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
4 Reset/Clock M anagement
(continued)
4.2 Reset/Clock Management Registers
The reset/clock management registers are used to program the status of the clock and power configuration of the
system.
Table 4. Reset/Clock Controller Register Map
Register Address
Pause register (see Table 5 on page 36).
Clock management register (see Table 7 on page 37).
Reserved. 0xE000 0008
Reserved 0xE000 000C
Version ID re gister
Clock status register (see Table 8 on page 37).
Clock control register (see Tabl e 10 on page 38).
Reserved. 0xE000 001C:0xE000 001F
Soft reset register (see T able 11 on page 39).
PPL control register (see Table 12 on page 39).
Reserved. 0xE000 0028:0xE 000 002C
Reset status (control, clear) register (see Table 13 on page 40).
Reserved. 0xE000 0038:0xE000 003F
Reset peripheral control (read, clear , set) register (see Table 14 on page 41).
RTC external divider register (see Table 15 on page 42).
RTC clock prescale register (see Table 16 on page 42).
RTC control register (see T able 17 on page 43).
RTC seconds alarm register (see Table 18 on page 44).
RTC seconds count register (see Table 19 on page 44).
RTC divider register (see Table 20 on page 45).
RTC interrupt status register (see Table 21 on page 45).
RTC interrupt enable register (see Table 22 on page 45).
Reserved. 0xE000 C018:0xE000 C01C
0xE000 0030:0xE000 0034
0xE000 0040:0xE000 0048
0xE000 0054:0xE000 005C
0xE000 0000
0xE000 0004
0xE000 0010
0xE000 0014
0xE000 0018
0xE000 0020
0xE000 0024
0xE000 0050
0xE000 C000
0xE000 C004
0XE000 C008
0xE000 C00C
0xE000 C010
0xE000 C014
4.2.1 Pause Register
The pause register put s the chip into wait-for-interrupt (WFI) mode. WFI mode is used to conserve power by turning off clocks to the pe rip herals. Writing a 1 to this bit cause s the system to go into WFI mode after completing any
active memory requests. WFI mode is used to conserve power by turning the clocks off.
Notes: CLKOFF should always be set when using WFI mode. When the system is shut down using CLKOFF (see
Table 10 on page 38) the SDRAM will not refresh. Valid data must be preser ved in the SDRAM.
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T8302 Internet Protocol Telephone Data Sheet
Advanced RISC Machine (ARM ) July 2001
4 Reset/Clock M anagement
(continued)
Table 5 shows the format of the pause register.
Table 5. Pause Register
Address 0xE000 0000
Bit #
Name
31:1 0
RSVD PAUSE
Bit # Name Description
31:1 RSVD Reserved.
0 PAUSE Specifies if the system is in wait-for-interrupt (WFI) mode.
If 1, the system is in WFI mode.
If 0, the system is in normal mode.
4.2.2 Version ID Register
The version ID register contains the chip identification and version information for the device. This register is read
only. The format of the version ID register is shown in Table 6.
Table 6. Version ID Register 0xE000 0010
Address 0xE000 0010
Bit #
Name
31:16 15:0
Device ID Version ID
Bit # Name Description
31:16
15:0
Device ID These bits will always contain 0x8302.
Version ID These bits will contain the version identification of
the device.
4.2.3 Clock Management Register
The clock management register selects the source of the clock to the chip blocks. Writing a 1 to a bit in this register causes the clock switching logic to switch to the selected clock. If more than one bit is set, the lowest numbered bit takes precedence.
Regarding the USBEXT and USBPLL control bits: if both are set, then USBEXT tak es precedence. For example, if
bits 1 and 0 are both written to 1, the clock switches to the USB_ALT_CLK. If all zeros are written, nothing hap-
pens.
CMRT, PLLC, and CMEC control the source of the system clock. The system clock can be either the slow clock,
the PLL clock or the external 11. 52 MHz crystal. Table 7 shows the format of the clock manageme nt regi s te r.
.
36 Agere Systems Inc.
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
4 Reset/Clock M anagement
Table 7. Clock Management Register
Bit #
Name
Bit # Name Description
31:6 RSVD Reserved.
5 USBEXT Switches USB clock source (USB_CLK) to USB_ALT_CLK.
4 USBPLL Switches USB clock source (USB_CLK) to the PRESCALE_USB_CLK.
3 EXTRTC Controls the source of the real-time clock (RTC_CLK).
2 CMRT CMRT switches the system clock source (SYS_CLK) to the slow clock (SLOW_CLK).
1 PLLC PLLC switches the system clock source (SYS_CLK) to the PLL clock.
31:6 5 4 3 2 1 0
RSVD USBEXT USBPLL EXTRTC CMRT PLLC CMEC
If 1, the clock switching logic switches the USB clock to the USB_ALT_CLK and then clears
this bit.
If 0, the clock switching logic is not activated.
If 1, the clock switching logic switches the USB_CLK to the PRESCALE_USB_CLK and then
clears this bit.
If 0, the clock switching logic is not activated.
If 1, the RTC_CLK is driven by the RTC_OSC_CLK.
If 0, the RTC_CLK is driven off of the RTC external divider register on EXT_CLK.
If 1, the clock switching logic switches the system clock source (SYS_CLK) to the
SLOW_CLK, and then clears this register.
If 0, the logic to switch to the SLOW_CLK is not activated.
(continued)
Address 0xE000 0004
If 1, the clock switching logic s witches the system clock so ur ce to the PLL clock, and then
clears this register.
If 0, the logic to switch to the PLL is not activated.
0 CMEC CMEC switches the system clock source (SYS_CLK) to the external clock (EXT_CLK).
If 1, the clock switching logic switches the system clock source to EXT_CLK, and then clears
this register.
If 0, the logic to switch to EXT_CLK is not activated.
4.2.4 Clock Status Register
The clock status register indicates the current clock source for the system clock (SYS_CLK) and the previous
fast cl ock source (FAST_CLK). CSC and PFSC default to 00. Table 8 shows the format of the clock status regis-
ter.
Table 8. Clock Status Register
Address 0xE000 0014
Bit #
Name
Bit # Name Descri ption
31:4 RSVD Reserved.
3:2 PFSC Identifies the previous fast clock source (FAST_CLK); see Ta ble 9 below.
1:0 CSC Identifies the clock that is the current source of the system clock
31:4 3:2 1:0
RSVD PFSC CSC
(SYS_CLK); see Table 9 below.
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Advanced RISC Machine (ARM ) July 2001
4 Reset/Clock M anagement
4.2.5 System Clock Source Encoding Table 9 shows the encoding of the clock sources for the clock status register (Table 8).
Table 9. System Clock Source Encoding
Bits (1:0 or 3:2) Description
00 External clock (PRESCALE_EXT_CLK).
01 Phase-locked loop clock (PRESCALE_PLL_CLK).
10 Slow clock (SLOW_CLK).
11 Reserved.
4.2.6 Clock Control Register The clock control register configures basic clock functions. Table 10 shows the format of the clock control regis-
ter.
Table 10. Clock Control Register
Bit #
Name
Bit # Name Description
31:4 RSVD Reserved.
3 ESCE External slow clock enable.
31:4 3 2 1 0
RSVD ESCE PLLE RSVD CLKOFF
(continued)
Address 0xE000 0018
If 1, the slow clock source is the EXT_CLK divided by the specified value in the RTC
external divider register (see Table 15 on page 42).
If 0, the real-time clock crystal (RTC_OSC_CLK) is the SLOW_CLK source.
2 PLLE Enables the PLL. This bit is reset to 1.
If 1, the PLL is enabled.
If 0, the PLL is disabled.
1 RSVD Reserved.
0 CLKOFF Determines if the CLKOFF mode feature is active. (CLKOFF mode shuts off all of the
clocks to the core and to the peripherals when in WFI mode.)
If 1, CLKOFF mode is active.
If 0, CLKOFF mode is not active.
Note: CLKOFF should always be set to 1 when using WFI mode.
This bit is reset to 0.
4.2.7 Soft Reset Register
When written, the soft reset register address causes a software reset to occur. When read, all zeros will be
returned.
Note: Soft reset has no effect on the RTC block.
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
4 Reset/Clock M anagement
Table 11 shows the format of the soft reset register.
Table 11. Soft Reset Register
Bit #
Name
Bit # Name Description
31:0 SOFT RESET Writing any value to this register causes a soft reset.
4.2.8 PLL Control Register The PLL control register co nfigures the PLL. Table 12 shows the format of the PLL control register.
Table 12. PL L Cont rol Reg ister
Bit #
Name
Bit # Name Description
31:12 RSVD Reserved. Tied to 0.
11 BYPASS Active-high, reset to 0.
10:8 NBITS Encodes NB ITS. 0 ≤ NBITS ≤ 7.
31:12 11 10:8 7:6 5 4:0
RSVD BYPASS NBITS RSVD FRANGE MBITS
If 1, PLL output = PLL input.
This value is used as a divisor to set the PLL frequency. Actual divisor used is NBITS + 1.
(continued)
Address 0xE000 0020
31:0
SOFT RESET
Address 0xE000 0024
Reset = 00.
7:6 RSVD Reserved. Tied to 0.
5 FRANGE Frequency range.
If PLL output is 100 MHz—400 MHz then set to 0.
If PLL output is 400 MHz—500 MHz then set to 1.
Reset = 0.
4:0 MBITS E ncodes MBITS. 0 ≤ MBITS ≤ 31.
This value is used as a multiplier to set the PLL frequency . Actual multiplier used is MBITS + 1.
Reset = 24 (0x18).
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4 Reset/Clock M anagement
4.2.9 Reset Status (Control/Clear) Registers
The reset status (control/clear) registers identify the source of the last chip reset. The bit in the register corresponding to the reset source is set to 1 and the other bits are cleared. Each bit is cleared by writing a 1 to the corresponding bit in the reset status clear register. Table 13 shows the for mat of the reset status (control/clear)
register.
Table 13. Reset Status (Control/Clear) Register
Address—Control 0xE000 0030, Clear 0xE000 0034
Bit #
Name
Bit # Name Description
31:4 RSVD Reserved.
3 SFT SF T identifies the last reset as a soft reset.
2 WR Identifies the last reset as a warm reset (caused by the watchdog timer).
1 POR Identifies the last reset as a powerup reset.
31:4 3 2 1 0
RSVD SFT WR POR ER
If 1, a soft reset has occurred.
If 0, the last reset was not a soft reset, or the bit was cleared.
If 1, a warm reset has occurred.
If 0, the last reset was not a warm reset, or the bit was cleared.
(continued)
s
If 1, a powerup reset has occurred.
If 0, the last reset was not a powerup reset, or the bit was cleared.
0 ER Identifies the last reset as an external reset.
If 1, an external reset has occurred.
If 0, the last reset was not an external reset, or the bit was cleared.
4.2.10 Reset Peripheral Control (Read, Clear, Set) Registers
The reset peripheral control (read, clear, set) registers provide the IPT_ARM with a mechanism for resetting an
individual peripheral without affecting other elements in the system. A 1 in a bit location corresponding to its
assigned peripheral holds the section in reset until the bit is cleared. Individual bits can be set by writing a 1 to the
corresponding bit location in the reset peripheral control (set) register. Values are read from the reset periph-
eral (read) register. Individual bits can be cleared by writing a 1 to the corresponding location in the reset periph-
eral (clear) register. Table 14 shows the format of the reset peripher al control (read, clear, set) register.
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4 Reset/Clock M anagement
Table 14. Reset Peripheral Control (Read, Clear, Set) Register
Address—Read 0xE000 0040, Clear 0xE 000 0044, Set 0xE000 0048
Bit #
Name
Bit #
Name
Bit #
Name
Bit # Name Description
31: 18 RSVD R eserved.
17 EREP Ethernet repeater circuit.
16 RSVD Reserved.
15 EMAC E t hernet MAC.
14 DCC DSP communications controller.
13 KLC Key and lamp controller.
12 RTC Real-time clock controller.
11 UART Asynchronous communications controller channel 1 to UART adjunct.
10 IrDA Asynchronous communications controller channel 0 to IrDA receiver.
9 USB Universal serial bus controller.
8 PIO P aral l el input output controller.
7 SSI Synchronous ser ial input output controller.
6 DMA Direct memory access controller.
5 INTC Interrupt controller.
4:3 RSVD Reserved.
2 ITIMR Interval and watchdog timer.
1 RSVD Reserved.
0 ERS External reset bit, (RTS0N).
31:18 17 16 15 14 13 12
RSVD EREP RSVD EMAC DCC KLC RTC
11 10 9 8 7 6 5
UART IrDA USB PIO SSI DMA INTC
4 3 2 1 0 — —
RSVD RSVD ITIMR RSVD ERS — —
(continued)
s
Note: This register is initialized to all zeros on reset except for the ERS (bit 0), which is set to 1 upon rese t.
4.2.11 RTC External Divider Register
The RTC external divider register allows the 11.52 MHz external clock (EXT_CLK) to be divided down to produce a pseudo real-time clock in applications where a real-time crystal and real-time accuracy are not needed. The
RTC external divider register is a 16-bit register whose value is loaded into a down counter every time the down
counter reaches 0. There is a toggle flip-flop that changes state whenever the counter reaches 0. The output clock
rate is given by the following equation:
EXT_PROG_CLK = EXT_CLK/ECD/2.
For a pseudo real-time clock of 32727.27 Hz the programmed value for ECD becomes 176 (0xB0).
Table 15 shows the format of the RTC external divider register.
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4 Reset/Clock M anagement
Table 15. RTC External Divider Register
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15:0 ECD RTC divider register. The clock changes state from high to low or low to high every time the
4.2.12 RTC Clock Prescale Registers
The RTC clock prescale registers indicate the value by which to divide the input clock to get the current clock. If
all zeros, the input clock is passed on without division. Only one of the divisor bits in the RTC clock prescale reg-
isters may be set at one time. If more than one bit is set, the lowest order bit set will determin e the divisor.
The format for each of the RTC clock prescale registers is identical and is as follows:
Prescaler Address Prescaler Input Prescaler Output
EXT_PRESCALER 0xE000 0054 EXT_CLK PRESCALE_EXT_CLK
PLL_PRESCALER 0xE000 0058 PLL_CLK PRESCALE_PLL_CLK
USB_PRESCALER 0xE000 005C USB_CLK PRESCALE_USB_CLK
31:16 15:0
RSVD ECD
RTC divider regis te r cou nts down to 0. It is then reloaded with the ECD value entered by the
user.
(continued)
Address 0xE000 0050
Table 16. RTC Clock Prescale Registers
Addresses 0xE000 0054:0xE000 005C
Bit #
Name
Bit # Name Description
31: 7 RSVD Reserved.
6 D16 Indicates that the prescaler input is divided by 16.
5 D8 Indicates that the prescaler input is divided by 8.
4 D6 Indicates that the prescaler input is divided by 6.
3 D5 Indicates that the prescaler input is divided by 5.
2 D4 Indicates that the prescaler input is divided by 4.
31:7 6 5 4 3 2 1 0
RSVD D16 D8 D6 D5 D4 D3 D2
If 1, divide the clock by 16.
If 0, do not divide the clock by 16.
If 1, divide the clock by 8.
If 0, do not divide the clock by 8.
If 1, divide the clock by 6.
If 0, do not divide the clock by 6.
If 1, divide the clock by 5.
If 0, do not divide the clock by 5.
If 1, divide the clock by 4.
If 0, do not divide the clock by 4.
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4 Reset/Clock M anagement
Table 16. RTC Clock Prescale Registers (continued)
Bit # Name Description
1 D3 Indi cates that the prescaler input is divided by 3.
If 1, divide the clock by 3.
If 0, do not divide the clock by 3.
0 D2 Indi cates that the prescaler input is divided by 2.
If 1, divide the clock by 2.
If 0, do not divide the clock by 2.
4.2.13 RTC Control Register
The RTC c ontrol regi ster selects the real-time clock source and enables the RTC counters. Table 17 shows the
format of the RTC control register.
Table 17. RTC Control Register
Bit #
Name
Bit # Name Description
31:8 RSVD Reserved.
7 ENA Cr ystal oscillator enable. Enables the analog portio n of the crys t al oscillator.
31:8 7 6:5 4 3 2 1 0
RSVD ENA RSVD BYP RSVD RSVD IE CS
(continued)
Address 0xE000 C000
If 1, the analog portion of the crystal oscillator is active and using current.
If 0, the analog portion of the crystal oscillator is not active and is not using current.
This bit is set to 0 if the RTC is not being used or bypass mode is set.
This bit is set to 1 on reset.
6:5 RSVD These bits are set to 11 on reset.
4 BYP Bypass mode. Bypasses the crystal oscillator circuit.
If 1, a crystal is connected between pins XRTC0 and XRTC1.
If 0, the CMOS clock on pin XRTC0 is used directly as the clock input.
This bit is set to 0 on reset.
3:2 RSVD Reserved.
1 IE Increment enable. Enables incrementing the RTC divider re gister
(see Table 20 on page 45).
If 1, increment of the RTC divider re g ister is enabled.
If 0, increment of the RTC divider re g ister is disabled.
This bit is reset to 0 on powerup.
0 CS Clock select. Sel e cts th e clock source for the RTC divider register
(see Table 20 on page 45).
If 1, the clock is from the crystal, or an external CMOS clock.
If 0, the clock is the divided SYSTEM_CLK.
This bit is reset to 1 on powerup.
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4 Reset/Clock M anagement
4.2.14 RTC Seconds Alarm Register The real-time clock interrupt (see Table 26 on page 51) is asserted when the values in the RTC seconds alarm
register (Table 18) and RTC seconds count register (Table 19) are equal. If the RTC interrupt is enabled
(AI ENA) in the RTC interrupt enable register (see Table 22 on page 45) and in the PIC (programmable interrupt
controller), an interrupt to the processor will occur. The RTC seconds alarm register is reset to 0 during powerup
reset, or hardware reset, but this register is not affected by the other reset sources. Table 18 shows the format of
the RTC seconds alarm register.
Table 18. RTC Seconds Alarm Register
Bit #
Name
Bit # Name Description
31:29 RSVD Reserved.
28:0 SA Represents time in clock ticks.
4.2.15 RTC Seconds Count Register
The RTC seconds count register shows the current time in seconds. If UCP is 1 when read, an update occurred
and the value is invalid and should be read again. Updates occur once per second. Table 19 shows the format of
the RTC seconds co unt register.
31:29 28:0
RSVD SA
(continued)
Address 0xE000 C004
Table 19. RTC Seconds Count Register
Address 0xE000 C008
Bit #
Name
Bit # Name Description
31 UCP Update cycle occurred.
30:29 RSVD Reserved.
28:0 SC Represents time in clock ticks.
4.2.16 RTC Divider Register The RTC divider register contains a count of the clocks that have occurred since the last time the RTC seconds
count register (Table 19) was updated. This register is incremented once per input clock cycle. This register is
written only during testing, when IE of the RTC control register (see Table 17 on page 43) is set to 0. Otherwise,
an interr upt illegal w r i te e r ro r is generated. Table 20 shows the format of the RTC divider register.
31 30:29 28:0
UCP RSVD SC
If 1, an update cycle occurred during a read access.
If 0, the value returned was stable.
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4 Reset/Clock M anagement
Table 20. RTC Divider Register
Bit #
Name
Bit # Name Description
31:15 RSVD Reser ved.
14:0 CCC Clock counter.
4.2.17 RTC Interrupt Status Register This register displays the current status of the IWI and AI interrupts. Table 21 shows the format of the RTC inte r -
rupt status register.
Table 21. RTC Interrupt Status Register
Bit #
Name
Bit # Name Description
31:2 RSVD Reserved.
1 IWI Illegal write interrupt. Set whenever software attempts to write to the RTC divider regis-
31:2 1 0
RSVD IWI AI
ter (see Ta ble 20 on page 45) while it is enabled, or when software attempts to write to
the RTC seconds count register (see Table 19 on page 44) while the divider is enabled
and an updat e to the seconds counter is about to be made.
(continued)
Address 0xE000 C00C
31:15 14:0
RSVD CCC
Address 0xE000 C010
To reset t h is b i t w rite a 1 to it.
0 AI Alarm interrupt. Set when seconds count = alarm regist er.
To clear this bit write a 1 to it.
4.2.18 RTC Interrupt Enable Register This register enables the interrupts in the RTC interrupt status register. Table 22 shows the format of the RTC
interrupt enable register.
Table 22. RTC Interrupt Enable Register
Address 0xE000 C014
Bit #
Name
Bit # Name Description
31:2 RSVD Reserved.
1 IW I ENE
0 AI ENA
31:2 1 0
RSVD IWI ENA AI ENA
Illegal write interrupt enable. If this bit and the IWI bit is set, IRQ_ RT C will be active.
Default = 0 on reset.
Alarm interrupt enable. If this bit is set and the AI bit is set, the real-time clock interrupt
will be as s erted in th e interrupt request status register IRSR (see Table 26 on page
51). The appropriate bit in the interrupt request enable register IRER (see Table 27 on
page 51) must also be set.
Default = 0 on reset.
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4 Reset/Clock M anagement
(continued)
4.3 Operation on Reset
Upon all resets, the reset/clock management controller performs the following:
The PLL is enabled with its default values.
■
All status register bits are reset to 0, except the reset status (control, clear) register (see Table 13 on page
■
40) that is set to the appropriate source and the exceptions specifically noted in the register descriptions.
The source clock is set to the extern al input clock.
■
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5 Programmable Interrupt Controller (PIC)
The PIC receives signals from 15 interrupt sources. The PIC groups and prioritizes these signals, and drives the
two interrupt signals at the interface to the core. Features of the PIC are as follows:
15 maskable interrupt inputs.
■
Two programmable priority groups (IRQ and FIQ).
■
15 programmable priority levels.
■
5.1 Interrupt Controller Operation
The interrupt controller receives 15 interrupt request signals, IRQ[15:1] as input. The ordering of the IRQ signals is
purely arbitrary and does not imply any relative priority. The interrupt request enable register, IRER (see Table
27 on page 51) provides a central point where the interrupts are enabled or disabled for the interrupt request status
path. In particular, the interrupt signals on input lines IRQ[15:1] are logically ANDed with IRER[15:1], and
the results are transferred to the interrupt request status register IRSR (see Table 26 on page 51). At any
time, the core can read the IRSR in order to check for pending interrupts.
The inter r up t pr io rity control registers IPCR[15:1] (see Table 29 on page 52) provide a means by which the rel-
ative priority of the interrupts are assigned programmatically. Each IPCR has an index field that contains the number of the interrupt assigned to that particular prior ity level. The IPCRs have an implicit priority ordering, where
IPCR1 has the highest priority, and IPCR15 has the lowest priority. At reset, all of the IPCRs are disabled.
The IPT_ARM core interface includes two maskable interrupt request inputs, IRQ and FIQ, where an active FIQ
request pre-empts an active IRQ request. Each interrupt is assigned to either the IRQ group or the FIQ group by
assigning a 1 (FIQ) or a 0 (IRQ) to TYP of the corresponding interrupt priority control register (see Table 29 on
page 52). Each group is handled independently. These inputs are referred to as core IRQ and core FIQ.
The following shows a typical setup method for interrupts:
Enable the interrupt in the desired peripheral's interrupt enable register .
■
Enable the specific peripheral interrupt in the interrupt request enable register IRER (Set); see Table 27 on
■
page 51.
Enable the specific interrupt priority in the interrupt priority enable register IPER (Set); see Table 33 on page
■
54.
Assign IRQs from the desired peripheral to a priority level (IS) and type (TYP) using the interrupt priority c o n-
■
trol register N (see Table 29 on page 52).
When active the interrupt will be displayed in the interrupt request status register. The interrupt in-service
■
register (ISRI or ISRF) contains the encoded value of the current highest priority interrupt.
To get the ARM core to process the interrupt, clear the F or I bit in the ARM current program status register
■
(CPSR). See the ARM 940T Technical Reference Manual for a register description.
To clear interrupts 3 through 15, remove the source of the interrupt in the peripheral registers. To clear interrupt 1
■
or 2, write to the C1 or C2 bit in th e interrupt request source clear register IRQESCR (see T able 32 on page
54).
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5 Programmable Interrupt Controller (PIC)
CORE
IRQ
ISRI
FIQ
ISRF
IRQ[2:1]
Figure 5. Interrupt Controller Block Diagram
PRIORITY
AND
CONTROL
LOGIC
IPCR[15:1]
IPER[15:1]
PERIPHERAL BUS
EDGE/LEVEL
SENSE
CONTROL
LOGIC
PERIPHERALS
(continued)
IRSR
IRQ[15:9]
IRQ[7:3]
&
IRER[15:1]
SOFT
INTERRUPT
IRQ[8]
5-8230(F)
5.1.1 Interrupt Registers Table 23. Interrupt Registers
Interrupt Register Description
IRSR Interrupt request status register (see Table 26 on page 51).
IRER Interrupt request enable register (see Table 27 on page 51).
IRQSR In terru pt request soft register (see Table 28 on page 52).
IPCR Interrupt priority control register (see Table 29 on page 52).
ISRI Interrupt in-service register for core IRQ (see T able 30 on page 53).
ISRF Interrupt in-service register for core FIQ (see Table 30 on page 53).
IRQESCR Interrupt request source clear register (see Table 32 on page 54).
IPER Interrupt priority enable regi ster (s ee Table 33 on page 54).
EICR External int errupt control register (see Table 34 on page 55).
For FIQ and IRQ, the interrupt control logic determ ines which interrupt source is to be serviced next and sets the
value for that interrupt in the in terru pt in-ser vice register, ISRI or ISRF (see Table 30 on page 53). The interrupt
controller issues IRQ or FIQ signals to the core. If an interrupt of higher priority is latched in the IRSR before the
interrupt in-service register is read, the interrupt in-service register is updated with the value of the higher-priority interrupt. However , if the interrupt in-service register is read, the current register value is frozen until the corresponding bit in the IRSR register is reset to 0.
Prior to returning from the interrupt service routine, software must clear the interrupt from the block that sources it.
Interrupts (with the exception of the two externa l interrupts ) cannot be cleared by the PIC itself. The two external
interrupts could be cleared from the IRSR[1:0] by writing a 1 to the appropriate bit of the interrupt request source
clear register (IRQESCR); see Table 32 on page 54. H owever, if the external inte rrupt control line is stil l a t th e
interrupt generating level, the interrupt will persist in the IRSR.
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5 Programmable Interrupt Controller (PIC)
The interrupt service routine also checks the IRSR for other pending interrupt requests and handles these interrupts before returning.
The IRQ request signals (for interrupt in-service) are shown in Table 24 below.
Table 24. Interrupt Request Signals (IRQ)
Interrupt R equest Line I nterrupt Type
IRQ1 External interrupt 1.
IRQ2 External interrupt 2.
IRQ3 PPIO software interrupt.
IRQ4 DMA interrupt.
IRQ5 Timer interrupt.
IRQ6 DSP interrupt.
IRQ7 Repeater interrupt.
IRQ8 Software interrupt.
IRQ9 UART_ACC interrupt.
IRQ10 Ethernet MAC interrupt.
IRQ11 IrDA_ACC interrupt.
IRQ12 USB interrupt.
IRQ13 SSI interrupt.
IRQ14 KLC interrupt.
IRQ15 Real-time clock interrupt.
(continued)
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5 Programmable Interrupt Controller (PIC)
(continued)
5.2 Programmable Interrupt Controller Registers
Table 25. Programmable Interrupt Controller Register Map
Register Address
Interrupt request status register IRSR (see Table 26 on page 51).
Reserved. 0xE000 1004
Interrupt request enable set register IRER (IRESR) (see Table 27 on page 51).
Interrupt request enable clear register IRER (IRECR) (see Table 27 on page 51).
Interrupt request soft register IRQSR (see Table 28 on page 52).
Reserved. 0xE000 1014
Interrupt priority control register 1 (see Table 29 on page 52).
Interrupt priority control register 2.
Interrupt priority control register 3.
Interrupt priority control register 4.
Interrupt priority control register 5.
Interrupt priority control register 6.
Interrupt priority control register 7.
Interrupt priority control register 8.
Interrupt priority control register 9.
Interrupt priority control register 10.
Interrupt priority control register 11.
Interrupt priority control register 12.
Interrupt priority control register 13.
Interrupt priority control register 14.
Interrupt priority control register 15.
Reserved. 0xE000 1054—
Interrupt in-service register ISR (ISRI) (see Table 30 on page 53).
Interrupt in-service register ISR (ISRF) (see Table 30 on page 53).
Interrupt request source clear register IRQESCR (see Table 32 on page 54).
Interrupt priority enable set registers IPER (IPESR) (see Table 33 on page 54).
Interrupt priority enable clear registers IPER (IPECR) (see Table 33 on page 54).
External interrupt control registers (see Table 34 on page 55).
0xE000 1000
0xE000 1008
0xE000 100C
0xE000 1010
0xE000 1018
0xE000 101C
0xE000 1020
0xE000 1024
0xE000 1028
0xE000 102C
0xE000 1030
0xE000 1034
0xE000 1038
0xE000 103C
0xE000 1040
0xE000 1044
0xE000 1048
0xE000 104C
0xE000 1050
0xE000 1090
0xE000 1094
0xE000 1098
0xE000 109C
0xE000 10A0
0xE000 10A4
0xE000 10A8—
0xE000 10AC
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5 Programmable Interrupt Controller (PIC)
5.2.1 Interrupt Request Status Register IRSR
The interrupt request status register IRSR indicates the status of the latched IRQ request inputs. The IRSR bits
are enabled by the bits in the interrupt request enable register, i.e., the bit will not bec ome set unles s the c or re sponding bit in the interrupt request enable register is also set. Table 26 shows the format of interrupt requ est
status register IRSR.
Table 26. Interrupt Request Status Register IRSR
Address 0xE000 1000
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
n* In* IRQn status. Indicates that an interrupt is active from interrupt request n.
0 RSVD Reserved.
31:16 15:1 0
RSVD In* RSVD
If 1, there is an active interrupt from interrupt source n.
If 0, there is no interrupt pending from interrupt source n.
IRQ1 and IRQ2 are cleared by writing a 1 to bit 1 or 2 of the IRQESCR. Bits[3:15} are cleared
by clearing the interrupt in their corresponding peripheral interrupt registers.
(continued)
* Replace n with any one of the following bits: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 , or 15.
5.2.2 Interrupt Request Enable Registers IRER (Set, Clear) The interrupt reques t enable regis ters IRER enable or disable an interrupt request signal. Upon disabling an
IRER bit, the corresponding bit in the interrupt request status register IRSR is cleared.
The interrupt reques t enable regis ters IRER have a dual mechanism for setting and clearing the enable bits.
Enable bits are allowed to be set or cleared independently with no knowledge of the other bits in the interrupt
request enable register IRER.
To set the enable bits, perform a write to the interrupt request enable set register IRESR. Each data bit that is
set to 1 enables the corresponding interrupt. To clear the enable bits, perform a write to the i nte rr upt req uest
enable clear register IRECR. Each data bit that is set to 1 disables the corresponding interrupt. These registers
are set to 0 on all reset conditions. Table 27 shows the format of interrupt request enable registers IRER.
Table 27. Interrupt Request Enable Registers IRER (Set = IRESR, Clear = IRECR)
Addresses—Set 0xE000 1008 , Clear 0xE000 100C
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
n* En Interrupt n enable. Indicates if interrupt n is enabled or disabled.
31:16 15:1 0
RSVD En
*
RSVD
If 1, interrupt n is enabled.
If 0, interrupt n is disabled.
0 RSVD Reserved.
* Replace n with any one of the following bits: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 , or 15.
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5 Programmable Interrupt Controller (PIC)
5.2.3 Interrupt Request Soft Register IRQSR
The interrupt request soft register IRQSR is used for programmed interrupt. A write to bit 0 (SOFT INTE RR UP T)
of this register sets or clears the programmed interrupt. Table 28 shows the format of interrupt request soft regis-
ters IRQSR.
Table 28. Interrupt Request Soft Register IRQSR
Address 0xE000 101 0
Bit #
Name
Bit # Name Description
31:1 RSVD Reserved.
0 SOFT INTERRUPT If 1, a soft interrupt is active.
5.2.4 Interrupt Priority Control Registers IPCR[15:1]
The interr upt priority cont rol regi st ers IPCR define the relative priority of each interrupt. The interrupt assigned
to IPCR[1 ] has the highest priority, and the interrupt assigned to IPCR[15] has the lowest priority. Only interrupts
that are assigned to IPCRs generate interrupts to the core. T ab le 29 shows the format of interrupt priority control
registers IPCR.
31:1 0
RSVD SOFT INTERRUPT
If 0, a soft interrupt is not active.
(continued)
Address 0xE000 1018 corresponds to IPCR1. Addresses follow in order thereafter.
These registers are set to 0 on reset.
Table 29. Interrupt Priority Control Registers IPCR[15:1]
Addresses—1 = 0xE000 1018, 15 = 0xE000 1050
Bit #
Name
Bit # Name Description
31:6 RSVD Reserved.
5 TYP Interrupt type. Indicates which interrupt signal lead on the core is driven when
4:0 IS Interrupt source. Assigns an interrupt to the interrupt priority control register.
31:6 5 4:0
RSVD TYP IS
this interrupt is active.
If 1, the interrupt will be mapped to FIQ.
If 0, the interrupt will be mapped to IRQ.
If 00000, there is no interrupt assigned to this priority level.
If 00001, IRQ1 is assigned to this priority level.
If 01111, IRQ15 is assigned to this priority level.
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5 Programmable Interrupt Controller (PIC)
(continued)
5.2.5 Interrupt In-Service Registers ISR (ISRI, ISRF) ISRI is the interrupt in-ser vic e register for IRQ type interrupts, and ISRF is the interrupt in-service register for
FIQ type interrupts. The interrupt in-service registers ISR contain the encoded value of the current highest prior-
ity interrupt. Writes to the ISR are ignored. If reading the ISR, the current value is frozen until the corresponding
interrupt is cleared in the IRSR (see Table 26 on page 51) if the freeze enable bit, FRZ, (bit 0 of IPER, see Table 33
on page 54) is set. Table 30 shows the for ma t of interrupt in-ser vic e registers ISR.
Table 30. Interrupt In-Service Registers ISR (ISRI, ISRF)
Addresses—ISRI 0xE000 1094, SRF 0xE000 1098
Bit #
Name
31:7 6:0
RSVD IIS
Bit # Name Description
31:7 RSVD Reserved.
6:0 IIS Interrupt s ource.
.
Table 31. Interrupt Source Encoding for Interrupt In-Service Registers
Bit 6:0 Interrupt Source
0000000 No Interrupt
0000100 IRQ1
0001000 IRQ2
0001100 IRQ3
0010000 IRQ4
0010100 IRQ5
0011000 IRQ6
0011100 IRQ7
0100000 IRQ8
0100100 IRQ9
0101000 IRQ10
0101100 IRQ11
0110000 IRQ12
0110100 IRQ13
0111000 IRQ14
0111100 IRQ15
5.2.6 Interrupt Request Source Clear Register IRQESCR
The interrupt reques t source clear register IRQESCR clears the serv ice interrup t pertaining to external interrupts. Write a 1 to the corresponding bit to clear the interrupt. Table 32 shows the format of interrupt request
source clear register IRQESCR.
Note: This register reverts back to 0 upon completion of the write.
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5 Programmable Interrupt Controller (PIC)
Table 32. Interrupt Request Source Clear Register IRQESCR
Addresses 0xE000 109C
Bit #
Name
Bit # Name Description
31:3 RSVD Reserved.
2 C2 Clear external interrupt 2. Writing a 1 to this bit clears interrupt 2.
1 C1 Clear external interrupt 1. Writing a 1 to this bit clears interrupt 1.
0 RSVD Reserved.
5.2.7 Interrupt Priority Enable Registers IPER (Set, Clear)
The interrupt prio rity enable registers IPER enable or disable an interrupt source based on its priority level, as
encoded in the interrupt priority control registers (see Table 29 on page 52). This simplifies the management of
nested interrupt service routines by disabling lower-priority interrupts while enabling higher-priority interrupts relative to the current interrupt.
The IPER has a dual mechanism for setting and clearing the enable bits. This sets or clears enable bits independently, with no knowledge of the other bits in the IPER.
To set the enable bits, a write is performed to the IPESR. Each data bit that is set to 1 enables the corresponding
interrupt prioprity level. To clear the enable bits, a write is perf ormed to the IPECR. Each data bit that is set to 1 dis-
ables the corresponding interrupt prioprity level. These registers are set to all ones on all reset conditions. Table 33
shows the format of the interrup t pr iority enable registers IPER.
31:3 2 1 0
RSVD C2 C1 RSVD
(continued)
Table 33. Interrupt Priority Enable Registers IPER (Set = IPESR, Clear = IPECR)
Addresses—Set 0xE000 10A0 Clear 0xE000 10A4
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
n* En Interr upt n enable. Indicates if interrupt at priority n is enabled or disabled.
0 FRZ Freeze the IRSR (see T able 26 on page 51).
* Replace n with any one of the following bits: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, or 15.
31:16 15:1 0
RSVD En FRZ
If 1, interrupt at priority n is enabled.
If 0, interrupt at priority n is disabled.
If 1, reading the IRSR causes the current value to be frozen until the corresponding interrupt is
cleared.
If 0, the IRSR value is not frozen and can change if a higher priority IRQ occurs.
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5 Programmable Interrupt Controller (PIC)
5.2.8 External Interrupt Control Registers
The external interrupt control registers configure the corresponding EXINT1 and EXINT2 pins (see Figure 2 on
page 27). ENA, SEN, POL, and ASY are writable and readable, however, DAT is read-only. Table 34 shows the for-
mat of the external interrupt control registers.
Table 34. External Interrupt Control Registers
Addresses 0xE000 10A8:0xE000 10AC
Bit #
Name
Bit # Name Description
31:5 RSVD Reserved.
4 DAT Interrupt data. A read-only copy of the data on the interrupt pin delayed by three cl ock cycles.
3 ASY Asynchronous interrupt. Determines if the pin can cause an interrupt asynchronously. This
2 POL Interrupt polarity. Determines the polarity of the external interrupt.
31:5 4 3 2 1 0
RSVD DA T ASY POL SEN ENA
functionality is only used in the CLKOFF powerdown mode.The external interrupts are
always synchronized when not in this mode.
If 1, the extern al interrupt is asynchrono us.
If 0, the extern al interrupt is synchronou s.
Reset value is 1.
(continued)
If 1, the extern al interrupt det ects a low-to-high transition or high level.
If 0, the extern al interrupt detects a high-to-low transition or low level.
Reset value is 0.
1 SEN Interr upt sense. Deter mi nes the sense of the interrupt.
If 1, the extern al interrupt is transition-detect.
If 0, the extern al interrupt is level-sensitive. Reset value is 0.
0 ENA Interrupt enable. Determines if the external interrupt is enabled and disables the programma-
ble I/O functionality on the pin if it is MUXed.
If 1, the extern al interrupt is enabled.
If 0, the extern al interrupt is disabled.
Reset value is 0.
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6 Programmable Direct Memo r y A ccess (DMA) Cont roller
The programmable direct memory access (DMA) controller provides four independent high-speed DMA channels.
A DMA channel is used to transfer data between two memory locations more efficiently than under program control
of the ARM core. Data is transferred in bytes, half-words, or words. Each DMA channel maintains a 32-bit source
and destination address. Some DMA controller features are as follows:
Four DMA channels.
■
32-bit source and destination address pointers.
■
Up to 64K [bytes/half-words/words] transferred at a time.
■
Interrupt generation on DMA transfer completion.
■
Four externa l DMA request input signals to regulate transfers.
■
Operates in three modes (explained below).
■
Circular buffer mode.
■
ASB (SYSTEM BUS)
ASB INTERFACE
TX_DRQ0 (ETHERNET)
TX_DRQ1 (IRDA)
TX_DRQ2 (UART)
TX_DRQ3 (SSI)
RX_DRQ0 (ETHERNET)
RX_DRQ1 (IRDA)
RX_DRQ2 (UART)
RX_DRQ3 (SSI)
5-9380 (F)
TO BRIDGE
BRIDGE
INTERFACE
APB (PERIPHERAL BUS)
DMA
CONTROL
LOGIC
APB INTERFACE
Figure 6. DMA Controller Block Diagram 1
6.1 DMA Ope r ati o n
Figure 6 above and Figure 7 on page 60 illustrate the functional blocks of the DMA controller. Each DMA channel
includes a 32-bit DMA source address register (see Table 37 on page 64), a 32-bit DMA destination address
register (see Table 39 on page 64), a 16-bit DMA transfer count register (see Table 41 on page 65), and a DM A
control register (see Table 36 on page 62). Each DMA channel operates in one of the modes listed in the next
Section.
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6 Programmabl e Di r ect Memory Access (D MA) Controller
(continued)
6.1.1 DMA Transfer Setup Procedure
All DMA transfers are set up by doing the following:
Program the source address through the DMA source address register (see Table 37 on page 64). This is the
■
beginning addre s s where the DMA c on troller will start the t rans fer.
Program the destination address through the DMA preload destination start address register (see Table 38
■
on page 64). This is the begin ning addre s s whe r e t h e source data will b e tr an sferre d.
Program the transfer count through the DMA preload transfer coun t register (s ee Table 40 on page 65).
■
Program the burst size and number of hold states in the DMA burst and hold count register (see Table 42 on
■
page 66). The DMA releases the bus to allow other masters access to it after each burst by the number of hold
states programmed in the DMA burst and hold count register.
Program the appropriate control codes into the DMA control register (see Table 36 on page 62). This includes
■
setting the following:
— Peripheral select (PS)—selects Ethernet, IrDA, UART, or SSI for modes 1 and 2.
— Circular buffer mode (CBM)—specifies buffer wrapping for mode 1.
— Channel mode (CMODE)—selects memory-to-memory (mode 0), peripheral-to-memory (mode 1), or mem-
ory-to-per ipheral (mode 2).
— Software DMA request enable (SDRQ_E)—enables software trigger used in modes 1 and 2.
— So ftware trigger DMA req ues t (SDRQ)—sof tware trigge r used in modes 1 and 2.
— Channel transfer size (CTS)—selects 8-bit, 16-bit, or 32-bit transfers.
— Channel increment source address (CIS)—selects auto source address increment during burst read.
— Channel increment destination source address (CID)—selects auto destination address incr eme nt dur ing
burst write.
— Channel star t (CS)—begin the transfer .
Chan n el Priority:
The DMA controller has the highest priority for accessing the system bus. When bursts are transferred, the DMA
channel gets uninterrupted access to the system bus. If hold states are specified, the DMA channel deasserts its
bus request signal for one or more cycles followi ng each write access to relinquish control of t he system bus to the
ARM.
DMA channels have a fixed priority, with channel 0 having the highest priority and channel 3 having the lowest priority.
Operational Comments:
To prepare for a DMA transf er, the required values are to be stored in the registers of one of the DMA channels, but
with the start bit (CS) of the DMA control register (see Table 36 on page 62) set to 0. The transfer begins when
the start bit is set to 1. If the transfer completes, the start bit is automatically set to 0. In memory-to-memory mode
(mode 0), the core is stalled for the duration of the transfer burst. The maximum burst size is 256 words.
For a DMA transfer to or from a FIFO, writing 0 to the start bit prematurely terminates the transfer. When the DMA
channel is active, the address and count registers are read but not written.
The source and destination addresses satisfy alignment restrictions. If a word is being transferred, address bits 1:0
of the address are 0; if a half-word is transferred, address bit 0 is zero. Failure to follow alignment restrictions
causes the transfer to be terminated and an exception fault recorded in the DMA status register (see T a ble 43 on
page 66).
The DMA controller transfers up to 64 k-1 [bytes/half-words/words] at a time. Byte transfer to or from internal RAM
is available to support data transfer to or from peripheral modules. Mixed size transfers are not supported.
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6 Programmabl e Di r ect Memory Access (D MA) Controller
(continued)
6.1.2 DMA Mode 0. Memory-to-Memory in Blocks of Burst Count Size
DMA mode 0 (memory-to-memory) is selected by setting CMODE[2:0] of the DMA control register (see Table 36
on page 62) to 000.
Memory-to-memory transfers are set up as specified in 6.1.1 DMA Transfer Setup Procedure.
Note: When SDRAM is one of the memory sources, the DMA transfer may be less efficient than ARM controlled
transfers utilizing cache because only one word is transferred at a time.
When the start bit (CS) in the DMA control r e gister (see Table 36 on page 62) is set to 1, the DM A tra ns fer will
■
start immediately in memory-to-memory mode as soon as the DMA ready signal is asserted.
The DMA will start to read, beginning at the address programmed in the DMA source address register (see
■
Table 37 on page 64). Transfers will be made to the address in the DMA destination address register (see
Table 39 on page 64), which is preset by writing to the DMA preload destination star t address register (see
Table 38 on page 64).
The number of items to be transferred is specified in t he DMA preload transfer count register (see Table 40 on
■
page 65).
The DMA releases the bus to allow other masters access to it after each programmed burst by the number of
■
hold states (also programmed). Burst count (BCNT[7:0]) and hold count (HCNT[7:0]) are programmed in the
DMA burst and hold count register (see Tab le 42 on page 66). Please note when using DMA to SSI,
BCNT[7:0] must b e set to 0.
Reads and writes in mode 0 (memory-t o-me mory) are performed with a data size programmed in the transfer
■
word size bits (CTS) in the DMA control register (see Table 36 on page 62). Available sizes are 8 bits, 16 bits,
or 32 bits.
Note: Care should be taken when setting up memory-to-memory (mode 0) transfers to allow for other, needed bus
traffic.
6.1.3 Mode 1. Peripheral-to-Memory in Blocks of Burst Count Size
DMA mode 1 (peripheral-to-memory ) is selected by setting CMODE[2:0] of the DMA control register (see Table
36 on page 62) to 001.
Peripheral-to-memory transfers are set up as specified in 6.1.1 DMA Transfer Setup Procedure.
In general, all transfers to/from peripherals should be 32-bit transfers. Valid data should be written into or read
■
from memory from the lower 8 bits, 16 bits or all 32 bits as controlled by the peripheral’s register or buffer size.
The suppor ted periph erals for DMA are Ethernet, SSI, IrDA, and UART. The ARM 2DSP and DSP2ARM buffers
may also be treated as peripherals while using the software triggered DMA mode (see Se ction 6.1.4.1 on page
60).
When the start bit (CS) in the DMA control r e gister (see Table 36 on page 62) is set to 1, the DM A tra ns fer will
■
start immed iately in peripheral-to-memory mode (mode 1) as soon as the DMA ready signal is asser ted. In the
mixed memory peripheral modes (modes 1 and 2), a software trigger (SDRQ) can be used to force the DMA to
see DMA ready.
Circular Buffer Mode (CBM):
Two transfer options are available in mode 1 and they are as follows:
The DMA will transfer until the transfer count, programmed through the DMA preload transfer count register
■
(see Table 40 on page 65), is reached.
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6 Programmabl e Di r ect Memory Access (D MA) Controller
Or, the DMA will transfer indefinitely in circular buffer mode until software resets the DMA start bit (CS) in the
■
(continued)
DMA control register (see Table 36 on page 62). In circular buffer mode, the transfer will continue as data
becomes available from the peripheral as indicated by the DMA ready signal from the peripheral. Circular buffer
mode is selected by setting the CBM bi t i n th e DMA control register (see Table 36 on page 62) to 1.
CBM Operation:
The buffer size is set by writing to the DMA preload transfer count register (see Table 40 on page 65).
■
The DMA will then transfer data to the memory as data becomes available from the peripheral until the transfer
■
count TCNT (see Table 41 on page 65) is reached.
The DMA destination address register (see Table 39 on page 64) and the DMA transfer count register (see
■
Table 41 on page 65) will then be rewritten with the preset values stored in their respective pre load registers.
The circular buffer reload counter (PCNTx) in the DMA status register (see Table 43 on page 66) will b e in c re -
■
mented whenever the transfer loops back to the preset values.
This DMA is gated by the DMA ready signal from the peripheral selected for the transfer. If the DMA ready signal
■
is deasserted before the number of words programmed into the DMA burst and hold count register (see Table
42 on page 66), the burst will halt and the DMA will relinquish the bus for the progr ammed number of hold states
before it will monitor the DMA ready signal again. When the DMA ready signal is reasserted the DMA will
request the bus, and will transfer up to burst count again when it receives its bus grant.
There is a software controlled DMA mode that does not use the DMA ready signal from the peripheral. This mode
is selected by setting the software trigger enable bit (SDRQ_E) in the DMA control register (see Table 36 on page
62). When the user is sure the number of words set up to be transferred is available in the peripheral's buffer, the
DMA is triggered by setting the software trigger DMA request bit (SDRQ) in the DMA control register (see Table
36 on page 62).The DMA ready signal is not monitored in this mode. If the DMA attempts to transfer more data
than can be buffered in the peripheral, data will be lost and questionable results will occur.
Notes: Data transfers to memory from the DSP2ARM/ARM2DSP buffer in the DCC block are much more efficient
in this mode, using the peripheral bus address of the DSP2ARM/ARM2DSP buffer, as opposed to using
the memory-to-me mory mode (mode 0) and the system bus address of the DSP2ARM/ARM2DSP buffer.
The memory wri te and buffer read can occur at the same time since they are on different busses in the
IPT_ARM, instead of the sequential read-then-write, that occur in the memory-to-memory mode.
6.1.4 Mode 2. Memory-to-Peripheral in Blocks of Burst Count Size
DMA mode 2 (memory-t o-per ipheral) is selected by setting CMODE[2:0] of the DMA control register (see Table
36 on page 62) to 010.
Memory-to-pe rip heral transfers are set up as specified in 6.1.1 DMA Transfer Setup Procedure.
In general, all transfers to/from peripherals should be 32-bit transfers and valid data should be written into or
■
read from memory from the lower 8 bits, 16 bits or all 32 bits as controlled by the peripheral’s register or buffer
size. The supported peripherals for DMA are Ethernet, SSI, IrDA, and UART. The ARM 2DSP and DSP2ARM
buffers may also be treated as peripherals while using the software triggered DMA mode (see Section 6.1.4.1 on
page 60).
When the start bit (CS) in the DMA control register (see Table 36 on page 62) is set to 1, the DMA transfer will
■
start imme diately in memory-to-peripheral mode (mode 2) as soon as the DMA ready signal is asser ted. In the
mixed memory periphe ral modes (modes 1 and 2), a software trigger (SDRQ) can be used to force the DMA to
see DMA ready. The DCC block does not supply a DMA ready signal to trigger the DMA transfers so the
software-triggered DMA mode must always be used for these transfers.
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6 Programmabl e Di r ect Memory Access (D MA) Controller
(continued)
There is a single transfer option availab le in mode 2 as follows:
The DMA will transfer until the transfer count, programmed through the DMA preload transfer count register
■
(see Table 40 on page 65), is reached.
Mode 2 does not support circular buffer mode.
■
6.1.4.1 Software-Triggered DMA Mode
There is a software triggered DMA mode that does not use the DMA ready signal from the peripheral. This mode is
selected by setting the software trigger enable bit (SDRQ_E) in the DMA control register (see Table 36 on page
62). When the user is sure the number of words set up to be transferred is availabl e in the peripheral's buffer , the
DMA is triggered by setting the software trigger DMA request bit (SDRQ) in the DMA control register. The DMA
ready signal is not monitored in this mode. If the DMA attempts to transfer more data then can be buffered in the
peripheral, data will be lost and questi onable resul ts will oc cur.
Notes: Data transfe rs to memory from t h e DSP2ARM/ARM 2DSP buffer in the DCC block are much more ef fi cient
in this mode, using the peripheral bus address of the DSP2ARM/ARM 2DSP buffer, as opposed to using
the memory-to-memory mode (mode 0) and the system bus address of the DSP2ARM/ARM 2DSP buffer.
The memory write and buffer read can occur at the same time since they are on different busses in the
IPT_ARM, instead of the sequential read-then-write, that occur in the memory-to-memory mode.
INTERRUPT
CONTROLLER
IRQ[10:8]
CONTROL
REGISTERS[5:0]
WORD COUNT
REGISTERS[3:0]
DESTINATION
ADDRESS
REGISTERS[3:0]
SOURCE
ADDRESS
REGISTERS[3:0]
CONTROL
LOGIC
ADDRESS
GENERATOR
DRC[3:0]
SSI
INTERFACE
ACC
INTERFACE
AMBA
SYSTEM BUS
INTERFACE
PERIPHERAL
BUS
INTERFACE
Figure 7. DMA Controller Block Diagram 2
5-8229(F)
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6 Programmabl e Di r ect Memory Access (D MA) Controller
(continued)
6.2 DMA Registers
Table 35. DMA Controller Register Map
Register Address
DMA control register for channel 0 (see Table 36 on page 62). 0xE000 2000
DMA control register for channel 1. 0xE000 2004
DMA control register for channel 2. 0xE000 2008
DMA control register for channel 3. 0xE000 200C
Reserved. 0xE000 2010:201C
DMA source address register for channel 0 (see Table 37 on page 64). 0xE000 2020
DMA source address register for channel 1. 0xE000 2024
DMA source address register for channel 2. 0xE000 2028
DMA source address register for channel 3. 0xE000 202C
Reserved. 0xE000 2030:203C
DMA preload destination start address register for channel 0 (see Table 38 on page 64). 0xE000 2040
DMA preload destination start address register for channel 1. 0xE000 2044
DMA preload destination start address register for channel 2. 0xE000 2048
DMA preload destination start address register for channel 3. 0xE 000 204C
Reserved. 0xE000 2050:205C
DMA destination address register for channel 0 (see Ta ble 39 on page 64). 0xE000 2060
DMA destination address register for channel 1. 0xE000 2064
DMA destination address register for channel 2. 0xE000 2068
DMA destination address register for channel 3. 0xE000 206C
Reserved. 0xE000 2070:207C
DMA preload transfer count register for channel 0 (see Table 40 on page 65). 0xE000 2080
DMA preload transfer count register for channel 1. 0xE000 2084
DMA preload transfer count register for channel 2. 0xE000 2088
DMA preload transfer count register for channel 3. 0xE000 208C
Reserved. 0xE000 2090:209C
DMA transfer count register for channel 0 (see Table 41 on page 65). 0xE000 20A0
DMA transfer count register for channel 1. 0xE000 20A4
DMA transfer count register for channel 2. 0xE000 20A8
DMA transfer count register for channel 3. 0xE000 20AC
Reserved. 0xE000
20B0:20BC
DMA burst and hold co unt registe r for chann el 0 (see Table 42 on page 66). 0xE000 20C0
DMA burst and hold count register for channel 1. 0xE000 20C4
DMA burst and hold count register for channel 2. 0xE000 20C8
DMA burst and hold count register for channel 3. 0xE000 20CC
Reserved. 0xE000
20D0:20FC
DMA status register (see Table 43 on page 66). 0xE000 2100
Reserved. 0xE000 2104
DMA interrupt reg ister (see Table 44 on page 68). 0xE000 2108
DMA interrupt enable register (see Table 45 on page 69). 0xE000 210C
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6 Programmabl e Di r ect Memory Access (D MA) Controller
6.2.1 DMA Control Registers for Channels [0:3] The DMA control registers programs different modes of DMA transfers. Table 36 shows the format of the DMA
control registers.
Table 36. DMA Control Registers for Channels [0:3]
Addresses, 0 (00xE000 2000), 1 (0xE000 2004), 2 (0xE000 2008), 3 (0xE000 200C)
Bit #
Name
Bit #
Name
Bit # Name Description
31:15 RSVD Res erved.
14:12 PS[2:0] DMA peripheral select. DMA peripheral select bit encoding.
31:15 14:12 11 10:8 7 6
RSVD PS[2:0] CBM CMODE[ 2:0 ] S DRQ_ E SDRQ
5:4 3 2 1 0 —
CTS[1:0] RSVD CIS CID CS —
000 Ethernet
001 IRDA
010 UART
011 SSI*
100:111 Reserved
These hardware ready selects are only valid when SDRQ_E = 0.
(continued)
Reset value = 000.
* Must have FAST_CLEAR set for DMA from SSI. Burst count should be set to 1 (pro-
grammed as 0) for DMA to SSI.
11 CBM Circular buffer mode. Used only for peripheral-to-memory transfer mode, (mode1). CBM is
ignored in other modes. A CH_DONEx interrupt will not be generated when CBM is active.
If set to 1 , CBM is enabled.
If set to 0 , CMB is disabled.
Note: CBM should not be used in conjunction with software trigger mode, since there is no
mechanism to ensure an endless supply of data. For example, once a peripheral's
FIFO is emptied, the data will be unknown.
Reset value = 0.
10:8 C MODE[2:0] Channel mode.
000 Memory-to-memory (mode 0)
001 Peripheral-to-memory (mode 1)
010 Memory-to-peripheral (mode 2)
011:111 Reserved
Reset value = 000
7 SDRQ_E Software DMA request enable. Setting this bit to 1 will select SDRQ as the DMA request
signal instead of the DRQ input from the peripheral. Valid only for peripheral-to-memor y
(mode 1) and memory-to-perip heral modes (mode 2).
Reset value = 0.
6 SDRQ Software trig ger DMA reques t. Setting thi s bit to 1 will trigger the DMA transfer in periph-
eral-to-memory (mode 1) and memory-to-peripheral modes (mode 2), when SDRQ_E = 1.
This bit is automatically cleared by hardware when the transfer is completed.
Reset value = 0.
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6 Programmabl e Di r ect Memory Access (D MA) Controller
Table 36. DM A Control Registers for Channels [0:3]
Bit # Name Description
5:4 CTS[1:0] Chann el transfer size.
00 Byte
01 Half word (16-bit)
10 Word (32-bit)
11 Reserved
Used only in memory-to-memory mode (mode 0). Peripheral-to-memory (mode 1) and
memory-to-peripheral mode (mode 2) transfers must always be 32-bit transfers. Mixed
size transfers are not supported.
Reset value = 00.
3 RSVD Reserved.
2 CIS Chann el increm ent source address.
If 1, autoincrement source address is active.
If 0, autoincrement source address is inactive.
Note: The SDRAM controller autoincrements during a burst read, therefore, setting
CIS = 0 has no effect in the memory-to-peripheral mode (mode 2) if the source
is the SDRAM. However, the SDRAM controller will require a new source
address at the start of the next burst, therefore, if the transfer is larger than the
burst, the CIS bit should be set to 1.
(continued)
(continued)
Reset value = 0.
1 CID Channel increment destination address.
If 1, autoincrement destination address is active.
If 0, autoincrement destination address is inactive.
Note: The SDRAM controller autoincrements during a burst write, therefore, setting
CID = 0 has no effect in the peripheral-to-memory mode (mode 1) if the destina-
tion is the SDRAM. However, the SDRAM controller will require a new destination address at the start of the next burst, therefore, if the transfer is larger than
the burst, the CID bit should be set to 1 especially if CBM = 1.
Reset value = 0.
0 CS Chann el start. In memory-to-mem ory mode (mode 0), DMA transfer starts as soon as
this bit is set to 1. For peripheral-to-memory (mode 1) and memory-to-peripheral mode
(mode 2) this bit must be set to 1 after the channel configuration is complete. The
transfer starts when the hardware or software DMA trigger goes high. Setting this bit to
0 in the middle of a transfer will kill the DMA transfer (i.e., the ARM breaks-in during a
channel hold sequence). This bit is automatically cleared by hardware when the trans-
fer is completed .
Reset value = 0.
6.2.2 DMA Source Address Registers for Channels [0:3]
The DMA source address registers are 32-bit registers that specify the starting source address. For all reset con-
ditions, the DMA source address registers are reset to 0. The DMA source address registers are written to
before starting a DMA operation and can be read at any time to determine the current address being written to by
the DMA.
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6 Programmabl e Di r ect Memory Access (D MA) Controller
The source address increments by the transfer word size after each transfer if the increment source address bit
(CIS) is set in th e DMA control register (see Table 36 on page 62). Table 37 shows the format of the DMA source
address registers.
Table 37. DMA Source Address Registers for Channels [0:3]
Addresses, 0 (0xE000 2020), 1 (0xE000 2024), 2 (0xE000 2028), 3 (0xE000 202C)
Bit #
Name
Bit # Name Description
31:0 SADR[31:0] Transfer source address. Written initially b y s oftw are, updated by hardware to show the
current source address.
This register in not initiali zed by ha rdware.
6.2.3 DMA Preload Destination Start Address Registers for Channels [0:3]
The DMA preload destination start address register is a 32-bit register that specifies the start ing destination
address. For all reset conditions, the DMA destination address register (Table 39) is set to 0. The DMA destina-
tion address register is a read-only register. It is updated with the value written in the DMA preload destination
start address register whenever the DMA preload destination start register (Table 38) is written, or in circular
buffer mode when the DMA transfer count register (see Table 41 on page 65) reaches 0. The DMA destination
address register is incremented by the transfer word size after every transfer if the increment destination address
bit (CID) is set in the DMA control register (see Table 36 on page 62). Th e DMA destination address register
(Table 39) can be read at any time to determine the current address location being written to. Table 38 shows the
format of the DMA preload destination start address register. Table 39 shows the forma t of the DMA destina-
tion address registers.
31:0
SADR[31:0]
(continued)
Table 38. DMA Preload Destination Start Address Registers for DMA Channels [0:3]
Addresses, 0 (0xE000 2040), 1 (0xE000 2044), 2 (0xE000 2048), 3 (0xE000 204C)
Bit #
Name
Bit # Name Description
31:0 PLD_DADR[31:0] Preload destination start address. A write to this register also writes through to the
DMA destination address register to initializes it. The contents of this register
are used to reload the DMA destination address register (DADR) on a circular
buffer wrap around.
This register is not initialized or updated by hardware.
Table 39. DMA Destination Address Registers for DMA Channels [0:3]
Addresses, 0 (0xE000 2060), 1 (0xE000 2064), 2 (0xE000 2068), 3 (0xE000 206C)
Bit #
Name
Bit # Name Description
31:0 DADR[31:0] Transfer destination address. Updated by hardware to show the current destination
address.
This register is not initialized by hardware.
31:0
PLD_DADR[31:0]
31:0
DADR[31:0]
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6 Programmabl e Di r ect Memory Access (D MA) Controller
6.2.4 DMA Preload Transfer Count Registers for Channels [0:3] The DMA transfer count register is a 16-bit register that decrements after each transfer . When the DMA transfer
count register reaches 0, the DMA transfer is halted unless it is in circular buffer mode. The DMA transfer count
register (Table 41) and the DMA destination address register (see Table 39 on page 64) are reset to the value in
their preset registers. The DMA transfer count register is a read-only register that is preset to the number of
[bytes/half-words/words] to be transferred by writing to the DMA preload transfer count register. For all reset
conditions, the DMA preload transfer count register is set to 0.
Table 40 shows the format of the DMA preload transfer count registers.
Table 40. DMA Preload Transfer Count Registers for Channels [0:3]
Addresses, 0 (0xE000 2080), 1 (0xE000 2084), 2 (0xE000 2088), 3 (0xE000 208C)
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15:0 PLD_TCNT[15:0] Preload value of the transfer count. A write to this register also writes through to
31:16 15:0
RSVD PLD_TCNT[15:0]
the DMA transfer count register (Tab le 41) and initializes it. In periphery-to-mem-
ory and circular buffer mode, these bits indicate the size of the circular buffer in
words.
(continued)
This register is not initialized or updated by hardware.
6.2.5 DMA Transfer Count Registers for Channels [0:3]
Table 41. DMA Transfer Count Registers for Channels [0:3]
Addresses, 0 (0xE000 20A0), 1 (0xE000 20A4), 2 (0xE000 20A8), 3 (0xE000 20AC)
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15:0 TCNT[15:0] Number of bytes/half-words/words remaining to be transferred. Updated by hardware
6.2.6 DMA Burst and Hold Count Registers
The DMA controller always attempts to send burst count (BCNT) number of transf ers and then backs off of the bus
for at least hold count (HCNT) number of clock cycles to allow bus activity from other bus masters to occur. The
DMA burst and hold count registers (see Table 42 on page 66) allow the programmer to specify how many trans-
fers should be performed in a burst, and how many wait-states should be allowed between bursts. Table 42 shows
the format of the DMA burst and hold count registers.
31:16 15:0
RSVD TCNT[15:0]
to show the transfer count remaining. If a start is issued and TCNT = 0x0000, a transfer
will not occur, however, a CH_DONEx will be generated in response to the start.
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Table 42. DMA Burst and Hold Count Registers for Channel [0:3]
Addresses—0 (0xE000 20C0), 1 (0xE000 20C4), 2 (0xE000 20C8), 3 (0xE000 20CC)
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15:8 HCNT[7:0] Number of hold states between bursts. The minimum hold count is 1, (i.e., HCNT= 0x00
7:0 BCNT[7:0] Burst count. Specifies the size of the bursts in which the DMA transfer will take place.
6.2.7 DMA Status Register
The DMA status register contains bits to indicate write or read faults on the DMA channels as well as the circular
buffer restart counters. Table 43 shows the forma t of the D MA status register.
31:16 15:8 7:0
RSVD HCNT[7:0] BCNT[7:0]
is the same as HCNT= 0x01). During this time, the active DMA channel drops its
request for the ASB bus while the other masters (USB, ARM, and the other DMA channels) arbitrate for control of the ASB.
Reset value = 0x00.
BCNT[7:0] actually encodes BCNT + 1 (1 to 256). The size of the transferred items is
specified by the CTS bits in the DMA control register (see Table 36 on page 62).
These per-channel register bits are not initialized by hardware. Please note: for SSI,
BCNT shou l d b e set to 0.
(continued)
Table 43. DMA Status Register
Address 0xE000 2100
Bit #
Name
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15 CRF3 Read fault on channel 3. Set by hardware when a read fault occurs during a DMA
14 CWF3 Write fault on channel 3. Set by hardware when a write fault occurs during a DMA
13:12 PCNT3[1:0] Circular buffer reload counter, channel 3. If channel 3 is in circular buffer mode, the
31:16 15 14 13:12 11 10 9:8
RSVD CRF3 CWF3 PCNT3[1:0] CRF2 CWF2 PCNT2[1:0]
7 6 5:4 3 2 1:0 —
CRF1 CWF1 PCNT1[1:0] CRF0 CWF0 PCNT 0[1 :0] —
transfer on channel 3.
Cleared by reset or writing a 1 to this bit.
transfer on channel 3.
Cleared by reset or writing a 1 to this bit.
hardware increments this by 1 each time the destination address is reloaded from the
corresponding DMA preload destination start address register (see Table 38 on
page 64).
Cleared by reset or writing a 1 to both bits.
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6 Programmabl e Di r ect Memory Access (D MA) Controller
Table 43. DMA Status Register (continued)
Bit # Name Description
11 CRF2 Read fault on channel 2. Set by hardware when a read fault occurs during a DMA
transmission on channel 2.
Cleared by reset or writing a 1 to this bit.
10 CWF2 Write fault on channel 2. Set by hardware when a write fault occurs during a DMA
transmission on channel 2.
Cleared by writing a 1 to this bit.
9:8 PCNT2[1:0] Circular buffer reload counter, channel 2. If channel 2 is in circular buffer mode, the
hardware increments this by 1 each time the destination address is reloaded from the
corresponding DMA preload destination start address register (see Table 38 on
page 64).
Cleared by reset or writing a 0x11 to these bits.
7 CRF1 Read fault on channel 1. Set by hardware when a read fault occurs during a DMA
transfer on channel 1.
Cleared by reset or writing a 1 to this bit.
6 CWF1 Write fault on channel 1. Set by hardware when a write fault occurs during a DMA
transfer on channel 1.
Cleared by reset or writing a 1 to this bit.
5:4 PCNT1[1:0] Circular buffer reload counter channel 1. If channel 1 is in circular buffer mode, the
hardware increments this by 1 each time the destination address is reloaded from the
corresponding DMA preload destination start address register (see Table 38 on
page 64).
(continued)
Cleared by reset or writing a 0x11 to these bits.
3 CRF0 Read fault on channel 0. Set by hardware when a read fault occurs during a DMA
transfer on channel 0.
Cleared by reset or writing a 1 to this bit.
2 CWF0 Write fault on channel 0. Set by hardware when a write fault occurs during a DMA
transfer on channel 0.
Cleared by reset or writing a 1 to this bit.
1:0 PCNT0[1:0] Circular buffer reload counter channel 0. If channel 0 is in circular buffer mode, the
hardware increments this by 1 each time the destination address is reloaded from the
corresponding DMA preload destination start address register (see Table 38 on
page 64).
Cleared by reset or writing a 0x11 to these bits.
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6.2.8 DMA Interrupt Register
The DMA interrup t register contains a 4-bit value that indicates the source of a DMA interrupt. For all reset conditions, the DMA interru pt reg ister is set to 0. Table 44 shows the format of the DMA interrupt register.
Table 44. DMA Interrupt Register
Address 0xE000 2108
Bit #
Name
Bit #
Name
Bit # Name Description
31:8 RSVD Rese rved.
7 CH_ERR3 D MA channel 3 error interrupt. Set to 1 by hardware on a read or write fault.
6 CH_DONE3 DMA channel 3 transfer interrupt complete. Set to 1 by hardware on transfer complete.
5 CH_ERR2 D MA channel 2 error interrupt. Set to 1 by hardware on a read or write fault.
4 CH_DONE2 DMA channel 2 transfer interrupt complete. Set to 1 by hardware on transfer complete.
31:8 7 6 5 4
RSVD CH_ERR3 CH_DONE3 CH_ERR2 CH_DONE2
3 2 1 0 —
CH_ERR1 CH_DONE1 CH_ERR0 CH_DONE0 —
Cleared by reset or writing 1 to this bit.
Cleared by reset or writing 1 to this bit.
Cleared by reset or writing 1 to this bit.
(continued)
Cleared by reset or writing 1 to this bit.
3 CH_ERR1 D MA channel 1 error interrupt. Set to 1 by hardware on a read or write fault.
Cleared by reset or writing 1 to this bit.
2 CH_DONE1 DMA channel 1 transfer interrupt complete. Set to 1 by hardware on transfer complete.
Cleared by reset or writing 1 to this bit.
1 CH_ERR0 D MA channel 0 error interrupt. Set to 1 by hardware on a read or write fault.
Cleared by reset or writing 1 to this bit.
0 CH_DONE0 DMA channel 0 transfer interrupt complete. Set to 1 by hardware on transfer complete.
Cleared by reset or writing 1 to this bit.
6.2.9 DMA Interrupt Enable Register
The DMA interrupt enable register contains an 8-bit value that enables the DMA interrupts from each channel.
For all reset conditions, the DMA interrupt enable register is set to 0. Table 45 shows the format of the DMA
interrupt enable register.
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6 Programmabl e Di r ect Memory Access (D MA) Controller
Table 45. DMA Interrupt Enable Register
Address 0xE000 210C
Bit #
Name
Bit #
Name
Bit # Name Description
31:8 RSVD R eserved.
7 CH_ERR3_E Ena ble DMA channel 3 interrupt.
6 CH_DONE3_E Ena ble DMA channel 3 transfer complete.
5 CH_ERR2_E Enable DMA channel 2 interrupt.
31:8 7 6 5 4
RSVD CH_ERR3_E CH_DONE3_E CH_E RR2_E CH_DONE2_E
3 2 1 0 —
CH_ERR1_E CH_DONE1_E CH_ERR0_E CH_DONE0_E —
If set to 1, interrupts are enabled.
If set to 0, interrupts are disabled.
Reset value = 0.
If set to 1, interrupts are enabled.
If set to 0, interrupts are disabled.
Reset value = 0.
If set to 1, interrupts are enabled.
If set to 0 interrupts are disabled.
(continued)
Reset value = 0.
4 CH_DONE2_E Ena ble DMA channel 2 transfer complete.
If set to 1, interrupts are enabled.
If set to 0, interrupts are disabled.
Reset value = 0.
3 CH_ERR1_E Enable DMA channel 1 interrupt.
If set to 1, interrupts are enabled.
If set to 0, interrupts are disabled.
Reset value = 0.
2 CH_DONE1_E Ena ble DMA channel 1 transfer complete.
If set to 1, interrupts are enabled.
If set to 0, interrupts are disabled.
Reset value = 0.
1 CH_ERR0_E Enable DMA channel 0 interrupt.
If set to 1, interrupts are enabled.
If set to 0, interrupts are disabled.
Reset value = 0.
0 CH_DONE0_E Ena ble DMA channel 0 transfer complete.
If set to 1, interrupts are enabled.
If set to 0, interrupts are disabled.
Reset value = 0.
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7 Programmable Timers
The programmable timers module supports two timer functions: interval timer (IT) and watchdog timer (WT). Features of the timer module are as follows:
Watchdog alarm interrupt
■
Watchdog alarm reset
■
Four interval timers
■
Generation of a shared interrupt request from the four interval timer channels
■
7.1 Tim ers Op er ation
All of the counters in the programmable timer module operate synchronous ly with the system clock. The count
rates are controlled by a clock prescaler that generates count enable signals at intervals of 2
n
of the system clock
rate. The interval timer and the watchdog timer functions independently select a count rate.
Figure 8 shows the programmable timer architecture.
PERIPHERAL CLOCK
WATCHDOG
TIMER
FUNCTION
INTERVAL
TIMER
FUNCTION
PERIPHERAL BUS
CONTROL/
STATUS/
MASK
WATCHDOG TIMER RESET
PERIPHERAL CLOCK
INTERRUPT REQUEST
32 kHz CLOCK
WIC
5-8227(F)
Figure 8. Programmable Timer Architecture Block Diagram
7.2 Inte rval T im er (I T)
The interval timer function supports four independent timers running off a common prescaler. Each timer consists
of a 16-bit, free-running counter , which increments at the selected count rate, and an IT maximum count register
(see Table 53 on page 77) that determines the interval.
The following text describes the general usage of the interval timers:
Set the count rate register (see Table 47 on page 74) to divide the system clock for the interval timers. The
■
count rate is selected by programming the interval timer count rate field (ITR) with an index between 0 and 11.
Set the IT maximum count register (see Table 53 on page 77) to set the timer interval. The IT count register
■
(see Table 53 on page 77) is loaded with the IT maximum count register va lue.
Enable timer by setting the ITEx bit in t h e tim er con trol register (see Table 52 on page 76). When the timer is
■
enabled, the IT count rate register begins decrementing.
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7 Programmable Timers
The IT count register will count down to 0. When it reaches 0, the timer status register (see T able 50 on page
■
(continued)
75) bit IxS (I3S:I0S) will be set and the IT count register is reloaded with the value in the IT maximum count
register.
If IxM (I3M:I0M) in the timer interrupt mask register (see Table 51 on page 76) is set to 1, the timer IRQ in the
■
interrupt request status register (see Table 26 on page 51) will be asserted (assuming it has been enabled in
the interrupt request enable register (see Table 27 on page 51).
Write 1 to the IxS bit in the timer status register (see Table 50 on page 75) to clear the interval timer status bit.
■
The interval timer function is illustrated in Figure 9 below . Only one of the four channels is shown. The IT count
registers are free-running counters that maintain the time-base of the inter val measurements.
IT MAXIMUM
COUNT REGISTER n
IT COUNT
PERIPHERAL BUS
REGISTER n
=0
CHANNEL n
INTERVAL TIMER COUNT RATE
INTERVAL TIMER CHANNEL n
TO STATUS R EGISTERS
IRQ
ENABLE
INTERNAL TIMER
CHANNEL n MASK
5-8228(F)a
Figure 9. Interval Timer Block Diagram
Comments:
The IT maximum count register (see Table 53 on page 77) may be read at any time.
■
Writing the IT maximum count register will cause the I T count register to reset to 0.
■
The period of the interval timers is determined by the count rate value and the value of COUNTVALUE in the IT
■
maximum count register. The status bit will be set every COUNTVALUE + 1 counts of the IT co unt register.
7.3 Watchdog Timer
The watchdog timer function asserts a time-out signal if the system software fails to restart the count sequence
within a specified time interval.
The watchdog timer block contains a 16-bit binary counter that increments at the selected count rate. The counter
is reset to the all-zeros value by writing a value of 0xFADE to the WT count re gister address (see Table 49 on
page 75). If the counter increments to the all-ones value, the watchdog timer time-out signal is asserted. The time-
out signal can be configured to generate a watchdog reset or to generate an interrupt. The count rate register for
the watchdog timer is configured to divide the 32 kHz RTC crystal or the system clock.
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(continued)
The following text describes the general usage of the watchdog timer:
Set the cou nt r at e r e gi ster (see Table 47 on page 74) to divide the clock input for the watchdog timer . The count
■
rate is selected by programming the watchdog timer count rate field (WTR) with an index of between 0 and 11.
Set the watchdog timer to run off of the system clock or the RTC crystal by setting the WIC bit in th e timer con-
■
trol register (see Ta ble 52 on page 76). This must be done before WTE is set.
Set the watchdog timer WTI bit in the timer cont rol regist er to generate an interrupt or a reset when the timer
■
expires.
Set the watchdog timer WTR bit in the timer con trol register for the desired reset mode.
■
Enable the timer by setting the WTE bit in th e ti m er cont rol register.
■
When the timer is enabled, the WT count register (see Table 49 on page 75) begins counting upwards. Writing
■
0xFADE to the WT count register will reset the timer and the count will start counting from 0 again.
When the WT count register value reaches 0xFFFF, the tim er status regis ter bit WTS (see Table 50 on page
■
75) bit will b e s e t.
If WTM is se t to 1 i n th e timer interrupt mask register, the timer IRQ in the interrupt request status register
■
(see Table 26 on page 51) will be asse rted (assumi ng it has been enabled in the interrupt req uest en able reg-
ister (see Tab le 27 on page 51).
Write a 1 to the WTS bit of the tim er st at us re g is t er (see Table 50 on page 75) t o cl ear the w atchdog timer inter-
■
rupt.
The watchdog timer function is illustrated below.
WT COUNT REGISTER
RESET
VALUE 0XFADE
PERIPHERAL BUS
ALL 1s
WATCHDOG TIMER COUNT RATE
WATCHDOG TIMER ENABLE
?
WATCHDOG TIMER TIMEOUT
?
Figure 10. Watchdog Timer Block Diagram
Comments
The WT count register (see Table 49 on page 75) can be read at any time, but cannot be written after the watch-
■
dog timer has been enabled.
A write access to the WT count register (see Table 49 on page 75) address with a data value 0xFADE causes
■
the WT count register (see Table 49 on page 75) to be set to the all-zeros value. Writing 0xFADE to the WT
count register will a ls o c le ar the WT status bit.
If the watchdog timer enable bit WTE (see Table 52 on page 76) is set to 1 and the WT count register incre-
■
ments to the all-ones value, the watchdog timer time-out signal is asserted. The effect of the watchdog time-out
is determined by the value of the watchdog timer interrupt bit WTI in the timer control register (see Table 52 on
page 76). If WTI is 1, a watchdog time-out will cause an interrupt. If another time-out occurs before the interrupt
is cleared in the timer status register, a watchdog reset w ill o c c ur. If WTI is 0, a time-out will always cause a
watchdog reset.
5-8226(F)
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7 Programmable Timers
Once the watchdog timer function is enabled in the timer control register, it cannot be disabled and the watch-
■
(continued)
dog timer count rate field (WTR) of the count rate register cannot be modified.
The WR bit in the reset status (control/clear) register (see Tabl e 13 on page 40) of the reset and power man-
■
agement function is set after the microcontroller restarts, if a watchdog timer reset occurred.
WTR of the timer control register (see Table 52 on page 76) is used to determine the effect of reset on the
■
watc hd og t ime r re gi st er s . If WTR is 1, the watchdog timer resets on powerup reset or watchdog reset but is not
affected by the external reset pin. If WTR is 0, the watchdog timer resets for all three reasons.
WIC of the timer control register selects the clock source for the watchdog timer. If 1, the clock source is the
■
32 kHz clock. If 0, the clock source is the system clock.
Note: The watchdog timer functionality should be completely set up before switching to the 32 kHz clock.
7.4 Timer Registers
The timer function (interval and watchdog) consists of the registers shown below. All timers depend on the control,
status, mask, and count rate registers.
.
Table 46. Timer Controller Register Map
Register Address
Reserved. 0xE000 5000—0x E000 5014
Count rate register (see Table 47 on page 74).
WT count register (16-bit counter) (see Table 49 on page 75).
Reserved. 0xE000 5020
Timer status register (see Table 50 on page 75).
Timer interrupt mask register (see Table 51 on page 76).
Timer control regist er (see Table 52 on page 76).
IT maximum count register 0 (16-bit counter).
IT count register 0 (16-bit counter).
IT maximum count register 1 (16-bit counter).
IT count register 1 (16-bit counter).
IT maximum count register 2 (16-bit counter).
IT count register 2 (16-bit counter).
IT maximum count register 3 (16-bit counter).
IT count register 3 (16-bit counter).
Reserved. 0xE000 5050—0xE000 507F
0xE000 5018
0xE000 501C
0xE000 5024
0xE000 5028
0xE000 502C
0xE000 5030
0xE000 5034
0xE000 5038
0xE000 503C
0xE000 5040
0xE000 5044
0xE000 5048
0xE000 504C
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7 Programmable Timers
7.4.1 Count Rate Register
The ITR and WTR bits in the count rate register are used to scale the input clock for the interval timers and the
watchdog timer. Table 47 shows the format of the count rate register . Use Table 48 below to encode the count
rate.
Table 47. Count Rate Register
Bit #
Name
Bit # Name Description
31:12 RSVD Reserved.
11:8 ITR Interval timer count rate; see Table 48 below.
7:4 WTR Watchdog timer count rate; see Table 48 below. WTR cannot be modified after the watchdog
3:0 RSVD Reserved.
7.4.2 Encoding of Interval Timer Count Rates (ITR) and Watchdog Timer Count Rates (WTR)
These values are used to encode the count rate for the watchdog and interval timers.
31:12 11:8 7:4 3:0
RSVD ITR WTR RSVD
timer has been enabled.
(continued)
Address 0xE000 5018
Table 48. Encoding of Interval Timer and Watchdog Timer Count Rates
Bit Field System Clock Divisor
0000 2
0001 4
0010 8
0011 16
0100 32
0101 64
0110 128
0111 256
1000 512
1001 1024
1010 2048
1011 4096
1100:1111 Reserved
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7 Programmable Timers
7.4.3 WT Timer Count Register The WT count register holds the current watchdog timer count value. Table 49 shows the format of the WT count
register.
Table 49. WT Count Register
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15:0 COUNTVALUE WT count register. This register uses a 16-bit counter format. The count rate is
7.4.4 Timer Status Register
The timer status register displays the interrupt status of both the watchdog timer and each of the 4 interval tim-
ers. Tabl e 50 shows the format of the timer status register.
(continued)
Address 0xE000 501C
31:16 15:0
RSVD COUNTVALUE
based on the programmed count rate value.
The value is res et by w rit in g 0xFADE to this registe r.
Table 50. Timer Status Register
Address 0xE000 5024
Bit #
Name
Bit # Name Description
31:12 RSVD Reserved.
11 WTS Watchdog timer interrupt status.
10:4 RSVD Res erved.
3:0 I3S:I0S Interval timer channel status.
7.4.5 Timer Interrupt Mask Register
The timer interrupt mask register enables and disables the status bits in the timer status register (Table 50)
from asserting the timer IRQ in the interrupt request status reg ister, assuming it has been enabled in the inter-
rupt request enable register. If IxM or WTM is set to 1, the IxS or WTS bit in the timer status register (Table 50)
will cause the shared IRQ (timer interrupt) in the interrupt request status register (see Table 26 on page 51) to
be asserted. Table 51 shows the format of the timer interrupt mask register.
31:12 11 10:4 3 2 1 0
RSVD WTS RSVD I3S I2S I1S I0S
If 1, the watchdog timer interrupt mode is enabled (WTI in the ti mer c ontrol
register) and the time-out signal is asserted. Write a 1 to this bit to clear it.
If 1, the IT count register for the channel has reached 0.
Writing a 1 to each of these bits clears the bit.
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Table 51. Timer Interrupt Mask Register
Bit #
Name
Bit # Name Description
31:12 RSVD Reserved.
11 WTM Watchdog tim er interrupt enable.
10:4 RSVD Reserved.
3:0 I3M:I0M Interval timer channel interrupt enable.
7.4.6 Timer Control Register
The timer control register affects the functionality of both the watchdog timer (WT) and the inter val timers (IT).
Table 52 shows the format of the timer control register.
31:12 11 10:4 3 2 1 0
RSVD WTM RSVD I3M I2M I1M I0M
If 1, the watchdog timer interrupt is enabled.
If 0, the watchdog timer interrupt is disabled.
If 1, the interrupt is enabled for the interval timer channel.
If 0, the interrupt is disabled for the interval timer channel.
(continued)
Address 0xE000 5028
Table 52. Timer Control Register
Address 0xE000 502C
Bit #
Name
Bit #
Name
Bit # Name Description
31:15 RSVD Reserved.
14:11 ITE3:ITE0 Interval timer channel enable.
10:9 RSVD Reserved. Must be written with 0s.
8 WTI Watchdog timer interrupt mode.
7:6 RSVD Reser ved. Must be written with 0s.
5 WI C Watchdog timer clock.
31:15 14 13 12 11 10:9
RSVD ITE3 ITE2 ITE1 ITE0 RSVD
8 7:6 5 4 3 2:0
WTI RSVD WIC WTR WRE RSVD
If 1, the channel is enabled.
If 0, the channel is disabled.
If 1, the watchdog timer generates an interrupt.
If 0, the watchdog timer generates a reset.
If 1, the timer runs off of the 32 KHz clock.
If 0, the timer runs off of the system clock.
This bit is reset to 1 on powerup reset but is not affected by other resets.
This bit can’t be changed once WTE is set.
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7 Programmable Timers
Table 52. Timer Control Register (continued)
Bit # Name Description
4 WTR Watchdog timer reset mode.
3 WTE Watchdog timer enable. Once enabled, the watchdog timer cannot be disabled.
2:0 RSVD Reserved. Must be wr itten with zeros.
7.4.7 IT Count Registers
The IT maximum count registers set the interval at which the timers will operate. The IT count re gisters contain
the current timer count value. The count value programmed in the IT maximum count register will be loaded into
the IT count register immediately after programming and again after the timer expires.
(continued)
If 1, the timer resets only on powerup or watchdog reset.
If 0, the timer resets on all sources of reset.
This bit resets to 0 on powerup but is not affected by other types of reset.
This bit can't be changed once WTE is set.
If 1, the timer is enabled to count and the system should write the value
(0xFADE) to the WT count register (see Table 49 on page 75) periodically to
reset its value to 0 and prevent the watchdog timer from reaching its maximum
count value.
If 0, the timer i s not enabled.
The bit description in Table 53 is the same for all eight registers listed below.
Table 53. IT Count Registers
Address 0xE000 5030:0xE000 504C
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15:0 COUNTVALUE Count value.
Register Address
IT maximum count register 0
IT count register 0
IT maximum count register 1
IT count register 1
IT maximum count register 2
IT count register 2
IT maximum count register 3
IT count register 3
Reserved 0xE000 5050
Reserved 0xE000 5054
31:16 15:0
RSVD COUNTVALUE
0xE000 5030
0xE000 5034
0xE000 5038
0xE000 503C
0xE000 5040
0xE000 5044
0xE000 5048
0xE000 504C
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8 External Memory Interface (EMI)
The IPT_ARM processor contains an external memory interface that is capable of addressing 16-bit-wide SDRAM,
and up to four SRAMs, FLASH memory, or I/O peripherals. Each memory range can be programmed for the
desired starting address (base addres s) and size (up to 64 Mbytes).
8.1 IPT_ ARM Processor Memory Map
Table 54. IPT_ARM Processor Memory Map
Range Description
0x0000 0000:0xBFFF FFFF Distributed over external ROM (FLASH), external SDRAM, general pur-
pose chip selects CS1, CS2, CS3, and internal 1K x 32 SRAM.
0xC000 0000:0xCFFF FFFF Reserved (for ARM 940T processor).
0xD000 0000:0xDFFF FFFF Reserved.
0xE000 0000:0xEFFF FFFF Peripheral address space.
0xF000 0000:0xFFFF FFFF Reserved.
8.2 External FLASH/SRAM Memory Interface (EMI FLASH)
The external FLASH/SRAM memory interface provides the following features:
Multiaccess timing and buffering to assemble a full 32-bit word (two 16-bit accesses or four 8-bit accesses) dur-
■
ing process or full-word reads.
Support for in-circuit reprogramming of external FLASH memory.
■
One FLASH chip select (FLASH_CS) for external program memor y.
■
Three general-purpose chip selects (CS 1, CS2, CS3) for external SRAM or I/O peripherals.
■
Configurable memory maps for FLASH_CS, CS1, CS2, CS3, in tern a l SR AM and SDRAM.
■
Optional setup cycle, wait-states, and hold-states fo r each de vi ce.
■
External WAIT pin (EXWAIT) for slow I/O peripherals.
■
Support s 8-bit and 16-bit devices on the external bus (FLASH memory must be 16-bit).
■
Support s ROM/RAM remappi ng to allow the RAM to be placed at address 0x00000000.
■
The EMI FLASH contains the logic and configuration information required to provide address and control generation for external FLASH memory and three other external memory areas. Each area is individually programmed for
setup, wait, and hold state generation.
8.3 EMI FLASH Memory Access
8.3.1 External Write
During the first cycle of the system clock, the A[23:0], BE1N, and WRN signals bec om e valid. If SET (bit 7) of the
corresponding chip select configuration register is 0, the appropriate chip select (FLASH_CS, CS1, CS2, CS3)
also goes active during this cycle. If an additional cycle of address/control setup with respect to the chip select is
desired, SET can be set to 1, and the chip select will go active during the second cycle of the system clock. The
write data (D[15:0]) goes active during the second cycle.
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8 External Memory Interface (EMI )
(continued)
8.3.2 External Read
During the first cycle of the system clock, the A[23:0] and BE1N signals become valid. If SET (bit 7) of the corresponding chip select configuration register is 0, the appropriate chip select (FLASH_CS, CS1, CS2, CS 3) and
RDN also go active during this cycle. If an additional cycle of address setup with respect to the chip select RDN is
desired, the SET bit can be set to 1, and the chip select and RDN will go active during the second cycle of the system clock.
8.3.3 Wait-States
During an external read or write, the number of active cycles durin g each access is deter m ined by the number of
wait- state s (WS[3:0]) and EXWAIT pin, if it is used.
A minimum of 2 wait-states must be programmed for external reads and writes to work properly.
WS = 0000 or WS = 0001 are not valid values.
Use of the EXWAIT pin (for slow devices) is enabled by setting the WT bit (bit 8) of the appropriate chip select
configur a tio n re gi st er. The polarity of the EXWAIT pin is programmed by the value of WP [bit 0] in the options
register (see Table 65 on page 89).
8.3.4 Hold State
If additional hold time is needed between the chip select going inactive and the start of the next access, one, two,
or three hold states may be added by setting HS (bits 5:4) of the corresponding chip select configuration regis-
ter to the appropriate value.
8.3.5 Hold Disable
For multiaccess read transactions to a device that requires hold states, it is only necessary to have hold states at
the end of the last access and not on each intermediate access. These intermediate hold states are suppressed by
setting HD (bit 10) of the appropriate chip select configuration register.
8.3.6 Error Conditions
The following errors are recorded in the status register (see T able 64 on page 88):
MAC register error. If an attempt is made to read/write the Ethernet MAC registers in the
■
0xE001 0800:0xE001 FFFF range when the PHY is not active (i.e., when the MAC is not receiving its Tx/Rx
clocks), a MAC register error occurs, and is recorded in MACRE (bit 15) of the status register.
Alignment error. If a nonaligned word access (with address bits 1:0 being nonzero) or a nonaligned half-word
■
access (with address bit 0 being nonzero) is attempted, an alignment error occurs and is recorded in AE (bit 13)
of the status register.
Peripheral subword access error. If a half-word or byte access attempt is made to the peripheral address space
■
(0xE000 0000:0xEFFF FFFF), a peripheral subword access error occurs, and is recorded in PSWE (bit 12) of
the status register.
Peripheral code access error. If an opcode fetch is attempted from peripheral address space
■
(0xE000 0000:0xEFFF FFFF), a peripheral code access error occurs and is recorded in the PCAE bit (bit 10) of
the status register.
DCC read error. If the ARM processor/DMA controller attempts to read from the ARM2DSP data buffer
■
(0xE004 0000:0xE004 07FF), a DCC read error occurs and is recorded in the DCCRE bit (bit 9) of the status
register.
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8 External Memory Interface (EMI )
DCC write error. If the ARM processor/DMA controller attempts to write to the DSP2ARM data buffer
■
(0xE006 0000:0xE006 07FF), a DCC write error occurs and is recorded in the DCCWE bit (bit 8) of the status
register.
In all of the abov e cases , the access is aborted. If the ARM processor was making the r equest, it j umps to t he error
vector in the vector table and begins executing code from there (refer to the ARM 940T documentation for information on how the ARM 940T handles errors). If the DMA controller was making the request, a read/write fault is
recorded in the DMA status register (see Table 43 on page 66).
(continued)
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8 External Memory Interface (EMI )
A[23:0]
t1
CS
RDN
D[15:0]
Figure 11. EMI FLASH/SRAM Read Interface Timing Diagram
A A + 2
t2
t6
D0 D1
(continued)
t3
t7
t4
t5
t8
Table 55. EMI FLASH/SRAM Read Access Timing Parameters
Symbol Timi ng Param e te rs Value (ns)
t1 Addres s Setup Time t o CS and RDN Active. SET ⋅ CLK (max)
t2
CS, RDN Active Time.
t3 Address Hold After CS Inactive, RDN Inactive (except last read
access in multicycle read).
t4 Addres s Hold A fter CS, RDN Inactiv e (l ast read access in multicycl e
WS ⋅ CLK
(HS + 1) ⋅ CLK ns, if HD = 0
CLK if HD = 1
(HS + 1) ⋅ CLK
read).
t5
CS, RDN In a ctive Time Betwe en Succe ssive Accesses.
(SET + HS+1) ⋅ CLK, if HD = 0
(SET + 1) ⋅ CLK, if HD = 1
t6 Read Data Setup Time Before CS and RDN Inactive. .5 ⋅ CLK + 1.3 ns (minimum)
t7 Read Data Hold Time After CS, RDN Inactive. 0 (minimum)
t8 Data 3-State After CS, RDN Inactive. 0 (minimum)
Notes:
CS refers to FLASH_CS/CS1/CS2/CS3.
HD = hold disable (HD) bit 1 in chip select configuration register.
HS = hold states (HS[1:0]) bits 5:4 in chip select configuration register, allowed values o f HS = 0, 1, 2, and 3.
SET = setup bit (SET) bit 7 in chip select configuration register, allowed values of SET = 0 and 1.
CLK = system clock period.
WS = wait-states (WS[3:0]) bits 3:0 in chip select configur ation regi st e r, allowed values of WS = 2, 3, 4—15.
Multiaccess read/write operations are:
32-bit reads/writes with a bus size of 16 bits/8 bits.
16-bit reads/writes with a bus size of 8 bits.
Single access read/write timing looks the same as the last access in a multicycle access.
All output parameters assume a 15 pF load.
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8 External Memory Interface (EMI )
t1
A[23:0]
CS
WRN
BE1N
t2
D[15:0]
A A + 2
t3
D0 D1
(continued)
t8
t4
t9
t7
Figure 12. EMI FLASH/SRAM Write Interface Timing Diagram
.
Table 56. EMI FLASH/SRAM Write Access Timing Parameters
t5
t6
Symbol Timing Para me ter Value (ns)
t1 Address, WRN, BE1N Setup Befor e CS Active. SET ⋅ CLK (maximum)
t2 A dd ress Valid to Write Data Valid. CL K + 1 ns (maximum)
t3
CS Active Time.
t4 Address Hold After CS Inactive (First Wr it e in Mu l tiple Acces s
WS ⋅ CLK
(HS
+ 1) ⋅
CLK + 1 ns (maximum)
Write).
t5 Address Hold After CS inactive (Single-Cycle Write Operation or
HS ⋅ CLK + 1 ns (maximum)
Last Access in a Multicycle Write).
t6
WRN, BE1N Inactive After CS Inactive.
HS ⋅ CLK + 1 ns (maximum)
t7 Data 3-State After CS Inactive. (HS + 2) ⋅ CLK + 2 ns (maximum)
t8
WRN High Between Successive Write Accesses (Multicycle Write).
t9
CS Inactive Between Successive Data Accesses.
CLK
(SET + HS + 1) ⋅ CLK
Address. 1.4 ns (maximum)
Data Skew. 1.0 ns (maximum)
Notes:
CS refers to FLASH_CS/CS1 /CS2 /CS3 .
HD = hold disable (HD) bit 1 in chip select configuration register.
HS = hold states (HS[1:0]) bits 5:4 in chip select configuration register . Allowed values of HS are 0, 1, 2, and 3.
SET = setup bit (SET) bit 7 in chip sel e ct configu rat i on reg i ster. Allowed values of SET are 0 and 1.
CLK = system clock period.
WS = wait-state s (WS[3:0]) bits 3:0 in chip select configuration reg ister. Allowed values of WS are 2, 3, 4, 5—15.
Multiaccess read/write operations ar e:
32-bit reads/writes with a bus size of 16 bits/8 bits.
16-bit reads/writes with a bus size of 8 bits.
Single access read/write timing looks the same as the last access in a multicycle access.
All output parameters assume a 15 pF load.
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8 External Memory Interface (EMI )
(continued)
8.4 ROM/RAM Remapping
An important design consideration is the layout of the memory map, and the memory present at address 0x0. Upon
reset, the ARM 940T starts to fetch instructions from address 0x0. This requires ROM to be present at location 0x0
upon reset. However , this has some disadvantages. ROM is slower than RAM, and this slows down the handling of
processor exceptions through the vector table. Also , if the vector tabl e is in ROM, it cannot be modified by the code.
For these reasons it is preferable to have RAM with the vector table and exception handlers at address 0x0.
For this purpose, the system decoder in the IPT_ARM suppor ts ROM/RAM remapping , using the value of the
REMAP bit (bit 12) of the chip select configuration register FLASH_CS (see Table 58 on page 84).
If REMAP = 0 FLASH_CS will go active at tw o possible base addresses, address 0x0, and the base address val ue
programmed in the chip select base address register FLASH_CS (see Table 62 on page 87). This allows an
aliased copy of ROM to be present at the chip select base address register FLASH_CS.
If REMAP = 1 FLASH_CS will go active only at the base address programmed in the chip select base address
register FLASH_CS register.
In both cases, the address range over which FLASH_CS goes active is determined by the block size (BSZ) (bits
3:0) of the chip select base address register FLASH_CS.
For an example of a remap system implementation, refer to the ARM Software Development Toolkit documenta-
tion.
ROMROM
ALIASED
RAM RAM
ROM
0x0 0x0
REMAP = 0 REMAP = 1
COPY OF
ROM
5-9387 (F)
Figure 13. ROM/RAM Remapping
8.4.1 Programmable Addresses
The memory address es for each chip select are programmable by setting a base address and a block size in the
corresponding chip select base address register (see Table 62 on page 87). On reset, the chip select base reg-
ister FLASH_CS is reset to a 2 Mbyte block starting at address 0x0. CS1, CS2, CS3, and the internal SRA M are
disabled.
The address space from 0x0000 0000:0xBFFF FFFF can be allocated over ROM (FLASH), external SDRAM, general-purpose chip selects FLASH_CS, CS1, CS2, CS3, and i nternal 1K x 32 SRAM in any way. Each chip select is
capable of addressing up to 64 Mbytes
Note: FLASH_CS is active-low..
Bits 3:0 (BSZ) of the chip select base address register select the block size of the memory covered by the chip
select. When the address is not in one of the ranges above, the value of the chip select base address register
bits 23:4 (ADDR[19:0]) is masked by the block size and then matched against bits 31:12 of the address of each
memory request. Since this is a match type operation, the base address for each chip select must be a multiple of
the block size.
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8 External Memory Interface (EMI )
(continued)
8.5 EMI FLASH Registers
The EMI FLASH has registers to configure the base address and other options for each of the chip selects
FLASH_CS, CS1, CS2, and CS3, the base address for the internal SRAM, a status register that records all system bus errors, and an options register common to all chip selects (FLASH_CS, CS1, CS2, and CS3).
Table 57. EMI FLASH Register Map
Register Address
Chip select configuration register FLASH_CS (see Table 58 on page 84).
Chip select configuration register CS1 (see Table 59 on page 85).
Chip select configuration register CS2 (see Table 59 on page 85).
Chip select configuration register CS3 (see Table 59 on page 85).
Reserved. 0xE000 3010:0xE000 301C
Chip select base address register FLASH_CS (see Table 62 on page 87).
Chip select base address register CS1 (see Table 62 on page 87).
Chip select base address register CS2 (see Table 62 on page 87).
Chip select base address register CS3 (see Table 62 on page 87).
Chip select internal SRAM base address register (see Table 62 on page 87).
Reserved. 0xE000 3034:0xE000 307C
Status register (see Table 64 on page 88).
Options register (see Table 65 on page 89).
0xE000 3000
0xE000 3004
0xE000 3008
0xE000 300C
0xE000 3020
0xE000 3024
0xE000 3028
0xE000 302C
0xE000 3030
0xE000 3040
0xE000 3044
8.5.1 Chip Select Configuration Register FLASH_CS
FLASH_CS is active-low.
Table 58. Chip Select Configuration Register FLASH_CS
Address 0xE000 3000
Bit #
Name
Bit # Name Description
31:14 RSVD Reserved.
13 UBE Use byte enables. Used for devices which are 16-bit devices and use byte enables. Byte
12 REMAP ROM/RAM remap. Remap ROM to the base address in chip select base address register
11 RSVD Reserved.
31:14 13 12 11 10 9 8 7 6 5:4 3:0
RSVD UB E REMAP RSVD HD RSVD WT SET RSVD HS WS
writes to these devices a r e ille gal if this bit is no t se t .
If 1, byte enables are used by the device.
If 0, no byte enables are used by the device.
(FLASH_CS).
If REMAP = 1, FLASH_CS goes active only at the base address in the chip select base
register FLASH_CS (see Table 62 on page 87).
If REMAP = 0, FLASH_CS goes active at address 0x0 as well as at the base address in the
chip select base register FLASH_CS.
Reset value = 0.
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8 External Memory Interface (EMI )
Table 58. Chip Select Configuration Register FLASH_CS (continued)
Bit # Name Description
10 HD Hold disable. Disables the hold states between accesses in a multicycle read transaction.
If 1, hold states are suppressed between the access.
If 0, each access is followed by the specified number of hold states.
Note: The hold states at the end of the transaction are not suppressed by this bit.
Reset value = 0.
9 RSVD Reser ved.
8 WT Enable or disable EXWAIT pin.
If 1, EXWAIT is enabled.
If 0, EXWAIT is disabled.
Reset value = 0.
7 SET Setup cycle. Adds an extra cycle of setup time to the address and control signals with
respect to the chip select.
If 1, the extra setup cycle is added.
If 0, the extra setup cycles is not added.
Reset value = 0.
6 RSVD Reser ved.
5:4 HS Hold states. The number of hold states inserted after each read or write access (see Table
60 on page 87).
(continued)
Reset value = 00.
3:0 WS Wait-states. The number of wait-states inserted during each read or write access (see Table
61 on page 87).
Reset value = 1111.
8.5.2 Chip Select Configuration Registers CS1, CS2, CS3
Table 59. Chip Select Configuration Registers CS1, CS2, CS3
Addresses—CS1 (0xE000 3004), CS2 (0xE000 3008), CS3 (0xE000 300C)
Bit #
Name
Bit # Name Description
31:14 RSVD Reserved.
13 UBE Use byte enables. Used for devices which are 16-bit devices and use byte enables. Byte
12 ENA Enable chip select.
31:14 13 12 11 10 9 8 7 6 5:4 3:0
RSVD UBE ENA RSVD HD RSVD WT SET BS HS WS
writes to these devices are illegal if this bit is not set.
If 1, byte enables are used by the device.
If 0, no byte enables are used by the device.
If 1, the chip select is enabled.
If 0, the chip select is disabled.
Reset value = 0.
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8 External Memory Interface (EMI )
Table 59. Chip Select Configuration Registers, (CS1, CS2, CS3) (continued)
Bit # Name Description
11 CS POL CS polar ity.
0 = active-low.
1 = active-high.
10 HD Hold disable. Disables the hold states between accesses in a multicycle read transaction.
If 1, hold states are suppressed between the access.
If 0, each access is followed by the specified number of hold states.
Note: The hold states at the end of the transaction are not suppressed by this bit.
Reset value = 0.
9 RSVD Reserved.
8 WT Enable or disable EXWAIT pin.
If 1, EXWAIT is enabled.
If 0, EXWAIT is disabled.
Reset value = 0.
7 SET Setup cycle. Adds an extra cycle of setup time to the address and control signals with
respect to the chip selec t.
If 1, the extra setup cycle is added.
If 0, the extra setup cycles is not added.
(continued)
Reset value = 0.
6 BS B u s size. The data bus size of the device.
If 1, the device supports 16-bit transfers and all 16 bits of the data bus are connected to it.
If 0, the device supports 8-bit transfers and bits 7:0 of the data bus are connected to it.
Reset value = 0.
5:4 HS Hold states. The number of hold states inserted after each read or write access (see Table
60 on page 87).
Reset value = 00.
3:0 WS W ait-s tate. The number of wait-states inserted during each read or write access (see T ab le
61 on page 87).
Reset value = 1111.
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8 External Memory Interface (EMI )
8.5.3 Hold and Wait-States Encoding
Table 60. Hold States Encoding
HS[1:0] Number of Hold States
00 0
01 1
10 2
11 3
Table 61. Wait-States Encoding
WS[3:0] Number of Wait-States WT Bit = 0 Number of Wait -States WT Bit = 1
0000 Illegal Illegal
0001 Illegal Illegal
0010 2 3 + EX WAIT pin
0011 3 3 + EX WAIT pin
0100 4 4 + EX WAIT pin
0101 5 5 + EX WAIT pin
0110 6 6 + EX WAIT pin
0111 7 7 + EX WAIT pin
1000 8 8 + EX WAIT pin
1001 9 9 + EX WAIT pin
1010 10 10 + EXWAIT pin
1011 11 11 + EXWAIT pin
1100 12 12 + EXWAIT pin
1101 13 13 + EXWAIT pin
1110 14 14 + EXWAIT pin
1111 15 15 + EXWAIT pin
(continued)
8.5.4 Chip Select Base Address Registers FLASH_CS, CS1, CS2, CS3, Internal SRAM
Table 62. Chip Select Base Address Registers FLASH_CS, CS1, CS2, CS3, Internal SRAM
Addresses—FLASH_CS (0xE000 3020), CS1(0xE000 3024), CS2 (0xE000 3028), CS3 (0xE000 302C),
Internal SRAM (0xE000 3030)
Bit #
Name
Bit # Name Description
31:24 RS VD Reserved.
23:4[19:0] ADDR
3:0[3:0] BSZ[3:0]
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31:24 23:4 3:0
RSVD ADDR[19:0] BSZ[3:0]
Base address. Bits 31:12 of the base address for the chip select. The 32-bit base address
must be a multiple of the block size. (Bits 11:0 are always assumed to be 0.)
Reset value = 0x00000.
Block size. Determines the size of the block at the given memory address for the chip
select. This size, in turn , determines which bits of the base address will be compared
against the address of the request. Table 63 shows the encoding of the block size field.
Reset values are as follows:
For FLASH_CS = 1010.
For CS1, CS2, CS2, and internal SRAM = 0000.
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Advanced RISC Machine (ARM ) July 2001
8 External Memory Interface (EMI )
8.5.5 Block Size Field Encoding
Table 63. Block Size Field Encoding
Value Block Size (Bytes) Address Bits to Match Value Block Size (Bytes) Address Bits to Match
0000 — Di sa bled 1000 512 K 31:19
0001 4 K 31:12 1001 1 M 31:20
0010 8 K 31:13 1010 2 M 31:21
0011 16 K 31:14 1011 4 M 31:22
0100 32 K 31:15 1100 8 M 31:23
0101 64 K 31:16 1101 16 M 31:24
0110 128 K 31:17 1110 32 M 31:25
0111 256 K 31:18 1111 64 M 31:26
8.5.6 Status Register
Table 64. Status Register
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15 MACRE
14 RSVD Reserved.
13 AE
12 PSWE
11 RSVD Reserved.
10 PCAE
9 DCCRE
31:16 15 14 13 12 11 10 9 8 7:0
RSVD MACRE RSVD AE PSWE RSVD PCAE DCCRE DCCWE RSVD
MAC register error. This bit is set to 1 if an attempt is made to read/write the Ethernet MAC
registers in the 0xE001 0800:0xE001 FFFF range when the PHY is not active (i.e., when
the MAC is not rec eiv in g its Tx/Rx cl ocks).
Cleared by writing a 1 to this bit.
Alignment error. This bit gets set to 1 if a nonaligned word access (with address bits 1:0
being nonzero) or a nonaligned half-word access (with address bit 0 being nonzero) is
attempted.
Cleared by writing a 1 to this bit.
Peripheral subword access error. If a half-word or byte access attempt is made to the
peripheral address space (0xE000 0000:0xEFFF FF FF).
Cleared by writing a 1 to this bit.
Peripheral code access error. This bit gets set to 1 if an opcode fetch is attempted from
peripheral address space (0xE000 0000:0xEFFF FF FF).
Cleared by writing a 1 to this bit.
DCC read error . This bit gets set to 1 if the ARM processor/DMA controller attempts to read
from th e ARM2DSP data buffer (0xE004 0000 :0xE004 07F F).
Cleared by writing a 1.
(continued)
Address 0xE000 3040
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8 External Memory Interface (EMI )
Table 64. Stat us Register (continued)
Bit # Name Description
8 DCCWE DCC write error. This bit gets set to 1 if the ARM processor/DMA controller attempts to write
to the DSP2ARM data buffer (0xE006 0000:0xE006 07FF).
Cleared by writing a 1.
7:0 RSVD Reserved.
8.5.7 Options Register
Table 65. Options Register
Bit #
Name
Bit # Name Description
31:1 RSVD Reser ved.
0 WP EXWAIT polarity.
If 1, EXWAIT is active- hig h.
If 0, EXWAIT is active-low.
31:1 0
RSVD WP
(continued)
Address 0xE000 3044
Reset value = 0.
8.6 External SDRAM Memory Interf ace
SDRAM register features are as follows:
Programmable address shifting to support a variety of SDRAM sizes.
■
Block or fast-page mode SDRAM acces ses.
■
One external SDRAM memory range.
■
8.6.1 External SDRAM Memory Map
Table 66. External SDRAM Memory Map
Register Address
SDRAM memory range base address register (see Table 67 on page 90).
SDRAM control register (see Table 68 on page 90).
SDRAM timi ng and configuratio n regi s te r (see Table 69 on page 90).
SDRAM manual register (see Table 70 on page 91).
0xE000 B000
0xE000 B004
0xE000 B008
0xE000 B00C
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8 External Memory Interface (EMI )
(continued)
8.6.2 SDRAM Memory Range Base Address Register
Table 67. SDRAM Memory Range Base Address Register
Address 0xE000 B000
Bit #
Name
31:24 23:4 3: 0
RSVD ADDR BSZ
Bit # Name Description
31:24 RSVD Reserved.
23:4 ADDR Base address. Bits 31:12 of the base address for the chip select. The 32-bit base address
must be a multiple of the block size.
3:0 BSZ Block size (see Table 63 on page 88).
8.6.3 SDRAM Control Register
Table 68. SDRAM Control Register
Address 0xE000 B004
Bit #
Name
31:2 1 0
RSVD SDRE GMA
Bit # Name Description
31:2 RSVD Reser ved.
1 SDRE SDRAM enable. If 1, the SDRAM auto process is enabled.
0 GMA Generate manual access. When 1 and SDRE = 0, the SDRAM’s bus will be put in manual
access state as defined in SDRAM manual access register for one cycle (see Table 70
on page 91). This special mode is used to do the start-up sequence for SDRAM in soft-
ware.
8.6.4 SDRAM Timing and Configuration Register
The external SDRAM memory interface signal should be configured in the SDRAM timing and configuration register (0xE000 B008) for proper operation as follows:
RAS to CAS delay—set to 1.
■
CAS to precharge—set to 3.
■
Precharge to RAS—fixed at 4.
■
Table 69. SDRAM Timing and Configuration Register
Address 0xE000 B008
Bit #
Name
31:26 25: 16 15:9 8:7 6:5 4:3 2 1:0
RSVD RFC RSVD CRCD RSVD CCPD CL CAB
Bit # Name Description
31:26 RSVD Reserved.
25:16 RFC Refresh count.
15:9 RSVD Reserved.
8:7 CRCD Clocks RAS to CAS delay. 01—1, 10—2, 11—3, 00—4.
6:5 RSVD Reserved.
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July 2001 Advanced RISC Machine (ARM )
8 External Memory Interface (EMI )
Table 69. SDRAM Timing and Configuration Register (continued)
Bit # Name Description
4:3 CCPD Clocks CAS to precharge delay. 11—3, 00—4.
Note: Values 01 and 10 are not supported.
2 CL CAS latency.
0 = 2 clocks.
1 = 3 clocks.
1:0 CAB Column address bits: 00—8 column address bits, 0—9 column address bits, 1x—reserved.
8.6.5 SDRAM Manual Access Register
Table 70. SDRAM Manual Access Register
Bit #
Name
Bit # Name Description
31:19 RSVD Reserved.
18 RAS SDRAM RAS value for manual access.
17 CAS SDRAM CAS value for manual access.
16 WE SDRAM WE value for ma nual acces s.
15 RSVD Reserved.
14:0 ADDR SDRAM address bus value for manual access.
31:19 18 17 16 15 14:0
RSVD RAS CAS WE RSVD ADDR
(continued)
Address 0xE000 B00C
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Advanced RISC Machine (ARM ) July 2001
8 External Memory Interface (EMI )
8.7 SDR AM T im in g
012345678910
SDRCK
t1
t2
SDRASN
t4
SDCASN
SDWEN
A[13:12]
BANK SELECT
A[10] AUTO
PRECHARGE
t5
BA
t6
RAx
t7
(continued)
t3
t8
BANK SELECT
CAx
t9
t10
t11
A[11:0]
SDLDQM/
SDUDQM
D[15:0]
RAx
CAx
t14
t13
t15
Ax0 Ax1 Ax2 Ax3
t12
Reference Parameter Minimum Maximum
t1 SDRCK High Time. — —
t2 SDRCK Low Time. — —
t3 SDRCK Cycle Time. — —
t4 SDRASN Output Delay. — 7.25 ns
t5 SDRASN Output Hold Time. 6.98 ns —
t6 Address/ P recha rge Out put Ho l d Time. 7.28 ns —
t7 Address/Precharge Maximum Output Delay Time. — 7 .44 ns
t8 SDCASN Maximum Output Delay. — 7.27 ns
t9 SDCASN Output Hold Time. 7.14 ns —
t10 SDWEN Maximum Output Delay. — 7.31 ns
t11 SDWEN Output Hold Time. 7.11 ns —
t12 Minimum Data Setup Time. 0 ns —
t13 Minimum Data Hold Time. 1.90 ns —
t14 Data I/O Mask Output Delay. — 7.89 ns
t15 Minimum Data I/O Mask Output Hold Time. — 7.09 ns
Figure 14. SDRAM Read Timing Diagram
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Data Sheet T8302 Internet Protocol Telephone
July 2001 Advanced RISC Machine (ARM )
8 External Memory Interface (EMI )
012345678910
SDRCK
t1
t5
t10
t6
SDRASN
SDCASN
SDWEN
A[13:12]
BANK SELECT
A[10]
AUTO
PRECHARGE
A[11:0]
SDLDQM/
SDUDQM
D[15:0]
t2
t4
BA
BA
t7
BA
(continued)
t3
t8
BANK SELECT
t12
t13
Ax0
Ax1
t9
t11
CAx
CAx
t14
t15
Ax2 Ax3
Reference Parameter Minimum Maximum
t1 SDRCK High Ti me. — —
t2 SDRCK L o w Time. — —
t3 SDRC K C ycle Ti mes. — —
t4 SDRASN Output Delay. — 7.25 ns
t5 SDRASN Output Hold Time. 6.98 ns —
t6 Address/Precharge Output Hold Time. 7.28 ns —
t7 Address/Precharge Maximum Output Delay Time. — 7.44 ns
t8 SDCASN Maximum Ou tput Delay. — 7.27 ns
t9 SDCASN Output Hold Time. 7.14 ns —
t10 SDWEN Maximum Output Delay. — 7.31 ns
t11 SDWEN Output Hold Time. 7 .11 ns —
t12 Maximum Data Output Valid. 0 ns —
t13 Minimum Data Hold Time. 1.90 ns —
t14 Data I/O Mask Output Delay . — 7.89 ns
t15 Minimum Data I/O Mask Output Hold Time. — 7.09 ns
Figure 15. SDRAM Write Timing Diagram
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Advanced RISC Machine (ARM ) July 2001
8 External Memory Interface (EMI )
(continued)
8.8 Signa ls
The EMI controls all the signals needed to access external devices. For transactions that are larger than the width
of the device, the EMI creates multiple accesses to read from or write to the device. For e xample, a 32-bit read from
an 8-bit device requires four read accesses. SDRAM, FLASH, and SRAMs share the same address and data bus.
8.8.1 Address, A[23:0]
For FLASH_CS, CS1, CS2, and CS3 devices , the address bus signals A[23:0] define the address of the least significant byte transferred during a memor y cycle. The address becomes valid during phase 1 of the first cycle of an
access and remains valid until phase 1 of first cycle of the next access.
Note: For F LASH and SRAM accesses, A[23:0] is used to access memory in units of bytes. If a 16-bit wide SRAM/
FLASH memory device is used, A[1] should be connected to the least significant address input pin of the
memory device. For 8-bit wide FLAS H/SRAM devices, A[0] should be connected to the least significant
address input.
8.8.2 Data, D[15:0]
Data bus si gnal s D[15:0] are bidirectional signals that transfer data to and from the chip. Use of the upper 8 bits of
the data bus is controlled on a per-device basis by BS (bit 6) of the chip select configuration register.
Note: The program memory that is accessed by FLASH_CS always uses a 16-bit data bus. During a read access,
the data on the data bus is latched at the end of phase 1 of the last active cycle of the access. For a write
access, the data becomes valid during phase 1 of the second cycle of the access. If there is no valid transaction on the EMI, the data bus stays in input mode.
8.8.3 Byte Enable, BE1N BE1N is used as a byte write enable for 16-bit devices that use byte enables. This signal is active-low and goes
active when an odd byte is to be written. The UBE bit (bit 13) of the chip select configuration register must be
set to 1 before attempting byte writes to 16-bit devices.
8.8.4 Read/Write Signals, RDN, WRN RDN and WRN are active-low signals that indicate whether a read or a write access is taking place. During a read
access, RDN goes low and WRN stays high. During a write access, RDN stays high am WRN goes low. If the EMI
flash is not being accessed, RDN and WRN stay high.
8.8.5 Chip Selects, FLASH_CS, CS1, CS2, CS3
The chip select signal s FLASH_CS, CS1, CS2, and CS3 indicate which of the external devices is accessed. The
appropriate chip select becomes active during phase 1 of the first cycle of an access if no setup cycle is used and
goes inactive after the last active cycle of the access. FLASH_CS is acti v e -l o w. CS1, CS2, and CS3 hav e program-
mable polarities and are active-low at reset.
8.8.6 External WAIT, EXWAIT
This signal can be driven by the external device to add additional wait-states to the memory access cycle, if
required. The use of the EXWAIT signal by a particular device is enabled by setting the WT bit (bit 8) of the appro-
priate chip select configuration register. The polarity of EXWAIT is programmable , and is determined by the WP
bit (bit 0) of the options register; see Tab l e 65 on page 89.
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8 External Memory Interface (EMI )
8.8.7 EMI SDRAM, Synchronous DRAM Memory Interface
The EMI SDRAM interface can support one 16-bit wide synchronous DRAM device. SDRAM devices of other
widths (8-bit/4-bit) are not supported. Device sizes up to 256 Mbits are supported. The SDRAM's chip select
should be tied off to active.
8.8.8 SDRAM Address Functionality Pins A[14:0] are used to output the row/column/bank address of the SDRAM location being accessed. Pins
A[23:15] are not used during an SDRAM access. The output on these pins depends upon the type of SDRAM
access cycle, e.g., when used with a 64 Mbit 16-bit wide SDRAM device.
Table 71. SDRAM Access Cycles, Using a 64 Mbit SDRAM
SDRAM Command Cycle Address Pins
Row address strobe (RAS)
Column address strobe (CAS)
Precharge
A[13: 0] = row address, where A[13:12] = bank select.
A[7:0] = column address.
A[10] = precharge mode.
If A[10] = 1, all banks are precharged.
If A[10] = 0, only the bank selected by the bank select signals on the
SDRAM are precharged.
(continued)
8.8.9 SDRAM Clock, SDRCK
This is the clock output that should be connected to the SDRAM. This runs at the same frequency as the IPT_ARM
system cloc k.
8.8.10 SDRASN, SDCASN, SDWEN
SDRAM row address strobe (SDRASN), column address strobe (SDCASN ), and write enable (SDWEN) are s tan-
dard SDRAM interface signals. The combination of these three outputs is used to indicate the type of command
that is to be performed on SDRAM.
8.8.11 SDUDQM, SDLDQM SDUDQM and SDLDQM are SDRAM upper byte enable and lower data byte enable, respectively. In read mode
SDUDQM/SDLDQM go low to turn on the SDRAM's output buffers. In write mode, SDUDQM/SDLDQM go low to
allow the corresponding byte to be written.
Note: Care should be taken to have the shortest possible routes on the board, and to avoid excessive loading
(>15 pF) for all the EMI pins.
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Advanced RISC Machine (ARM ) July 2001
9 DSP Commu ni cations Contr o lle r (DCC)
The DSP communications controller consists of the following elements:
ARM (write only) DSP (read-only) 512 x 32 bit internal SRAM for use as a communications mailbox.
■
ARM (read-only) DSP (write only) 512 x 32 bit internal SRAM for use as a communications mailbox.
■
Token register to support single owner of memory segments or message headers.
■
ARM 2DSP interrupt register.
■
DSP2ARM interrupt register.
■
Dedicated I/O pins for single wait-state DSP accesses.
■
DSP communications controller address map.
■
IPT_ARM peripheral controller circuits.
■
DSP_A[10:0]
DSP_D[15:0]
DSP_RWN
DSP_MCSN
DSP_ICSN
IPT_DSP
INTERFACE
ARM2DSP
BUFFER
(512x32)
DSP2ARM
BUFFER
(512x32)
INTERRUPT
AND
TOKEN
REGISTERS
APB
INTERFACE
TO INTERRUPT CONTROLLER
(PERIPHERAL BUS)
IRQ_DCC
APB
5-9379 (F)
Figure 16. DSP Communications Controller Block Diagram
9.1 ARM Processor Memory and I/O Map
Table 72. ARM Processor Memory and I/O Map
Register Address
Token regi s te r (see Table 73 on page 97). 0xE000 F0 00
Reserved. 0xE000 F004:0x E000 F01C
DSP2ARM interrupt register (see Table 74 on page 98). 0xE000 F020
Reserved. 0xE000 F024:0x E000 F02C
ARM 2DSP interrupt register (s ee Table 75 on page 98). 0xE000 F030
Reserved. 0xE000 F034:0x E000 F03C
ARM 2DSP data buffer; write only by ARM, read-only by DSP. 0x E004 0000:0xE004 07FF
Reserved. 0xE004 0800 :0 x E005 FF FF
DSP2ARM data buffer; write only by DSP, read-only by ARM. 0xE006 0000:0xE006 07FF
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9 DSP Communications Con troller (DCC)
(continued)
9.2 DCC Token Register
The DSP communications controller (DCC) provides a 16-bit token register (see Table 73 on page 97). The upper
byte (DSPT) of this register is writable only through the DSP interface. The lower byte (ARMT) of this register is
writable only through the ARM APB bus. The entire 16-bit token register can be read by either interface.
The token register should help the programmer manage the communication buffers. A jitter buffer, for example,
can be implemented by using the token bits to mark full areas and empty sections of the buffer . When an audio
packet is placed in the buffer by the IPT_ARM, it could interrupt the DSP with information about the section where
this packet was placed. The DSP could then use one of its token bits to mark that section as full. At the appropriate
time, the DSP c o uld then remove a packet that wa s placed in its buffer many milliseconds ear lier and mark this
other section as empty.
Table 73. Token Register
Address 0xE000 F000
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15:8 DSPT DSP writable token bits. These bits can only be written through the DSP interface but
7:0 ARMT ARM writable token bit. These bits can only be written by the ARM proc es s o r b u t th e y ar e
31:16 15:8 7:0
RSVD DSPT ARMT
they are readable by both the DSP and the ARM.
readable by both the DSP and the ARM.
9.3 DCC Inter rup t Regi ste rs
There are two DCC interrupt registers in the IPT_ARM. The DSP2ARM interrupt register (see Tabl e 74 on page
98) is used by an external device (the IPT_DSP) to generate an interrupt to the ARM 940T processor core. The
ARM 2DSP interrupt register (see T able 75 on page 98) is written by the ARM 940T processor to generate an
active-low interrupt output. This interrupt output is to be connected to the IPT_DSP interru pt input (DSP_INT0).
Both of these registers are similarly organized. Bit 15, the MSB, is the interrupt bit and can only be written to 1 by
the interrupting processor. Bit 15 (DSP2ARM_INT) in the DSP2ARM interrupt register can only be set by the
external DSP through the DCC interface. Bit 15 (ARM 2DSP_INT) in the ARM 2DSP interrupt register can only
be set by the IPT_ARM processor. DSP2ARM_INT and ARM 2DSP_INT can read by both processors.
When bit 15 is set to 1 by the appropriate processor, INT_CLR and INT_FLAG are automatically set to 1. These
bits can only be written to 0 by the interrupted processor. When the interrupted processor writes INT_CLR to 0, bit
15 is automatically reset to 0 and clears the interrupt. In addition the interrupted processor can write INT_FLAG to
0 to indicate that it has completed the operation, or freed up the memory.
Bits 12:0 (INT_MSG) of the ARM 2DSP interrupt register (see Table 75 on page 98) can only be written by the
interrupting processor, which uses these bits to implement a message-passing protocol to signal the purpose of
the interrupt. These bits can also be used to identify an offset and length in the interprocessor communication buffers where a message, or data, is stored.
This message-interrupt scheme sho uld help the programmers pass data and command s back and forth while preventing a processor from overwriting a set of data in the interprocessor communications buffer before the other
processor has finished accessing it.
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9 DSP Communications Con troller (DCC)
9.3.1 DSP2ARM Interrupt Register
Table 74. DSP2ARM Interrupt Register
Bit #
Name
Bit # Name Description
31:16 RSVD Reserved.
15 DSP2ARM_INT DSP to ARM interrupt. Interrupt from the DSP to the ARM.
14 INT_CLR Interrupt clear. This will clear the interrupt signal.
13 INT_FLAG Interrupt flag. Interrupt flag to signal to the DSP that an interrupt was serviced and
12:0 INT_MSG Interrupt m ess age. Interrupt message from the DSP.
9.3.2 ARM 2DSP Int errupt Regist er
31:16 15 14 13 12:0
RSVD DSP2ARM_INT INT_CLR INT_FLAG INT_MSG
This is controlled only by the ARM.
completed.
This is read-only from the DSP.
This is read-only from the ARM.
Address 0xE000 F020
(continued)
Table 75. ARM 2DSP Interrupt Register
Address 0xE000 F030
Bit #
Name
Bit # Name Description
31:14 RSVD Reserved.
15 ARM 2DSP_INT ARM to DSP interrupt. Interrupt from the ARM to the DSP.
14 INT_CLR Interrupt c l e ar. Interr upt clear w ill c lea r the interrupt sig na l.
13 INT_FLAG Interrupt f lag. Interrupt flag to signal to DSP that interrupt was serviced and com-
12:0 INT_MSG Interrupt m es sage. Interrupt message from the ARM.
31:14 15 14 13 12:0
RSVD ARM2DSP_INT INT_CLR INT_FLAG INT_MSG
This is controlled only by the DSP.
pleted.
This is read-only from the ARM.
This is read-only from the DSP.
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