Datasheet T8100 Datasheet (Lucent Technologies)

Advisory
March 1999

TM

Ambassador

T8100

H.100/H.110 Interface and Time-Slot Interchanger

This advisory details two changes to the AmbassadorTM

Interchanger

Preliminary Data Sheet: DS98-195NTNB.

T8100 H.100/H.110 Interface and Time-Slot

Change Affecting Page 15, Section 2.1.3 Address Mode Register

Problem:

Workaround:

There is a minor bug in the T8100. If a write is issued to the address mode register (AMR)
address 0x70 (local bus, holding registers, and reset), the T8100’s RDY line gets stuck low (not
ready state).

To solve this, issue another write command to any of the four direct registers (MCR, LAR,
AMR, or IDR) and the RDY signal will reset.

Change Affecting Page 38, Section 2.4.2 Dividers and Rate Multipliers

There is an anomaly in the digital phase-lock loop (DPLL) performance of the device. The behavior affects all
versions of the T8100 but has been corrected in the T8100A, T8102, and T8105. This anomaly affects applica­tions that use the DPLL for CT bus clock generation.

When used for clocking, the DPLL uses the 16.384 MHz internal oscillator to rate multiply an 8 kHz input sig­nal. In order for the DPLL to lock to the 8.000000 kHz signal, the required internal oscillator frequency range
should be centered at 16.388 MHz. A frequency of 16.384 MHz is too low for the DPLL to perform properly.

If this crystal adaptation is used for the DPLL, there are several limitations. First, do not select the crystal as a
fallback clock source. When the crystal is a clock source, the generated clocks are all multiples of the crystal. In
that case, they will be offset by the same ratio as the crystal. Second, do not use TCLKOUT. It is also derived
from the crystal and will be offset by the same ratio. Third, the watchdogs will be slightly more sensitive due to
the increased clock frequency. In designs affected by these limitations, conversion to the T8100A is recom­mended.

For additional information, contact your Microelectronics Group Account Manager or the following:
INTERNET:
E-MAIL:

http://www.lucent.com/micro
[e-mail]

N. AMERICA:Microelectronics Group, Lucent Technologies In c., 55 5 Uni on Boulevard, Room 30L-15P-BA, Allentown, PA 1 81 03

1-800-372-2447

, FAX [phone] (In CANADA:

1-800-553-2448

, FAX [phone])

ASIA PACIFIC:Microelectronics Group, Lucent Technologies Singapore Pte. Ltd . , 77 Science Park Drive, #03-18 Cintech III, Singapore 118256

Tel. [phone]

, FAX [phone]

CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai

200233 P. R. China

Tel. [phone], ext. 316

, FAX [phone]

JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE:

Tel. [phone]

Technical Inquiries:GERMANY:

Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.

Copyright © 1999 Lucent Technologies Inc.
All Rights Reserved

, FAX [phone]

(49) 89 95086 0

FRANCE:
ITALY:

(33) 1 40 83 68 00

(39) 02 6608131

(Munich), UNITED KINGDOM:

Tel. [phone]

(Paris), SWEDEN:

(Milan), SPAIN:

(34) 1 807 1441

Ambassador

is a trademark of Lucent Technologies Inc.

, FAX [phone]

(44) 1344 865 900

(46) 8 594 607 00

(Madrid)

(Stockholm), FINLAND:

(Ascot),

(358) 9 4354 2800

(Helsinki),

March 1999
AY99-019NTNB (Replaces AY99-011NTNB and must accompany DS98-195NTNB)

Preliminary Data Sheet
August 1998

H.100/H.110 Interface and Time-Slot Interchanger

1 Product Overview

1.1 Introduction

Increasingly, enhanced telephony services are pro­vided by equipment based on mass-market com­puter-telephony architectures. The H.100 time­division multiplexed (TDM) bus has emerged as the
industry standard used in these systems. The

Ambassador

complete interface for H.100/H.110-based systems.
The T8100 will support the newer bus standards,

H-

MVIP

compatible with
Data can be buffered in either minimum delay or con­stant delay modes on a connection-by-connection
basis.

The T8100 will take advantage of new technology: it
is based on 0.35 micron feature sizes and a robust
standard-cell library. It utilizes associative memory
(content addressable memories [CAM]) in addition to
traditional static RAM and register file structures for
the connection and data memories. The T8100 oper­ates on a single 3.3 V supply, but all inputs are 5 V
tolerant and standard TTL output levels are main­tained.

T8100 is a single devi ce that pro vides a

* and ECTF H.100, but remain downward

MVIP

-90 and

Dialogic’

s† SC-Bus.

TM

Ambassador

Programmable switching between local time slots

■

T8100

and H.100 bus, up to 256 connections
Choice of frame integrity or minimum latency

■

switching on a per-time-slot basis
— Frame integrity to ensure proper switching of

wideband data

— Minimum latency switching to reduce delay in

voice channels

On-chip phase-locked loop (PLL) for H.100,

■

MVIP

or SC-Bus clock operation in master or slave clock
modes

Serial TDM bus rate and format conversion

■

between most standard buses
Optional 8-bit parallel input and/or 8-bit parallel

■

output for local TDM interfaces
High-performance microprocessor interface

■

— Provides access to device configuration regis-

ters and to time-slot data

— Supports both

§

multiplexed/nonmultiplexed modes

Intel

Two independently programmable groups of up to

■

Motorola

‡

nonmultiplexed and

12 framing signals each

3.3 V supply with 5 V tolerant inputs and TTL-com-

■

patible outputs

,

1.2 Features

Complete solution for interfacing board-level cir-

■

cuitry to the H.100 telephony bus
H.100 compliant interface; all mandatory signals

■

Programmable connections to any of the 4096 time

■

slots on the H.100 bus
Up to 16 local serial inputs and 16 local serial

■

outputs, programmable for 2.048 Mbits/s,

4.096 Mbits/s, and 8.192 Mbits/s oper ation per CHI
specifications

Programmable switching between local time slots,

■

up to 1024 connections

Boundary-scan testing support

■

208-pin, plastic SQFP package

■

217-pin BGA package (industrial temperature

■

range)

*

is a registered trademark of GO-MVIP, Inc.

MVIP

†
‡

§

is a registered trademark of Dialogic Corporation.

Dialogic

is a registered trademark of Motorola, Inc.

Motorola

is a registered trademark of Intel Corporation.

Intel

Ambassador

T8100

H.100/H.110 Interfac e and Ti me-Sl ot I nterchanger

Table of Contents

Preliminary Data Sheet

August 1998

Contents Page

1 Product Overview.....................................................1

1.1 Introduction ........................................................1

1.2 Features .............................................................1

1.3 Pin Information ...................................................5

1.4 Enhanced Local Stream Addressing ................10

1.5 Full H.100 Stream Address Support ................10

1.6 Onboard PLLs and Clock Monitors ..................11

1.7 Phase Alignment of Referenced and

Generated Frames ...........................................11

1.8 Interfaces .........................................................11

1.8.1 Microprocessors..........................................11

1.8.2 Framing Groups ..........................................11

1.8.3 General-Purpose Register and I/O..............11

1.9 Applications ......................................................11

1.10 Application Overview .....................................11

2 Architecture and Functional Description.................12

2.1 Register/Memory Maps ....................................14

2.1.1 Main Registers ............................................14

2.1.2 Master Control and Status Register............14

2.1.3 Address Mode Register...............................15

2.1.4 Control Register Memory Space.................16

2.2 Local Bus Section ............................................21

2.2.1 Constant Frame Delay and Minimum

Delay Connections......................................22

2.2.2 Serial and Parallel.......................................23

2.2.3 Data Rates and Time-Slot Allocation ..........23

2.2.4 LBS: Local Stream Control, 0x0C ...............27

2.2.5 State Counter Operation .............................28

2.3 H-Bus Section ..................................................29

2.3.1 Memory Architecture...................................29

2.3.2 CAM Operation and Commands.................31

2.3.3 H-Bus Access..............................................35

2.3.4 L-Bus Access ..............................................36

2.3.5 H-Bus Rate Selection and Connection

Address Format...........................................36

2.4 Clocking Section ..............................................36

2.4.1 Clock and NETREF Selection.....................38

2.4.2 Dividers and Rate Multipliers.......................38

2.4.3 State Machines ...........................................39

2.4.4 Bit Sliding (Frame Locking).........................39

2.4.5 Clock Fallback.............................................39

2.4.6 Clock Control Register Definitions...............41

2.4.7 CKMD, CKND, CKRD: Clocks, Main,
NETREF, Resource Dividers, 0x07, 0x08,

and 0x09 .....................................................46

2.5 Interface Section ..............................................46

2.5.1 Microprocessor Interface.............................46

2.5.2 General-Purpose Register...........................47

2.5.3 Framing Groups ..........................................47

2.6 Error Registers .................................................50

2.7 The JTAG Test Access Port ............................51

2.7.1 Overview of the JTAG Architecture.............51

2.7.2 Overview of the JTAG Instructions..............51

2 Lucent Technologies Inc.

Contents Page

2.7.3 Elements of JTAG Logic............................. 52

2.8 Testing and Diagnostics .................................. 53

2.8.1 Testing Operations..................................... 53

2.8.2 Diagnostics................................................. 53

3 Using the T8100.................................................... 55

3.1 Resets ............................................................. 55

3.1.1 Hardware Reset ......................................... 55

3.1.2 Software Reset........................................... 55

3.1.3 Power-On Reset......................................... 55

3.2 Basic Connections .......................................... 55

3.2.1 Physical Connections for H.110................. 56

3.2.2 H.100 Data Pin Series Termination............ 56

3.2.3 PC Board Considerations........................... 56

3.3 Using the LAR, AMR, and IDR for

Connections .................................................... 57

3.3.1 Setting Up Local Connections.................... 57

3.3.2 Setting Up H-Bus Connections................... 59

3.3.3 Programming Examples............................. 62

3.2.4 Miscellaneous Commands......................... 65

4 Electrical Characteristics....................................... 66

4.1 Absolute Maximum Ratings ............................ 66

4.2 Handling Precautions ...................................... 66

4.3 Crystal Oscillator ............................................. 67

4.4 dc Electrical Characteristics, H-Bus

(ECTF H.100 Spec., Rev. 1.0) ........................ 67

4.4.1 Electrical Drive Specifications—CT_C8

and /CT_FRAME........................................ 67

4.5 dc Electrical Characteristics, All Other Pins .... 68

4.6 H-Bus Timing (Extract from H.100

Spec., Rev. 1.0) .............................................. 69

4.6.1 Clock Alignment ........................................ 69

4.6.2 Frame Diagram .......................................... 70

4.6.3 Detailed Timing Diagram............................ 71

4.6.4 ac Electrical Characteristics, Timing,

H-Bus (H.100, Spec., Rev. 1.0).................. 72

4.6.5 Detailed Clock Skew Diagram.................... 73

4.3.6 ac Electrical Characteristics, Skew

Timing, H-Bus (H.100, Spec., Rev. 1.0)..... 73

4.6.7 Reset and Power On.................................. 73

4.7 ac Electrical Characteristics, Local

Streams, and Frames ...................................... 74

4.8 ac Electrical Characteristics, Micro-

processor Timing ............................................. 75

4.8.1 Microprocessor Access

Write and Read Cycles............................... 75

4.8.2 Microprocessor Access

and Read Cycles........................................ 76

4.8.3 Microprocessor Access

Write Cycle................................................. 77

Intel

Multiplexed

Motorola
Intel

Write

Demultiplexed

Preliminary Data Sheet
August 1998

Ambassador

T8100

H.100/H.110 Interface and Time-Sl ot Interchanger

Table of Contents

Contents Page

5 Outline Diagram......................................................78

5.1 208-Pin Square Quad Flat Package (SQFP) ...78

5.2 217-Pin Ball Grid Array (PBGA) ......................79

6 Ordering Information...............................................79

Appendix A. Application of Clock Modes...................80

Appendix B. Minimum Delay and Constant Delay

Connections...........................................86

B.1 Connection Definitions .....................................86

B.2 Delay Type Definitions ....................................87

B.2.1 Exceptions to Minimum Delay.....................88

B.2.2 Lower Stream Rates...................................88

B.2.3 Mixed Minimum/Constant Delay.................89

Figures Page

Figure 1. Pin Diagram .................................................5

Figure 2. 217 PBGA—Top View .................................6

Figure 3. Block Diagram of the T8100 ......................13

Figure 4. Local Bus Section Function .......................21

Figure 5. Local Bus Memory Connection Modes ......22

Figure 6. Local Streams, Memory Structure .............24

Figure 7. Local Memory, Fill Patterns .......................25

Figure 8. Simplified Local Memory State Timing,

65.536 MHz Clock ...................................28

Figure 9. CAM Architecture ......................................30

Figure 10. Simplified H-Bus State Timing,

65.536 MHz Clock ...................................32

Figure 11. Illustration of CAM Cycles .......................34

Figure 12. Clocking Section ......................................37

Figure 13. A, B, and C Clock Fallback State

Diagram ..................................................40

Figure 14. Frame Group Output Options ..................49

Figure 15. External Connection to PLLs ...................55

Figure 16. Physical Connections for H.110 ..............56

Figure 17. Local-to-Local Connection

Programming ..........................................58

Figure 18. CAM Programming, H-Bus-to-Local

Connection ..............................................60

Figure 19. Clock Alignment ......................................69

Figure 20. Frame Diagram .......................................70

Figure 21. Detailed Timing Diagram .........................71

Figure 22. Detailed Clock Skew Diagram .................73

Figure 23. ac Electrical Characteristics, Local

Streams, and Frames .............................74

(continued)

Figures Page

Figure 24. Microprocessor Access

plexed Write Cycle ................................. 75

Figure 25. Microprocessor Access

plexed Read Cycle ................................. 75

Figure 26. Microprocessor Access

Write Cycle ............................................. 76

Figure 27. Microprocessor Access

Read Cycle ............................................ 76

Figure 28. Microprocessor Access

Demultiplexed Write Cycle ..................... 77

Figure 29. Microprocessor Access

Demultiplexed Read Cycle ..................... 77

Figure 30. E1, CT Bus Master, Compatibility Clock

Master, Clock Source = 2.048 MHz

from Trunk .............................................. 81

Figure 31. T1, CT Bus Master, Compatibility Clock

Master, Clock Source = 1.544 MHz

from Trunk .............................................. 82

Figure 32. E1, Slave to CT Bus, Clock Source Is

Either a 16 MHz or a 4 MHz or a
2 MHz and Frame, NETREF

Source = 2.048 MHz from Trunk ............ 83

Figure 33. T1, Slave to CT Bus, Clock Source Is

Either a 16 MHz or a 4 MHz or a
2 MHz and Frame, NETREF Source

= 1.544 MHz from Trunk ........................ 84

Figure 34. Constant Delay Connections,

CON[1:0] = 0X ........................................ 87

Figure 35. Minimum Delay Connections,

CON[1:0] = 0X ........................................ 88

Figure 36. Mixed Minimum/Constant Delay Con-

nections, CON[1:0 = 10] ......................... 89

Figure 37. Extended Linear (Mixed Minimum/Con-

stant) Delay, CON[1:0] = 11 ................... 90

Intel

Multi-

Intel

Multi-

Motorola
Motorola
Intel
Intel

Lucent Technologies Inc. 3

Ambassador

T8100

H.100/H.110 Interfac e and Ti me-Sl ot I nterchanger

Preliminary Data Sheet

August 1998

Table of Contents

Tables Page

Table 1. Pin Descriptions: Clocking and Framing

Pins ..............................................................6

Table 2. Pin Descriptions: Local Streams Pins ...........8

Table 3. Pin Descriptions: H-Bus Pins ........................8

Table 4. Pin Descriptions: Microprocessor Interface

Pins ..............................................................9

Table 5. Pin Descriptions: JTAG Pins .......................9

Table 6. Pin Descriptions: Power Pins ......................9

Table 7. Pin Descriptions: Other Pins ......................10

Table 8. Addresses of Programming Registers ........14

Table 9. Master Control and Status Register ..........14

Table 10. Address Mode Register ............................15

Table 11. Control Register Memory Space ..............16

Table 12. CKM: Clocks, Main Clock Selection,

0x00 .........................................................17

Table 13. CKN: Clocks, NETREF Selections,

0x01 .........................................................17

Table 14. CKP: Clocks, Programmable Outputs,

0x02 .........................................................17

Table 15. CKR: Clocks, Resource Selection,

0x03 .........................................................17

Table 16. CKS: Clocks, Secondary (Fallback)

Selection, 0x04 ........................................17

Table 17. CK32: Clocks, Locals 3 and 2, 0x05 ........17

Table 18. CK10: Clocks, Locals 1 and 0, 0x06 ........17

Table 19. CKMD: Clocks, Main Divider; CKND:

Clocks, NETREF Divider; CKRD: Clocks,

Resource Divider, 0x07, 0x08, 0x09 ........18

Table 20. LBS: Local Stream Control, 0x0C ............18

Table 21. CON: Connection Delay Type, 0x0E .......18

Table 22. HSL: H-Bus Stream Control, Low

Byte, 0x10 ...............................................18

Table 23. HSH: H-Bus Stream Control, High

Byte, 0x11 ...............................................18

Table 24. GPR: General-Purpose I/O Register,

0x18 .........................................................18

Table 25. FRLA: Frame Group A, Start Address

Low, 0x20 ................................................19

Table 26. FRHA: Frame Group A, High Address

and Control, 0x21 ....................................19

Table 27. FRLB: Frame Group B, Start Address

Low, 0x22 ................................................19

Table 28. FRHB: Frame Group B, High Address

and Control, 0x23 ....................................19

Table 29. FRPL: Frame Group B, Programmed

Output, Low, 0x24 ...................................19

Table 30. FRPH: Frame Group B, Programmed

Output, High, 0x25 ..................................19

Table 31. CLKERR1: Clock Error Register, Error

Indicator, 0x28 .........................................20

Table 32. CLKERR2: Clock Error Register, Current

Status, 0x29 ............................................20

Table 33. SYSERR: System Error Register,

0x2A ........................................................20

Table 34. CKW: Clock Error/Watchdog Masking

Register, 0x2B .........................................20

(continued)

Tables Page

Table 35. DIAG1: Diagnostics Register 1, 0x30 ..... 20

Table 36. DIAG2: Diagnostics Register 2, 0x31 ..... 20

Table 37. DIAG3: Diagnostics Register 3, 0x32 ..... 20

Table 38. LBS: Local Stream Control, 0x0C ........... 27

Table 39. CKM: Clocks, Main Clock Selection,

0x00 ......................................................... 41

Table 40. CKN: Clocks, NETREF Selections,

0x01 ......................................................... 42

Table 41. CKP: Clocks, Programmable Outputs,

0x02 ......................................................... 43

Table 42. CKR: Clocks, Resource Selection,

0x03 ......................................................... 44

Table 43. CKS: Clocks, Secondary (Fallback)

Selection, 0x04 ........................................ 45

Table 44. CK32 and CK10: Clocks, Locals 3, 2, 1,

and 0, 0x05 and 0x06 .............................. 46

Table 45. FRHA, Frame Group A High Address

and Control, 0x21 ................................... 47

Table 46. FRHB, Frame Group B High Address

and Control, 0x23 .................................... 47

Table 47. FRPH: Frame Group B, Programmed

Output, High, 0x25 .................................. 48

Table 48. CLKERR1 and CLKERR2: Error Indicator

and Current Status, 0x28 and 0x29 ......... 50

Table 49. SYSERR: System Error Register,

0x2A ........................................................ 50

Table 50. T8100 JTAG Instruction Set ................... 51

Table 51. T8100 JTAG Scan Register .................... 52

Table 52. Time-Slot Bit Decoding ............................ 57

Table 53. IDR: Indirect Data Register, Local

Connections Only .................................... 58

Table 54. IDR: Indirect Data Register, H-Bus

Connections Only ................................... 59

Table 55. Crystal Oscillator ..................................... 67

Table 56. Alternative to Crystal Oscillator ............... 67

Table 57. Electrical Drive Specifications—CT_C8

and /CT_FRAME ..................................... 67

Table 58. dc Electrical Characteristics, All Other

Pins .......................................................... 68

Table 59. ac Electrical Characteristics, Timing,

H-Bus (H.100, Spec., Rev. 1.0) .............. 72

Table 60. ac Electrical Characteristics, Skew

Timing, H-Bus (H.100, Spec., Rev. 1.0) . 73

Table 61. Reset and Power On ............................... 73

Table 62. ac Electrical Characteristics, Local

Streams, and Frames .............................. 74

Table 63. Microprocessor Access Timing (See

Figure 24 through Figure 29.) ................. 77

Table 64. Clock Register Programming Profile for

the Four Previous Examples .................. 85

Table 65. Table of Special Cases (Exceptions) ....... 88

4 Lucent Technologies Inc.

Preliminary Data Sheet
August 1998

Ambassador

T8100

H.100/H.110 Interface and Time-Sl ot Interchanger

1 Product Overview

1.3 Pin Information

CT_D24

CT_D26

CT_D25

VSS

CT_D27
CT_D28

CT_D29
CT_D30
CT_D31

LDO0
LDO1
LDO2
LDO3

LDO4
LDO5
LDO6
LDO7

LDO8

LDO9
LDO10
LDO11

LDO12
LDO13
LDO14
LDO15

LDI10

LDI11

LDI12

LDI13

LDI14

LDI15

TCLKOUT

PLL2GND

PLL2VDD

VDD

VSS

VDD

VSS

VDD

XCS
VSS
LDI0
LDI1
LDI2
LDI3
LDI4
LDI5
LDI6
LDI7
VDD
LDI8
LDI9

(NC)
VSS

(NC)
(NC)

157

1

(continued)

CT_D23

CT_D21

VDD

CT_D22

CT_D20

CT_D19

CT_D18

CT_D16

CT_D15

CT_D17

VSS

CT_D14

CT_D13

CT_D12

VSS

CT_D11

CT_D10

(NC)

CT_D9

CT_D8

VDD

CT_D7

CT_D5

VSS

CT_D2

CT_D1

VSS

VSS

VSS

/FR_COMP

VSS

VSS

CT_D6

CT_D4

CT_D3

VDD

CT_D0

/CT_FRAME_A

CT_C8_A

CT_NETREF

VSS

/CT_FRAME_B

CT_C8_B

SCLK

SCLKX2

VDDC2VSS

105

/C4
VSS
/C16+
/C16–
VSS
FGA0
FGA1
FGA2
FGA3
FGA4
FGA5
VDD
FGA6
FGA7
FGA8
FGA9
FGA10
FGA11
VSS
FGB0
FGB1
FGB2
FGB3
FGB4
FGB5
VDD
FGB6
FGB7
FGB8
FGB9
FGB10
FGB11
VSS
GP0
GP1
GP2
GP3
GP4
GP5
TODJAT/GP6
FROMDJAT/GP7
VDD
(NC)
(NC)
(NC)
(NC)
PRIREFOUT
VSS
(NC)
EN1
4MHZIN
PLL1VDD

53

D0

VSS

D1

VDD

CLKERR

SYSERR

TDI

EN2

(NC)

DPUE

3MHZIN

TTS

TMS

TDO

TCLK

TRST

D7

D5

D3

VSS

RESET

RDY (DTACK

)

D6

D4

D2

A1

A0

CS

ALE

RD (DS)

WR (R/W)

VSS

VDD

L_SC3

L_SC2

L_SC1

L_SC0

L_REF4

L_REF2

L_REF0

L_REF5

L_REF3

L_REF1

VSS

(NC)

VDD

L_REF6

L_REF7

(NC)

XTALIN

PLL1GND

XTALOUT

5-6118bF

Figure 1. Pin Diagram

Lucent Technologies Inc. 5

Ambassador

T8100

H.100/H.110 Interfac e and Ti me-Sl ot I nterchanger

Preliminary Data Sheet

August 1998

1 Product Overview

1.3 Pin Information

184

1

A

SS

2

B

C

D

E

F

G

H

J

K

10

13

17

20

22

24

26

V

6

3

7

11

14

18

21

23

27

(continued)

180

183

SS

V

4

9

12

15

19

25

28

(continued)

176

173

179

175

182

178

V

181

SS

5

8

16

V

DD

V

SS

V

DD

171

172

174

177

167

168

170

169

164

165

166

V

V

V

V

DD

SS

SS

SS

162

161

163

V

V

V

V

160

158

155

159

156

152

157

153

150

V

SS

SS

SS

SS

154

DD

V

SS

V

SS

V

SS

146

151

149

147

143

148

145

142

V

135

131

123

V

V

V

SS

DD

SS

DD

141

V

136

132

128

124

120

117

111

139

SS

V

138

SS

137

134

133

130

129

127

126

125

122

121

119

118

115

116

113

114

140

144

29

L

M

N

P

R

T

U

30

33

34

37

35

41

38

45

42

SS

46

V

47

48

1234567891011121314151617

31

32

39

36

43

40

44

V

SS

49

52

51

V

SS

50

53

56

55

57

59

54

58

60

63

62

61

64

66

V

V

77

85

82

80

79

89

86

83

81

DD

SS

71

69

70

74

73

72

DD

78

76

75

V

65

67

68

Figure 2. 217 PBGA—Top View

Table 1. Pin Descriptions: Clocking and Framing Pins

Symbol Pin Ball Type Name/Description

L_REF[7:0] 45—38 P3, N4, R1, P2, N3,

Local Frame Reference Inputs.

I

M4, P1, N2

MVIP

/C16+
/C16–

102
101

R14
P13

H-

I/O

drive, Schmitt in, 50 kΩ internal pull-up.

16.384 MHz Clock Signals.

107

104

101

96

V

91

88

110

112

106

109

103

105

99

102

95

SS

98

V

SS

94

92

93

108

100

97

V

90

87

84

SS

50 kΩ internal pull-up.

Differential 24 mA

5-6626(F)

6 Lucent Technologies Inc.

Preliminary Data Sheet
August 1998

Ambassador

T8100

H.100/H.110 Interface and Time-Sl ot Interchanger

1 Product Overview

1.3 Pin Information

Table 1. Pin Descriptions: Clocking and Framing Pins

Symbol Pin Ball Type Name/Description

/C4 104 U16 I/O

C2 106 T17 I/O

SCLK 110 R17 I/O

SCLKX2

L_SC[3:0] 36—33 M3, N1, M2, M1 O

FGA[5:0] 94—99 R12, T13, U14, P12,

FGA[11:6] 87—92 T11, P11, R11, U12,

FGB[5:0] 80—85 U9, R9, U10, T10,

FGB[11:6] 73—78 U6, T7, R8, U7, T8,

PRIREFOUT 58 P5 O

PLL1V

DD

PLL1GND 51 No ball for this

EN1 55 T3 I

4MHZIN 54 U2 I

PLL2V

DD

PLL2GND 206 No ball for this

EN2 3 C2 I

3MHZIN 1 A1 I

XTALIN 47 R2 I

XTALOUT 48 T1 O

TCLKOUT 203 C4 O Selected output to drive framers. 8 mA drive, 3-state.

108 P15 I/O

53 U1 —

208 A2 —

(continued)

(continued)

R13, T14

T12, U13

R10, U11

U8

signal, internally

connected.

signal, internally

connected.

(continued)

MVIP

4.096 MHz Clock.

internal pull-up.

MVIP

2.048 MHz Clock.

internal pull-up.

SC-Bus 2/4/8 MHz Clock.

internal pull-up.

SC-Bus Inverted 4/8 MHz Clock (Active-Low).

drive, Schmitt in, 50 kΩ internal pull-up.

Local Selected Clocks.

4.096 MHz, 8.192 MHz, 16.384 MHz, frame (8 kHz), or sec­ondary (NETREF). 8 mA drive, 3-state.

Frame Group A.

O

Frame Group B.

O

Output from Primary Clock Selector/Divider.
PLL #1 VCO Power.

even if PLL #1 is not used.

PLL #1 VCO Ground.

—

ground, even if PLL #1 is not used.

PLL #1 Enable.

reset, or may be driven with RESET
pull-up.

PLL #1 Rate Multiplier.

50 kΩ internal pull-up.

PLL #2 VCO Power.

if PLL #2 is not used and 3MHZIN is used. Can be l eft float­ing only if both PLL #2 and 3MHZIN are not used.

PLL #2 VCO Ground.

—

ground if PLL #2 is not used and 3MHZIN is used. Can be
left floating only if both PLL #2 and 3MHZIN are not used.

PLL #2 Enable.

reset, or may be driven with RESET
pull-up.

PLL #2 Rate Multiplier.

16.384 MHz Crystal Connection or External Clock
Input.

16.384 MHz Crystal, Feedback Connection.

8 mA drive, 3-state.

Requires cap to V

Requires cap to V

8 mA drive, Schmitt in, 50 kΩ

8 mA drive, Schmitt in, 50 kΩ

24 mA drive, Schmitt in, 50 kΩ

1.024 MHz, 2.048 MHz,

8 mA drive, 3-state.

This pin must be connected to power,

This pin must be connected to

to form power-on

SS

line. 50 kΩ internal

Can be 2.048 MHz or 4.096 MHz.

This pin must be connected to power

This pin must be connected to

to form power-on

SS

line. 50 kΩ internal

Input, 50 kΩ internal pull-up.

24 mA

8 mA drive.

Lucent Technologies Inc. 7

Ambassador

T8100

H.100/H.110 Interfac e and Ti me-Sl ot I nterchanger

Preliminary Data Sheet

August 1998

1 Product Overview

1.3 Pin Information

Table 2. Pin Descriptions: Local Streams Pins

Symbol Pin Ball Type Name/Description

LDI[15:8]

LDI[7:0]

LDO[15:12]

LDO[11:8]

LDO[7:4]
LDO[3:0]

Table 3. Pin Descriptions: H-Bus Pins

Symbol Pin Ball Type Name/Description

CT_D[31:28]
CT_D[27:24]
CT_D[23:20]
CT_D[19:16]
CT_D[15:12]
CT_D[11:10]

CT_D[9:8]
CT_D[7:4]
CT_D[3:2]
CT_D[1:0]

/CT_FRAME_A 120 L14 I/O

/CT_FRAME_B 114 P17 I/O

/FR_COMP 115 M15 I/O

CT_NETREF 116 N17 I/O

CT_C8_A 118 M16 I/O

CT_C8_B 112 M14 I/O

DPUE 4 D3 I

201—194
192—185

182—179
177—174
172—169
167—164

162—159
157—154
152—149
147—144
142—139
137—136
134—133
131—128
126—125
123—122

(continued)

(continued)

A3, B4, C5, D6, A4, B5, C6, A5
B6, A6, C7, D7, B7, A7, C8, B8

C9, A9, B9, A10

B10, A11, C10, B11
D11, C11, B12, A13
B13, A14, C13, D12

A15, D13, C14, B15
A17, C16, D15, E14
C17, D16, E15, F14

D17, E16, F15, E17

F16, F17, G15, G14

G16, G17
H15, H16

H17, J15, J17, J16

K17, K16
L17, K15

Local Data Input Streams.

I

nal pull-up.

Local Data Output Streams.

O

drive, 3-state.

H-Bus, Data Lines.

I/O

4 Mbits/s, 8 Mbits/s. 5 V tolerant, PCI compliant,
50 kΩ internal pull-up.

To conform to H.100, connect an external 24 Ω
series, 1/8 W resistor between each pin and the
bus. Also, data lines 16—31 should be pro­grammed to 8 Mbits/s.

H-Bus, 8 kHz, Frame.

24 mA drive, Schmitt in. No pull-up.

H-Bus, Alternate 8 kHz Frame.

compliant, 24 mA drive. Schmitt in. No pull-up.

H-Bus, Compatibility Frame Signal.

Schmitt in, 50 kΩ internal pull-up.

H-Bus, Network Reference.

1.544 MHz. 8 mA drive, slew rate limited, Schmitt
in. Not internally pulled up.

H-Bus, Main Clock.

24 mA drive, Schmitt in. No pull-up.

H-Bus, Alternate Main Clock.

compliant, 24 mA drive, Schmitt in. No pull-up.

Data Pull-Up Enable.

CT_Dxx only for H.100, low disables for H.110.
50 kΩ internal pull-up.

Variable rate 2 Mbits/s,

5 V tolerant, PCI compliant,

8 kHz, 2.048 MHz, or

5 V tolerant, PCI compliant,

5 V tolerant, PCI

High enables pull-ups on

50 kΩ inter-

8 mA

5 V tolerant, PCI

24 mA drive,

8 Lucent Technologies Inc.

Preliminary Data Sheet
August 1998

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T8100

H.100/H.110 Interface and Time-Sl ot Interchanger

1 Product Overview

1.3 Pin Information

Table 4. Pin Descriptions: Microprocessor Interface Pins

Symbol Pin Ball Type Name/Description

RESET

A[1:0] 31—30 L4,

D[7:0] 22—15 H1,

ALE 29 L1 I

CS

RD

(DS)

WR

(R/W)

RDY (DTACK

CLKERR 13 E1 O

SYSERR 12 F3 O

24 J1 I

28 K3 I
27 K2 I

26 K1 I

25 J3 O

)

(continued)

(continued)

L2

I/O
H2,
G1,
H3,
G2,
F1,
G4,

G3

Master Reset (Active-Low).

up.

Microprocessor Interface, Address Lines.

I

Microprocessor Interface, Data Lines.

Address Latch Enable.
Chip Select (Active-Low).

Intel

Read Strobe (
Low]).

50 kΩ internal pull-up.

Write Strobe (
Low]).

Data Ready (

8 mA, open drain (user should add pull-up to this line).

Clock Error.

3-state

System Error.

8 mA drive, 3-state.

50 kΩ internal pull-up.

Mode [Active-Low]), Data Strobe (

Intel

[Active-Low]), Read/Write Select (

Intel

), Data Transfer (

Logical OR of CLKERR register flags (only). 8 mA drive,

Logical OR of all CLKERR and SYSERR register flags.

See Section 3.1 Resets. 50 kΩ internal pull-

Internal 20 kΩ pull-down.

50 kΩ internal pull-up.

Motorola

Internal 20 kΩ pull-down.

8 mA drive, 50 kΩ internal pull-up.

Motorola

Motorola

[Active-Low]).

[Active-

[Active-

Table 5. Pin Descriptions: JTAG Pins

Symbol Pin Ball Type Name/Description

TCLK 9 E3 I

TMS 8 F4 I

TDI 7 D2 I

TDO 6 C1 O

TRST

Table 6. Pin Descriptions: Power Pins

Symbol Pin Ball Type Name/Description

V

SS

V

DD

Lucent Technologies Inc. 9

11, 23, 37, 49, 57, 72,

86, 100, 103, 105, 109,
111, 113, 117, 119, 121,
127, 138, 143, 153, 163,

173, 184, 204

14, 32, 46, 63, 79, 93,

107, 124, 132, 148, 158,

168, 178, 193

5E4I

JTAG Clock Input.
JTAG Mode Select.
JTAG Data Input.
JTAG Data Output.
JTAG Reset (Active-Low).

B2, B16, C3, C15, D4,

D9, D14, H8, H9, H10,

J4, J8, J9, J10, J14,

K8, K9, K10, L15, N14,

P4, P9, P14, P16, R3,

R15, T2, T15, T16,

U15, U17

A16, D8, D10, F2, H4,

H14, K4, K14, L16, P8,

P10, T9

50 kΩ internal pull-up.

50 kΩ internal pull-up.

8 mA drive, 3-state.

50 kΩ internal pull-up.

Chip Ground.

—

3.3 V Supply Voltage

—

.

Ambassador

T8100

H.100/H.110 Interfac e and Ti me-Sl ot I nterchanger

Preliminary Data Sheet

August 1998

1 Product Overview

1.3 Pin Information

Table 7. Pin Descriptions: Other Pins

Symbol Pin Ball Type Name/Description

GP[5:0] 66—71 T5, R6, U5, T6, R7, P7 I/O

TODJAT/GP6 65 U4 I/O

FROMDJAT/GP7 64 R5 I/O

XCS 183 A8 O

TTS 10 D1 I

(NC) 2, 50, 52, 56,

(continued)

(continued)

59, 60, 61, 62,
135, 202, 205,

207

A12, B1, B3, B14, B17,

C12, D5, E2, J2, L3, M17,

N15, N16, P6, R4, R16,

T4, U3

General-Purpose Bidirectional Regis­ter.

8 mA drive, Schmitt in, 50 kΩ inter-

nal pull-up.

Output from Selector to Drive DJAT
(for NETREF) or GP Register Bit 6.

8 mA drive, Schmitt in, 50 kΩ internal
pull-up.

Smoothed Input to NETREF Divider
and Drivers or GP Register Bit 7.

8 mA drive, input, Schmitt in, 50 kΩ
internal pull-up.

Serial Output from Connection Mem­ory.

8 mA drive, 3-state.

Test Type Select.

output test, internal pulldown.

Reserved, No Connection.

—

0 = JTAG, 1 = forced

1.4 Enhanced Loc al Stream Addressing

Local stream addressing has 1024 locations. Separate
connection and data memories maintain all necessary
information for local stream interconnections. The
streams may operate at maximum rate on eight physi­cal inputs and eight physical outputs. Choices for
slower input or output rates allow enab li ng of additional
physical inputs or outputs for a maximum of 16 pins
each. Data rates are 2.048 Mbits/s, 4.096 Mbits/s, or

8.192 Mbits/s.
In addition to the enhanced serial streaming, the local

memories may be used for 8-line-serial-in/1-byte-paral­lel-out, 1-byte-parallel-in/8-line-serial-out, or 1-byte­parallel-in/1-byte-parallel-out options. All three data
rates are supported in the parallel modes. The
addresses for the local memories have been simplified
so that stream and time-slot designations are automati­cally translated to the appropriate memory address,
regardless of rate or serial/parallel modes.

1.5 Full H.100 Stream Address Support

The T8100 provides access to the full 4096 H.100 bus
slots (32 streams x 128 slots) or any standard subset
(H-

MVIP

has a maximum 24 streams x 128 time
slots, for example). The number of stored time-slot
addresses is limited to 256 at any one time, but these
may be updated on the fly. In addition, accesses to and
from the H.100 bus can be directed through the 1024
local stream/time slots, giving a total space of 5120
time slots. Data rates are programmable on each of
the 32 physical streams, selected in groups of four.
The rates are 2.048 Mbits/s, 4.096 Mbits/s, or

8.192 Mbits/s.

10 Lucent Technologies Inc.

Preliminary Data Sheet
August 1998

Ambassador

T8100

H.100/H.110 Interface and Time-Sl ot Interchanger

1 Product Overview

(continued)

1.6 Onboard PLLs an d Cl ock Monitors

The T8100 uses rate multipliers and state machines to
generate onboard frequencies for supporting the
H.100, H­provided for coupling the internal clock circuitry with
commonly available clock adapters and jitter attenua­tors. If external resources are not available, an internal
digital phase-locked loop (DPLL) can be used to gener­ate all the bus frequencies and remain synchronized to
an 8 kHz reference. One of several clock input refer­ence sources may be selected, and separate input­active detection logic can identify the loss of the individ­ual input references. The entire cl oc ki ng st ructure oper­ates from a 16.384 MHz crystal or external input.

MVIP, MVIP

, MC-1, and SC-Buses. Pins are

1.7 Phase Alignment of Referenced and
Generated Frames

If this resource is selected, special control logic will cre­ate bit-sliding in the data streams when the reference
frame and generated frame are out of phase. The bit­sliding refers to removing a fraction of a bit time per
frame until the frames are in phase.

1.8 Interface s

1.8.1 Microprocessors

The T8100 provides the user a choice of either

ola

or

Intel

interfacing through an 8-bit data bus, a 2-bit
address bus, and multifunction control pins. All access
to T8100 memory blocks and registers use indirect
addressing.

1.8.2 Framing Groups

Two groups of programmable framing signals are avail­able. Each group is composed of 12 sequenced lines
operating in one of four modes. The T8100 supports
1-bit, 2-bit, 1-byte, and 2-byte pulse widths. Starting
position of the pulse sequences are also programma­ble.

Motor-

1.8.3 General-Purpose Register and I/O

A general-purpose register is provided as either a byte­wide input or byte-wide output through a separate set
of pins.

1.9 Applications

■

Computer-telephony systems

■

Enhanced service platforms

■

WAN access devices

■

PBXs

■

Wireless base stations

1.10 Application Overview

The integration of computers and telecommunications
has enabled a wide range of new communications
applications and has fueled an enormous growth in
communications markets. A key element in the devel­opment of computer-based communications equipment
has been the addition of an auxiliary telecom bus to
existing computer systems. Most manufacturers of
high-capacity, computer-based telecommunications
equipment have incorporated some such telecom
bus in their systems. Typically, these buses and bus
interfaces are designed to transport and switch
N x 64 kbits/s low-latency telecom traffic between
boards within the computer, independent of the com­puter’s I/O and memory buses. At least a half dozen of
these PC-based telecom buses emerged in the early
1990s for use within equipment based on ISA/EISA
and MCA computers.

With the advent of the H.100 bus specification by the
Enterprise Computer Telephony Forum, the computer­telephony industry has agreed on a single telecom b us
for use with PCI and compact PCI computers. H.100
facilitates interoperation of components, thus prov iding
maximum flexibility to equipment manufacturers, value­added resellers, system integrators, and others build­ing computer-based telecommunications applications.

Lucent Technologies Inc. 11

Ambassador

T8100

H.100/H.110 Interface and Time-Slot Interchanger

2 Architecture and Functional Descrip­tion

The T8100 is an H.100-compliant device that provides
a complete interface between the H.100 bus and a
wide variety of telephony interface components, pro­cessors, and other circuits. The bus interface provides
all signals needed for the H.100 bus, the H-

MVIP

-90 buses, or the SC-Bus. Local interfaces
include 16 serial inputs and 16 serial outputs based on
the Lucent Technologies Microelectronics Group con­centration highway interface (CHI). Two built-in time­slot interchangers are included. The first provides a
local switching domain with up to 1024 programmable
connections between time slots on the local CHI inputs
and outputs. The second supports up to 256 program­mable connections between any tim e slot on the H.100
bus and any time slot in the local switching domain.
The

Ambassador

is configured via a microprocessor
interface. This interface can also read and write time
slot and device data. Onboard clock circuitry, including
a DPLL, supports all H.100 clock modes including

MVIP

and

MVIP

The local CHI interfaces support PCM rates of

2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s. The
T8100 has internal circuitry to support either minimum
latency or multi-time-slot fr ame integrity. Frame integrity
is a requisite feature for applications that switch wide­band data (ISDN H-channels). Minimum latency is
advantageous in voice applications.

The T8100 has four major sections:

■

■

■

■

Figure 3 shows a T8100 block diagram. The T8100
operates on a 3.3 V supply for both the core and I/Os,
though the I/Os are TTL compatible and 5 V tolerant.

Preliminary Data Sheet

August 1998

and SC-Bus compatibility clocks.

Local bus—refers to the local streams.
H-Bus—refers to the H.100/H.110/H-

legacy streams.
Interface—refers to the microprocessor interface,

frame groups, and general-purpose I/O (GPIO).
Timing—the rate multipliers, DPLL, and clocking

functions.

MVIP

and

1212 Lucent Technologies Inc.

Preliminary Data Sheet
August 1998

Ambassador

T8100

H.100/H.110 Interface and Time-Sl ot Interchanger

2 Architecture and Functional Description

MVIP, MVIP

256

LOCATION

DATA
SRAM

THREE 256

LOCATION

CONNECTION

CAMs

1024

LOCATION

DATA

MEMORY

INPUT
LOGIC

AND S/P

CONVERT

H.100, H.110, H-

S/P AND P/S CONVERTERS

(continued)

, SC-BUS

OUTPUT

LOGIC

AND P/S

CONVERT

LOCAL OUTLOCAL IN

1024

ADDR[1:0]

DATA[7:0]

INTERNAL
ADDRESS

AND

CONTROL

MICROPROCESSOR

INTERFACE

LOCATION

CONNECTION

MEMORY

INTERNAL

CLOCKS AND

STATE

COUNTER

TIMING AND

CONTROL

INTERNAL

DATA

FRAME GROUP

INTERFACE

LOGIC

FRAME

GROUPS

………

µ

P CONTROLS MISC. I/O CLOCKS AND REFS

5-6101.a (F)

Figure 3. Block Diagram of the T8100

Lucent Technologies Inc. 13

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T8100
H.100/H.110 Interfac e and Ti me-Sl ot I nterchanger

Preliminary Data Sheet

August 1998

2 Architecture and Functional Description

(continued)

2.1 Register/Memory Maps

In this section, a general overview of the registers and the indirect mapping to different memory spaces is
described. More detailed descriptions for using the regi sters in s oftw are can be found in Section 3.2 Basic Connec­tions.

(Throughout this document, all registers are defined with the MSB on the left and the LSB on the right.)

2.1.1 Main Registers

The address bits are used to map a large memory space.
All registers default to 0 at powerup.

Table 8. Addresses of Programming Registers

A1 A0 Name Description

0 0 MCR Master Control and Status Register (read/write)
0 1 LAR Lower Address Register—Lower Indirect Address (time slot) (write only)
1 0 AMR Address Mode Register—Upper Address (stream) and Address Type (write only)
1 1 IDR Indirect Data Register (read/write)

2.1.2 Master Control and Status Register
Table 9. Master Control and Status Register

Bit Name Description

7MR
6CER
5SER

4AP

3HBE

2LBE
1LCE

0CB

Master (Software) Reset
Clock Error Reset
System Error Reset

CER, and SER are automatically cleared by the T8100 after the requested reset is com­plete.)

Active Page

zero indicates buffer 0; a one indicates buffer 1. The AP identifies which data buffer is being
accessed during a write operation (i.e., input from local streams or input from H-Bus).

H-Bus Enable

HBE must be set high to reenable the 3-stated buffers.

Local Bus Enable
Local Clock Enable

the TCLKO is disabled during a Master Reset and is unaffected by HBE, LBE, or LCE,
though there are control bits for this signal in the CKP register, Section 2.4.6 Clock Control
Register Definitions.)

CAM Busy

means that one (or more) of the CAMs is being accessed by the microprocessor. In most
cases, this bit will read low since there are many internal operational cycles dedicated to the
microprocessor, which allow it to finish quickly.

. This bit identifies which of the double-buffered data memories are active. A

. On powerup or software reset, all H-Bus pins (inc luding cl ocks) are disabled.

. A status bit indicating microprocessor activity in any of the CAM blocks. A high

. A high reinitializes the T8100 registers.

. A high resets the error bits of the CLKERR registers.

. A high resets the error bits of the SYSERR register. (Note that MR,

. Same function as HBE for local data outputs.

. Enables all other local functions: clocks, frame groups, etc. (Note that

14 Lucent Technologies Inc.

Preliminary Data Sheet
August 1998

Ambassador

T8100

H.100/H.110 Interface and Time-Sl ot Interchanger

2 Architecture and Functional Description

2.1 Register/Memory Maps

2.1.3 Address Mode Register

The AMR is defined in Table 10 below where (aaaa) is the stream address and the LAR is the time-slot address of
the selected memory space.

Note:

All unused AMR values are reserved.

Table 10. Address Mode Register

Bits 7—4 Bits 3—0 Register Function

0000 0000 Control Registers.
0001 (aaaa) Local Bus, Data Memory 1.
0010 (aaaa) Local Bus, Data Memory 2.
0100 (aaaa) Local Bus, Connection Memory, Time-Slot Field.
0101 (aaaa) Local Bus, Connection Memory, Stream, and Control Bit Field.
0111 0000 Local Bus, Holding Registers, Reset.
1001 0000 CAM, Data Memory 1.
1010 0000 CAM, Data Memory 2.
1011 0000 CAM, Connection, Time-Slot Field.
1011 0001 CAM, Connection, Stream, and Control Bit Field.
1011 0010 CAM, Connection, Tag Field.
1110 0000 CAM, Even, Make Connection (MKCE). Write to next free location.
1110 0001 CAM, Odd, Make Connection (MKCO). Write to next free location.
1110 0011 CAM, Local, Make Connection (MKCL). Write to next free location.
1110 0100 CAM, Even, Break Connection (BKCE).
1110 0101 CAM, Odd, Break Connection (BKCO).
1110 0111 CAM, Local, Break Connection (BKCL).
1110 1000 CAM, Even, Clear Location (CLLE). Requires LAR.
1110 1001 CAM, Odd, Clear Location (CLLO). Requires LAR.
1110 1011 CAM, Local, Clear Location (CLLL). Requires LAR.
1110 1100 CAM, Even, Read Location (RDCE). Requires LAR, IDR holds results.
1110 1101 CAM, Odd, Read Location (RDCO). Requires LAR, IDR holds results.
1110 1111 CAM, Local, Read Location (RDCL). Requires LAR, IDR holds results.
1111 0000 CAM, Even, Find Entry (FENE). IDR holds results.
1111 0001 CAM, Odd, Find Entry (FENO). IDR holds results.
1111 0011 CAM, Local, Find Entry (FENL). IDR holds results.
1111 1000 CAM, Even, Reset (RSCE).
1111 1001 CAM, Odd, Reset (RSCO).
1111 1011 CAM, Local, Reset (RSCL).
1111 1100 CAM, Holding Registers, Reset (RCH).
1111 1111 CAM, Initialize (CI). Reset all CAM locations and holding registers.

(continued)

(continued)

Lucent Technologies Inc. 15

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T8100
H.100/H.110 Interfac e and Ti me-Sl ot I nterchanger

Preliminary Data Sheet

August 1998

2 Architecture and Functional Description

2.1 Register/Memory Maps

2.1.4 Control Register Memory Space

Function of LAR values when AMR = 0x00. All control registers reset to 0x00.

Table 11. Control Register Memory Space

Register
Address

0, 0x00 CKM Clocks, Main Clock Selections 2.4.6
1, 0x01 CKN Clocks, NETREF Selections 2.4.6
2, 0x02 CKP Clocks, Programmable Outputs 2.4.6
3, 0x03 CKR Clocks, Resource Selection 2.4.6
4, 0x04 CKS Clocks, Secondary (Fallback) Selection 2.4.6
5, 0x05 CK32 Clocks, Locals 3 and 2 2.4.6
6, 0x06 CK10 Clocks, Locals 1 and 0 2.4.6
7, 0x07 CKMD Clocks, Main Divider 2.4.6
8, 0x08 CKND Clocks, NETREF Divider 2.4.6
9, 0x09 CKRD Clocks, Resource Divider 2.4.6

10—11, 0x0A—0x0B (Reserved) — —

12, 0x0C LBS Local Stream Control 2.2.4
13, 0x0D (Reserved) — —
14, 0x0E CON Connection Delay Type Appendix B
15, 0x0F (Reserved) — —
16, 0x10 HSL H-Bus Stream Control, Low Byte 2.3.5
17, 0x11 HSH H-Bus Stream Control, High Byte 2.3.5

18—23, 0x12—0x17 (Reserved) — —

24, 0x18 GPR General-purpose I/O Register 2.5.2

25—31, 0x19—0x1F (Reserved) — —

32, 0x20 FRLA Frame Group A, Start Address, Low 2.5.3
33, 0x21 FRHA Frame Group A, High Address and Control 2.5.3
34, 0x22 FRLB Frame Group B, Start Address, Low 2.5.3
35, 0x23 FRHB Frame Group B, High Address and Control 2.5.3
36, 0x24 FRPL Frame Group B, Programmed Output, Low 2.5.3
37, 0x25 FRPH Frame Group B, Programmed Output, High 2.5.3

38—39, 0x26—0x27 (Reserved) — —

40, 0x28 CLKERR1 Clock Error Register, Error Indicator 2.6
41, 0x29 CLKERR2 Clock Error Register, Current Status 2.6
42, 0x2A SYSERR System Error Register 2.6
43, 0x2B CKW Clock Error/Watchdog Masking Register 2.4.6 & 2.6

44—47, 0x2C—0x2F (Reserved) — —

48, 0x30 DIAG1 Diagnostics Register 1 2.8.2
49, 0x31 DIAG2 Diagnostics Register 2 2.8.2
50, 0x32 DIAG3 Diagnostics Register 3 2.8.2

51—255, 0x33—0x0FF (Reserved) — —

(continued)

Register

Mnemonic

(continued)

Description

Refer to

Section

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2.1 Register/Memory Maps

2.1.4 Control Register Memory Space

This section is a summary of the register functions. The
reader is encouraged to read through the rest of this
specification to learn the details of the individual regis­ters and their interactions with the overall architecture.

Table 12. CKM: Clocks, Main Clock Selection, 0x00

Bit Description

7 Phase Alignment Enable
6 Phase Alignment Select
5 Compatibility Clock Direction
4 Input Clock Invert
3 Input Clock Select, MSB
2 Input Clock Select
1 Input Clock Select
0 Input Clock Select, LSB

Table 13. CKN: Clocks, NETREF Selections, 0x01

Bit Description

7 Output Enable
6 I/O Select
5 Bypass Select
4 Input Clock Invert
3 Input Clock Select, MSB
2 Input Clock Select
1 Input Clock Select
0 Input Clock Select, LSB

Table 14. CKP: Clocks, Programmable Outputs,

0x02

Bit Description

7 TCLK Select, MSB
6 TCLK Select
5 TCLK Select, LSB
4 CT_C8 Pins, Input Type Select
3 CT_C8A Output Enable
2 CT_C8B Output Enable
1 CT_C8 Pins, Output Type Select
0 (Reserved)

(continued)

(continued)

Table 15. CKR: Clocks, Resource Selection, 0x03

Bit Description

7 Resource Select, MSB
6 Resource Select, LSB
5 PLL #1 Bypass
4 PLL #1 Rate Select
3 PLL #2 Bypass
2 PLL #2 Rate Select
1 SCLK Output Select, MSB
0 SCLK Output Select, LSB

Table 16. CKS: Clocks, Secondary (Fallback)

Selection, 0x04

Bit Description

7 Secondary Resource Select, MSB
6 Secondary Resource Select, LSB
5 Fallback Type Select, MSB
4 Fallback Type Select, LSB
3 Fallback, Force Selection of Secondary Input
2 Secondary Input Clock Select, MSB
1 Secondary Input Clock Select
0 Secondary Input Clock Select, LSB

Table 17. CK32: Clocks, Locals 3 and 2, 0x05

Bit Description

7 Local Clock 3 Select, MSB
6 Local Clock 3 Select
5 Local Clock 3 Select
4 Local Clock 3 Select, LSB
3 Local Clock 2 Select, MSB
2 Local Clock 2 Select
1 Local Clock 2 Select
0 Local Clock 2 Select, LSB

Table 18. CK10: Clocks, Locals 1 and 0, 0x06

Bit Description

7 Local Clock 1 Select, MSB
6 Local Clock 1 Select
5 Local Clock 1 Select
4 Local Clock 1 Select, LSB
3 Local Clock 0 Select, MSB
2 Local Clock 0 Select
1 Local Clock 0 Select
0 Local Clock 0 Select, LSB

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2.1 Register/Memory Maps

2.1.4 Control Register Memory Space

Table 19. CKMD: Clocks, Main Divider; CKND:

Clocks, NETREF Divider; CKRD: Clocks,
Resource Divider, 0x07, 0x08, 0x09

Bit Description

7 Divide Value, MSB
6 Divide Value
5 Divide Value
4 Divide Value
3 Divide Value
2 Divide Value
1 Divide Value
0 Divide Value, LSB

Table 20. LBS: Local Stream Control, 0x0C

Bit Description

7 Parallel/Serial Select, MSB
6 Parallel/Serial Select, LSB
5 Local Group A Rate Select, MSB
4 Local Group A Rate Select, LSB
3 Local Group B Rate Select, MSB
2 Local Group B Rate Select, LSB
1 Local Group C Rate Select, MSB
0 Local Group C Rate Select, LSB

Table 21. CON: Connection Delay Type, 0x0E

Bit Description

7 Reserved
6 Reserved
5 Reserved
4 Reserved
3 Reserved
2 Reserved
1 Disabled Connection-by-Connection Delay

Setting

0 Enable Linear Delay

(continued)

(continued)

Table 22. HSL: H-Bus Stream Control, Low Byte,

0x10

Bit Description

7 H-Bus Group D Rate Select, MSB
6 H-Bus Group D Rate Select, LSB
5 H-Bus Group C Rate Select, MSB
4 H-Bus Group C Rate Select, LSB
3 H-Bus Group B Rate Select, MSB
2 H-Bus Group B Rate Select, LSB
1 H-Bus Group A Rate Select, MSB
0 H-Bus Group A Rate Select, LSB

Table 23. HSH: H-Bus Stream Control, High Byte,

0x11

Bit Description

7 H-Bus Group H Rate Select, MSB
6 H-Bus Group H Rate Select, LSB
5 H-Bus Group G Rate Select, MSB
4 H-Bus Group G Rate Select, LSB
3 H-Bus Group F Rate Select, MSB
2 H-Bus Group F Rate Select, LSB
1 H-Bus Group E Rate Select, MSB
0 H-Bus Group E Rate Select, LSB

Table 24. GPR: General-Purpose I/O Register, 0x18

Bit Description

7 General-Purpose I/O, MSB
6 General-Purpose I/O
5 General-Purpose I/O
4 General-Purpose I/O
3 General-Purpose I/O
2 General-Purpose I/O
1 General-Purpose I/O
0 General-Purpose I/O, LSB

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2.1 Register/Memory Maps

2.1.4 Control Register Memory Space

Table 25. FRLA: Frame Group A, Start Address

Low, 0x20

Bit Description

7 Start Address, Bit 7, or Programmed Output,

Bit 7

6 Start Address, Bit 6, or Programmed Output,

Bit 6

5 Start Address, Bit 5, or Programmed Output,

Bit 5

4 Start Address, Bit 4, or Programmed Output,

Bit 4

3 Start Address, Bit 3, or Programmed Output,

Bit 3

2 Start Address, Bit 2, or Programmed Output,

Bit 2

1 Start Address, Bit 1, or Programmed Output,

Bit 1

0 Start Address, LSB, or Programmed Output,

Bit 0

T ab le 26. FRHA: Frame Group A, High Address and

Control, 0x21

Bit Description

7 Rate Select, MSB
6 Rate Select, LSB
5 Pulse Width Select, MSB
4 Pulse Width Select, LSB
3 Frame Invert, or Programmed Output, Bit 11
2 Start Address, MSB, or Programmed Output,

Bit 10

1 Start Address, Bit 9, or Programmed Output,

Bit 9

0 Start Address, Bit 8, or Programmed Output,

Bit 8

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(continued)

Table 27. FRLB: Frame Group B, Start Address

Low, 0x22

Bit Description

7 Start Address, Bit 7
6 Start Address, Bit 6
5 Start Address, Bit 5
4 Start Address, Bit 4
3 Start Address, Bit 3
2 Start Address, Bit 2
1 Start Address, Bit 1
0 Start Address, LSB

T able 28. FRHB: Frame Group B, High Address and

Control, 0x23

Bit Description

7 Rate Select, MSB
6 Rate Select, LSB
5 Pulse Width Select, MSB
4 Pulse Width Select, LSB
3 Frame Inversion Select
2 Start Address, MSB
1 Start Address, Bit 9
0 Start Address, Bit 8

Table 29. FRPL: Frame Group B, Programmed

Output, Low, 0x24

Bit Description

7 Programmed Output, Bit 7
6 Programmed Output, Bit 6
5 Programmed Output, Bit 5
4 Programmed Output, Bit 4
3 Programmed Output, Bit 3
2 Programmed Output, Bit 2
1 Programmed Output, Bit 1
0 Programmed Output, Bit 0

Table 30. FRPH: Frame Group B, Programmed

Output, High, 0x25

Bit Description

7 Group A Output Pins Select, MSB
6 Group A Output Pins Select, LSB
5 (Reserved, Use 0)
4 Group B Output Pins Select
3 Programmed Output, Bit 11
2 Programmed Output, Bit 10
1 Programmed Output, Bit 9
0 Programmed Output, Bit 8

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2.1.4 Control Register Memory Space

Table 31. CLKERR1: Clock Error Register, Error

Indicator, 0x28

Bit Description

7 C8A or Frame A Error
6 C8B or Frame B Error
5 FR_COMPn Error
4 C16+ or C16– Error
3 C4n or C2 Error
2

SCLKX2

1 SCLK Error
0NETREF Error

Table 32. CLKERR2: Clock Error Register, Current

Bit Description

7 C8A or Frame A Fault Status
6 C8B or Frame B Fault Status
5 FR_COMPn Fault Status
4 C16+ or C16– Fault Status
3 C4n or C2 Fault Status
2

SCLKX2

1 SCLK Fault Status
0 NETREF Fault Status

Table 33. SYSERR: System Error Register, 0x2A

Bit Description

7 Even CAM Underflow Error (No Match)
6 Odd CAM Underflow Error (No Match)
5 Local CAM Underflow Error (No Match)
4 Even CAM Overflow or No-Match Error
3 Odd CAM Overflow or No-Match Error
2 Local CAM Overflow or No-Match Error
1 (Reserved)
0 Fallback Enable Indicator

Error

Status, 0x29

Fault Status

(continued)

(continued)

Table 34. CKW: Clock Error/Watchdog Masking

Register, 0x2B

Bit Description

7 C8A and Frame A Error Mask
6 C8B and Frame B Error Mask
5 FR_COMPn Error Mask
4 C16+ and C16– Error Mask
3 C4n and C2 Error Mask
2

SCLKX2

1 SCLK Error Mask
0 NETREF Error Mask

Table 35. DIAG1: Diagnostics Register 1, 0x30

Bit Description

7 Frame Group A Output Select, MSB
6 Frame Group A Output Select, LSB
5 Frame Group B Output Select, MSB
4 Frame Group B Output Select, LSB
3 Memory Fill Enable
2 Memory Fill Pattern Select, MSB
1 Memory Fill Pattern Select, LSB
0 Memory Fill Status Bit (Read Only)

Table 36. DIAG2: Diagnostics Register 2, 0x31

Bit Description

7 Frame Groups Cycle Test Enable
6 Break State Counter into Subsections
5 Bypass Internal Frame with FR_COMPn
4 (Reserved)
3 Enable State Counter Parallel Load
2 Parallel Load Value of State Counter, MSB
1 Parallel Load Value of State Counter, Bit 9
0 Parallel Load Value of State Counter, Bit 8

Table 37. DIAG3: Diagnostics Register 3, 0x32

Bit Description

7 Parallel Load Value of State Counter, Bit 7
6 Parallel Load Value of State Counter, Bit 6
5 Parallel Load Value of State Counter, Bit 5
4 Parallel Load Value of State Counter, Bit 4
3 Parallel Load Value of State Counter, Bit 3
2 Parallel Load Value of State Counter, Bit 2
1 Parallel Load Value of State Counter, Bit 1
0 Parallel Load Value of State Counter, LSB

Error Mask

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2.2 Local Bus Section

Figure 4 shows the local bus section function diagram.

Note:

XCS is a pseudo serial stream, read out from the connection memory on each memory access. It is read out
directly, i.e., not passing through any parallel/serial converters or holding registers, so it precedes the connection
associated with it by one time slot.

Routing and MUXing for the H-Bus section is included since the H-Bus requires access to the converters
for local bus-to-H-Bus or H-Bus-to-local bus transfers (the H-Bus is discussed in Section 2.3 H-Bus Sec­tion).

FROM CAM

LOCAL STREAM

INPUTS

SERIAL

PARALLEL

INTERNAL

ADDRESS

BUS

TO

(S/P)

8

11

ADDRESS
BUFFER &

11

DECODER

(AMR) + (LAR)

ADDRESS

11

BUFFER &
DECODER

S/P

BYPASS

TO CAM

10

10

8

DATA BUFFER-

REGISTER

8

(1024 LOCATIONS

x BITS) x 2

DATA

MEMORY

(PATTERN MODE)

CTL BITS

CONNECTION

BUFFER-

REGISTER

1024 LOCATIONS

x 15 bits

CONNECTION

MEMORY

8

INTERNAL
DATA BUS

CAM-

8

LOCAL

SELECT

EACH LOCATION:

STREAM = 4 bits

TIME SLOT = 7 bits

TIME-SLOT ENABLE BIT

CONSTANT/MIN DELAY BIT

PATTERN MODE BIT

XCS BIT

PARALLEL

TO

SERIAL

(P/S)

P/S

BYPASS

LOCAL STREAM

XCS

OUTPUTS

5-6102F

Figure 4. Local Bus Section Function

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2.2 Local Bus Section

(continued)

(continued)

2.2.1 Constant Frame Delay and Minimum Delay Connections

The local bus section contains the local connection memory and the double-buffered local data memory. Collec­tively, the connection memory and data memory are referred to as local memory since it is used for implementing
local-to-local switching only. Operation is similar to other time-slot interchangers. Data is written into the memory in
a fixed order and then read out according to the indirect addresses held in the connection memory. If any of the
connections on the T8100 are operating in constant frame delay (also call ed constant delay) mode, then the output
data is accessed from a second block of data memory. The input data will not be output until the next frame bound­ary has been crossed and the memory blocks have swapped functions. Figure 5 shows an exampl e of a set of con­nections which create the delay types referred to as minimum delay and constant delay.

WRITE N

1020
1021
1022
1023

0
1
2
3

FRAME N DATA

DATA BLOCK 0

READ N

MINIMUM DELAY

CONNECTION

FRAME N

FRAME N – 1 DATA

0
1
2
3

1020
1021
1022
1023

DATA BLOCK 1

READ N – 1

CONSTANT DELAY

CONNECTION

1020
1021
1022
1023

0
1
2
3

FRAME N DATA

DATA BLOCK 0

READ N

CONSTANT DELAY

CONNECTION

FRAME N + 1

WRITE N + 1

FRAME N – 1 DATA

0
1
2
3

1020
1021
1022
1023

DATA BLOCK 1

Figure 5. Local Bus Memory Connection Modes

READ N + 1

MINIMUM DELAY

CONNECTION

5-6103F

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2.2 Local Bus Section

2.2.2 Serial and Parallel

Nominally, the memory will be accessed by serial data
streams which will require conversion of serial-to-paral­lel (S/P) for write accesses and parallel-to-serial (P/S)
for read accesses . Since the l ocal memory can hav e up
to 16 serial inputs and 16 serial outputs, there will be a
maximum of 16 S/P converters and 16 P/S converters
operating simultaneously. If desired, eight of the S/P
converters, local inputs 0—7, can be bypassed for a
direct parallel write to the data memory. Likewise, eight
of the P/S converters, local outputs 0—7, can be
bypassed for a direct parallel read of the data memory.
Unused S/P or P/S converters are nonfunctional in
these modes.

Note:

The normal serial-to-serial local streaming is not
available simultaneously with any of the parallel
modes.

2.2.3 Data Rates and Time-Slot Allocation

At its maximum, the T8100 will be able to process
1024 nonblocking-to-local connections. The data rate

8.192 Mbits/s corresponds to 128 time slots,

4.096 Mbits/s corresponds to 64 time slots, and

2.048 Mbits/s corresponds to 32 time slots. Since dif­ferent data rates require different amounts of memory,
the local memory can be filled in a number of ways. A
nonblocking s witch permits any ti me slot on any stream
to be switched to another time slot on any stream in
any direction.

(continued)

The local streams are arranged in three groups: A, B,
and C. Group A corresponds to the local data pins 0—
7, group B with local data pins 8—11, and g roup C with
local data pins 12—15. The groups ma y be oper ated at
any of the three data rates: 2.048 Mbits/s,

4.096 Mbits/s, or 8.192 Mbits/s; however, group B is
activated only when group A is operating below

8.192 Mbits/s. Likewise, group C is activated when
group B is operating below 8.192 Mbits/s.

Note:

In order to efficiently fill the memory, the mem­ory locations are read or filled in the same order
regardless of their activation or rate.

The streams are scanned in intervals equal to

8.192 Mbits/s time slots: first g roup A from 0 through 7,
then group B from 8 through 11, then group C from 12
through 15. If a group is active, the data is input from or
output to the streams in that group. If a group is operat­ing below 8.192 Mbits/s and has already been scanned
(at the 8.192 Mbits/s rate), then the data transf er opera­tion is ignored.

For T8100 addressing, the user directly provides
stream and time-slot information. The T8100 will map
this into the physical memory, regardless of which
stream groups are active or at what rate. While this
makes programming simpler, it makes the internal
operation more difficult to understand. Several dia­grams are required to illustrate how the memory utiliza­tion works.

Unassigned time slots in the local output section are 3­stated. Therefore, multiple lines can be connected
together.

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(continued)

(continued)

(continued)

Figure 6 below shows the overall structure of the local memory:

Note:

Both the connection and two data memories are arranged in four blocks of 256 locations each
(i.e., 4 x [4 x 64]).

The arrangement is important to establishing a memory fill pattern which supports all of the various groups and
rates. The rows of each memory, which are split into four groups of 4, correspond to the 16 streams. The columns
correspond to 64 time-slot addresses.

LOCATION 0

4 4 4 4

64

CONNECTION

MEMORY

LOCATION 15

EACH (SMALL) SQUARE

REPRESENTS 15 bits

OF CONNECTION

INFORMATION

64

4 4 4 4

DATA MEMORY 0
DATA MEMORY 1

EACH (SMALL)

SQUARE

REPRESENTS 1

byte OF DATA

TO/FROM

STREAMS

LOCAL

LOCATION 1023

5-6104F

Figure 6. Local Streams, Memory Structure

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(continued)

(continued)

(continued)

Examples of how the memory is filled are found in Figure 7.

Note:

Again, the user needs only to provide stream and time-slot addresses; the T8100 will generate the internal
memory addresses.

Both the connection and data memories are filled using the same algorithm. In the case where group C is running
at 8.192 Mbits/s, group B is at 4.096 Mbits/s (or 2.048 Mbits/s), and group A is at 2.048 Mbits/s, then an additional
virtual memory space of 4 x 64 locations is created by the T8100 from unused locations in other parts of the mem­ory.

STREAM

0—3

TIME SLOT 0
TIME SLOT 2
TIME SLOT 4

STREAM

4—7

STREAM

0—3

TIME SLOT 1
TIME SLOT 3
TIME SLOT 5

STREAM

4—7

STREAM

0—3

TIME SLOT 0
TIME SLOT 1
TIME SLOT 2

STREAM

4—7

STREAM

8—11

TIME SLOT 0
TIME SLOT 2
TIME SLOT

STREAM

TIME SLOT 1
TIME SLOT 3

4

TIME SLOT 5

8—11

GROUP A, GROUP A, GROUP A,64 TIME SLOTS 64 TIME SLOTS

EVEN ODD

TIME SLOTS TIME SLOTS

GROUP A AT 8.192 Mbits/s

GROUPS B AND C OFF

Figure 7. Local Memory, Fill Patterns

GROUP

ALL

TIME

SLOTS

GROUP A AT 4.096 Mbits/s
GROUP B AT 8.192 Mbits/s

AND GROUP C OFF

B, EVEN
SLOTS

TIME

GROUP
B, ODD

TIME

SLOTS

5-6105F

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2.2.3 Data Rates and Time-Slot Allocation

STREAM

0—3

TIME SLOT 0
TIME SLOT 1
TIME SLOT 2

GROUP A,64 TIME SLOTS

SLOTS

(continued)

STREAM

4—7

ALL

TIME

STREAM

8—11

TIME SLOT 0
TIME SLOT 1
TIME SLOT 2

GROUP

B,

ALL

TIME

SLOTS

(continued)

STREAM

12—15

TIME SLOT 0
TIME SLOT 1
TIME SLOT 2

GROUP

C,

ALL

TIME

SLOTS

(continued)

STREAM

STREAM

0—3

(USED FOR GROUP C)

TIME SLOT 0

TIME SLOT 1

GROUP A,64 TIME SLOTS

ALL

TIME

SLOTS

4—7

STREAM

8—11

TIME SLOT 0
TIME SLOT 1
TIME SLOT 2

GROUP

B,

ALL

TIME

SLOTS

STREAM

12—15

TIME SLOT 0
TIME SLOT 2
TIME SLOT 4

GROUP

C,

EVEN

TIME

SLOTS

STREAM

12—15

TIME SLOT 1
TIME SLOT 3
TIME SLOT 5

GROUP C, ODD (VIRTUAL) TIME SLOTS

GROUP A AT 4.096 Mb its/ s
GROUP B AT 4.096 Mb its/ s
GROUP C AT 4.096 Mbits/s

Figure 7. Local Memory, Fill Patterns

(continued)

GROUP A AT 2.048 Mbits /s
GROUP B AT 4.096 Mbits /s
GROUP C AT 8.192 Mbits/s

5-6106F

In any of the parallel modes (S/P, P/S, P/P), the local memories treat parallel data as a series of sequential time
slots (i.e., all one stream): 8.192 Mbits/s corresponds to 1024 time slots, 4.096 Mbits/s corresponds to 512 time
slots, and 2.048 Mbits/s corresponds to 256 time slots. The memory locations are scanned in order from 0 to 1023
at 8.192 Mbits/s, even locations are scanned at 4.096 Mbits/s (odd locations are skipped), and at 2.048 Mbits/s,
every second even location is scanned.

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2.2.4 LBS: Local Stream Control, 0x0C

The normal mode of operation for local streams is serial in/serial out, but parallel modes are available. Modes and
data rates are controlled by register LBS. The mapping is s ho wn belo w. See the preceding pages for a full descrip­tion.

Table 38. LBS: Local Stream Control, 0x0C

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

LBS — P/S SGa SGb SGc

Symbol Bit Name/Description

P/S 7—6 P/S = 00. Serial In/Serial Out.

The SGa bits control the group A pins, SGb bits control the group B pins, and SGc bits control the

group C pins. As serial streams, input and output rates within the same group are constrained to

be identical so both inputs and outputs share the same 2 bits for programming.
The SGb bits are enabled when SGa ≠ 11.
The SGc bits are enabled when SGb ≠ 11.

P/S = 01. Serial In/Parallel Out.

SGa sets input (serial) rate using the rate definition within this table.
SGb is reserved.
SGc sets the output (parallel) rate using the rate definition within this table.

P/S = 10. Parallel In/Serial Out.

SGa sets input (parallel) rate.
SGb is reserved.
SGc sets output (serial) rate.

P/S = 11. Parallel In/Parallel Out.

SGa sets input (parallel) rate.
SGb is reserved.
SGc sets output (parallel) rate.

SGa 5—4 SGa = 00, 3-state.

SGa = 01, 2.048 Mbits/s.
SGa = 10, 4.096 Mbits/s.
SGa = 11, 8.192 Mbits/s.

SGb 3—2 SGb = 00, 3-state.

SGb = 01, 2.048 Mbits/s.
SGb = 10, 4.096 Mbits/s.
SGb = 11, 8.192 Mbits/s.

SGc 1—0 SGc = 00, 3-state.

SGc = 01, 2.048 Mbits/s.
SGc = 10, 4.096 Mbits/s.
SGc = 11, 8.192 Mbits/s.

There are no additional registers required for addressing the local memory other than the main address registers
(discussed in Section 2.1 Register/Memory Maps). The data and connection memory locations can be queried for
their contents by indirect reads through the main address registers; howe ver, the memory locations are referred to
by the stream and time-slot designators, rather than physical address locations, to simplify the queries.

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(continued)

2.2.5 State Counter Operation

All operations are synchronized to the master state counter. The state counter is in turn synchronized to the inter­nal frame signal and driven by an internal 65.536 MHz clock. In normal operation, the internal frame and clock are
synchronized to either the H-Bus or trunks (see Section 2.4 Clocking Section, for a more detailed explanation of
clocking options). The local memory states are illustrated in Figure 8. The state counter is a modulo-8192 counter
(7 bits for time slot, 4 bits for stream, 2 bits for state function) which can also be reset and loaded with other values
for diagnostic purposes (as described in Section 2.8 Testing and Diagnostics). The H-Bus memories are also refer­enced to this state counter so that T8100 maintains synchronizati on with the H-Bus to ensure proper acc ess to the
bus as well as ensure synchronization between the H-Bus and local memory structures. The H-Bus memories are
discussed in Section 2.3 H-Bus Section.

L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12

976 ns

61 ns

CONNECTION

MEMORY

H6 READ

MICROPROCESSOR

L13

L14 L15

DATA

SRAM

CLOCK

H6 WRITE H6 READ

MICRO-

PRO-

CESSOR CESSOR

15.25 ns

MICRO-

PRO-

Figure 8. Simplified Local Memory State Timing, 65.536 MHz Clock

5-6107F

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(continued)

2.3 H-Bus Sec tio n

2.3.1 Memory Architecture

To access the H-Bus, the T8100 uses a new twist
on an existing approach to accessing large address
spaces: the data is stored in an independent double­buffered SRAM which acts like the local data memory,
but the connection information for the H-Bus is held in
three 256 location CAMs. Two CAMs are used for two
groups of 16 H-Bus streams each, and one CAM for all
16 local input/output pairs. Each CAM compares
16 streams for read and write and allows access time
to the host microprocessor for updates to the connec­tions. Thus, each stream is allotted three operations
per 976 ns time slot, so there are a maximum of 48
accesses per CAM per time slot. The CAMs must oper­ate for at least 20.34 ns/access* or faster . The selected
technology operates at 13 ns/access maximum, so an
internal clock speed of 15.26 ns (65.536 MHz) is used.

For the follo wing discussions, the reader should ref er to
Figure 9. The combined comparison plus retrieval
operations take 2 CAM cycles, leaving little time for
microprocessor updates. To circumvent this, a separate
SRAM (actually, a register file) is tied to each CAM.
Each entry of this register file is associated with an
entry in the CAM on a location-by-location basis. (For

example, ph y sical address 0xA7 in the CAM is coupled
with physical address 0xA7 of the register file.) The
CAMs will have only the comparand field for stream
and time-slot addresses, and the associated register
files will hold the data field, which is comprised of a tag
(an indirect pointer to the double-buffered data SRAM)
and some control bits. Using the associated SRAM
allows the operations to be pipelined so that the data
retrieval occurs while the CAMs are doing the next
comparison. The SRAM is double-buffered to permit
constant delay or minimum delay on a connection-by­connection basis, as described in Section 2.2.1 Con­stant Frame Delay and Minimum Delay Connections
and as illustrated in Figure 5.

* The H-Bus presents a unique set of problems. A full nonblocking,

double-buffered switch of 5120 locations has significant barriers in
size and in control of memory access time. Further, the traffic
between the local bus and H-Bus is generally limited to a small
number of time slots at any given moment (120 full duplex is typical,
although we are permitting 128 duplex or 256 simplex connections),
but the requirement to access any time slot out of the full range of
5120 locations remains. To solve this, content addressable memo­ries (CAM) are utilized. They provide access to the full 5120 loca­tions through an encoded width (13 bits), but require a depth equal
to the maximum number of connections required (256).

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2 Architecture and Functional Description

2.3 H-Bus Sec tio n

2.3.1 Memory Architecture

H-BUS:

EVEN STREAMS

A12 = 0

A0 = 0

H-BUS:

ODD STREAMS

1 = 01

A12 = 0

A0 = 1

LOCAL 0—15

A12.A11 = 11

(continued)

(continued)

ADDRESS TAG

AA

…………………

11 1

CAM-E CE-SRAM

ADDRESS TAG

AA

…………………

11 1

CAM-O CO-SRAM

ADDRESS TAG

AA

…………………

10 0

CAM-L CL-SRAM

TT
70

0

……………………

255

TT
7

0

……………………

255

TT
7

0

……………………

255

………………

………………

………………

0

0

(continued)

READ/WRITE
VALID ENTRY MARKER

PATTERN/NORMAL
DATA SRAM SELECT

PATTERN MODE

OUTPUTS TAG

TO H-BUS

LOCAL I/O

H-BUS

READ/WRITE AND

SRAM SELECT

DD

………………

70

DATA BUFFER 0 DATA BUFFER 1

THIS IS THE H-BUS DATA MEMORY:

EFFECTIVE ACCESS TIME < 10 ns

DD

………………

70

DATA SRAM

0

……………………

255

THIS IS THE H-BUS CONNECTION MEMORY:

3 CAMS, MAXIMUM OF 48 ACCESSES PER 976 ns

TIME SLOT, REQUIRES <20 ns/ACCESS

PATTERN MODE

OUTPUTS TAG
TO LOCAL OUT

5-6108F

Figure 9. CAM Architecture

The maximum number of connections is set by the number of locations in the data SRAM and the CAMs. In this
implementation, 256 simplex connections are permitted. Since one connection requires two CAM entries pointing
to a common data location, the maximum number of connections could be reduced to 128 simplex if all connection
entries reside within only one CAM. The maximum number of connections is increased above 256 simplex if the
connection type is broadcast, i.e., from one to many.

30 Lucent Technologies Inc.

Preliminary Data Sheet
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2.3 H-Bus Sec tio n

2.3.2 CAM Operation and Commands

The three CAMs operate in parallel. Each CAM’s com­parand field is compared with the state counter (Sec­tion 2.2.5 State Counter Operation) which holds the
existing stream and time-slot value*. If there is a match,
the CAM issues a hit. If there is more than one match,
then it is considered a multiple hit. Likewise, no match
is a miss. As a part of the state counter, a bit is toggled
for read/write. The read/write bit is stored in the CAM,
so it becomes part of the value to be compared. If the
comparison for a write yields a hit, then there is a
request for write access to the data memory for the
incoming data from the H-Bus. If the comparison for a
read yields a hit, then there is a request for a read
access from the data memory for outgoing data to the
H-Bus. Any multiple hit withi n one CAM b loc k is treated
as a controlled error although it is not reported. The
action taken is to acknowledge the hit which corre­sponds to the lowest physical address of the CAM. A
miss implies no action. A multiple hit is assigned to be
more than one valid connection. These are prioritized

(continued)

such that the match with the lowest physical address
(i.e., closest to CAM location 0x0) is the address whi ch
is processed. Thus, errors are handled in a controlled
manner. Multiple hits can occur because multiple loca­tions are assigned to the same time slot. Bad software
can cause this problem. A controlled error has no
impact on performance, and the CAM contents are not
changed as a result of the error. The data SRAMs are
actually dual-port register files which will process both
writes and reads on each clock cycle of the clock. The
T8100 can process a read and write request from each
CAM and two microprocessor requests during the time
of one address comparison. Due to the fixed order of
operations, the data SRAM cannot overflow or under­flow like the CAMs. The timing is shown in Figure 10.

* As mentioned in Section 2.2.5 State Counter Operation, for each

stream and time-slot value, the state counter goes through four
functional states for each stream and time slot. These states are
used to synchronize the CAMs, pipeline register files, data SRAMs,
and microprocessor accesses just as they are used to synchronize
local memory operations and the frame groups. (Microprocessor
accesses to the memories are initiated asynchronously, though the
actual microprocessor cycles are synchronous.)

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2.3 H-Bus Sec tio n

2.3.2 CAM Operation and Commands

H0 H2 H4 H6 H8 H10 H12 H14 H16 H18 H20 H22 H24
H1L0H3L1H5L2H7L3H9L4H11L5H13L6H15L7H17L8H19L9H21

CAM-E

CAM-O

CAM-L

(continued)

(continued)

61 ns

H12 WRITE H12 READ

H13

WRITE

L6 WRITE L6 READ

MICRO-

PRO-

CESSOR

MICRO-

PRO-

MICRO-

PRO-

CESSOR

H13 READ

(continued)

976 ns

MICRO-

PRO-

CESSOR

MICRO-

PRO-

CESSORCESSOR

MICRO-

PRO-

CESSOR

L10

H23
L11

H25

L12

H26
H27

L13

H28 H30
H29

H31

L14

L15

C0-SRAM

C1-SRAM

CL-SRAM

DATA SRAM WRITES

DATA SRAM READS

CLOCK

H12 WRITE H12 READ

H13

WRITE

L6 WRITE L6 READ

15.25 ns

MICRO-

PRO-

CESSOR

MICRO-

PRO-

CESSOR

MICRO-

PRO-

CESSOR

EVEN (H12) LOCAL (L6)

MICRO-

PRO-

CESSOR

H13 READ

ODD (H13)

EVEN (H12)

Figure 10. Simplified H-Bus State Timing, 65.536 MHz Clock

MICRO-

PRO-

CESSOR

MICRO-

PRO-

CESSOR

MICRO-

PRO-

CESSOR

ODD (H13)

MICRO-

PRO-

CESSOR

LOCAL (L6)

5-6109F

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2.3 H-Bus Sec tio n

2.3.2 CAM Operation and Commands

A number of commands are available to control the
CAMs. Connections can be made or broken, entry data
can be searched for, individual locations may be read
or cleared, or the CAMs can be reset. The address
mode register (AMR) (see Section 2.1 Register/Mem­ory Maps) is used to issue the CAM control commands.
Some commands require the use of the lower address
register (LAR), and some use the IDR as a transfer reg­ister.

The tags in each CAM’s associated register file refer­ence the storage location of the data being transferred,
so each CAM/tag location also has control information.
The three control bits are read-to/write-from data
SRAM (i.e., a direction bit, located in the CAM and
used during the comparison operations), a pattern
mode enable, which bypasses the data SRAM and out­puts the tag directly into the specified time slot for
writes to the bus, and an SRAM buffer select that con­trols the minimum delay or constant delay select,
equivalent to the local memory’s selection of minimum
or constant delay.

In addition, the CAM carries a valid entry bit. This is an
identifier for the status of the CAM (and corresponding
register file) location. If the bit is low, as all validity bits
are after a reset, then the location is available to be
written into. When data is written into a location, then
this bit is set, indicating that this is a valid entry. If spe­cific data is no longer valid, such as when a connection
is broken, then the bit is cleared.

(continued)

(continued)

The CAM commands make use of either one or two
cycles. The two cycles are described pictorially in Fig­ure 11. The reader will note that matching and retriev al
are actually separate cycles. The need for two cycles
accounts for the requirement of the pipeline register
files.

Detailed descriptions of the commands follow:
The basic make connection command is referred to as

MKCn, where n is the CAM designator*. The MKCn
uses two CAM cycles: first, the CAM is searched to
determine where to find the next free location (as deter­mined by the val idity bits), and during the second c ycle,
the next empty location is written into. The MKCn com­mand uses holding registers which convey the connec­tion information to the CAM and its associated register
file. The three holding registers contain the lower con­nection address (i.e., time slot), the upper connection
address (stream plus control bits), and the tag. An
attempt to write to a full CAM (all 256 locations fully
occupied) results in an overflow error flagged through
the system error register, SYSERR (see Section 2.6
Error Registers).

Note:

A single MKCn command only speci fies one half
of a connection. The MKCn specifies the con­nection address and a pointer to the data mem­ory, but a second connection address and
pointer to the same data memory location must
also be provided for a complete connection.

* The H-Bus CAM covering the 16 even-numbered H-Bus streams is

designated E, the H-Bus CAM covering the 16 odd-numbered H­Bus streams is designated O, and the CAM that services the 16
local stream pairs is designated L.

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2 Architecture and Functional Description

2.3 H-Bus Sec tio n

2.3.2 CAM Operation and Commands

CONTROLS,

e.g., SEARCH

FOR EMPTY

(continued)

APPLY COMPARAND,

i.e., STREAM + TIME SLOT

ONE CYCLE CAM

OPERATION:

MATCH COMPARAND

GET STATUS

APPLY PHYSICAL LOCATION TO

CAM, i.e., LOCATION 0—255

(continued)

PHYSICAL LOCATION IN CAM,

FLAGS

OR

APPLY COMPARAND,

i.e., STREAM + TIME SLOT

PHYSICAL LOCATION

(continued)

IDENTIFY HIT OR EMP TY
(FLAGS) THEN RETRIEVE

i.e., LOCATION 0—255

RETRIEVE

ONE CYCLE CAM

OPERATION:

GET COMPARAND OR

TAG, OR

CHANGE STATUS

RETRIEVE COMPARAND O R DATA,

i.e., GET STREAM + TIME SLOT FROM CAM

OR GET TAG FROM PIPELINE REGISTER FILE

FLAGSCONTROLS

CONTROLS FLAGS

PHYSICAL PHYSICAL
LOCATION LOCATION

i.e., GET TAG FROM PIPELINE REGISTER FILE

TWO CYCLE CAM

OPERATIONS:

IDENTIFY COMPARAND

AND RETRIEVE TAG

IDENTIFY COMPARAND

AND CHANGE STATUS

OR

RETRIEVE DATA,

OUT IN

Figure 11. Illustration of CAM Cycles

5-6110F

34 Lucent Technologies Inc.

Preliminary Data Sheet
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2 Architecture and Functional Descrip­tion

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2.3 H-Bus Sec tio n

2.3.2 CAM Operation and Commands

If the user determines that a stream/time slot is no
longer valid, then the validity bit may be cleared by pre­senting the connection address to the CAM and by
using the BKCn, break connection, command. The
connection that the user intends to break, which con­sists of the time slot, and the stream plus control bits,
but not the tag, is transferred to the holding registers
prior to issuing this command. This is a two-cycle com­mand: during the first cycle, the connection address is
presented to the CAM to identify which physical loca­tion holds that connection address, and then, in the
second cycle, the val idity bit is cleared for the identified
physical location. If there is a miss, it flags a no-match
error through the underflow bit in SYSERR.

Note:

A complete connection break requires two
BKCn commands, one for each half of the con­nection, as with the MKCn command.

The clear location command, CLLn, is a one-cycle
command. The LAR contains the physical address (i.e.,
the physical CAM location) to be cleared. When it is
presented to the CAM, the validity bit is cleared, return­ing the location to an empty status (i.e., it becomes
available for new make connection commands). The
CLLn can also be regarded as the second cycle of a
break connection command. CLLn is valuable if se v eral
outputs are driven from a common input (broadcast)
and the user wishes to break one of the output connec­tions, but leave the others intact. When the physical
location in the CAM is identified, either by software
tracking or by use of the find entry command (later in
this section), then the CLLn can be issued.

(continued)

(continued)

If the user wishes to poll the CAM for its contents, then
the RDCn or read CAM command can be used to
query a particular location (0—255) in a specific block
using the LAR for the l ocation address . The contents of
the CAM and tag location are transferred to the holding
registers, and then the time slot, stream plus control,
and tag are returned (in sequence) from three consec­utive IDR reads. The actual RDCn operation is one­cycle.

The converse of the RDCn is the FENn, or find entry
command. It can be thought of as the first cycle of a
BKCn command. Only time slot and stream plus con­trol bits are necessary for identifying the location. The
tag is not needed. The value returned to the IDR is the
physical location of the entry in the CAM block, if it is
found. If the entry is not found, then the underflow error
bit in the SYSERR register will be set. FENn is a one­cycle command.

RSCn is the reset CAM command, and this renders all
locations in one CAM block invalid. This can be consid­ered a CLLn for all locations in the CAM. Two special
resets are the RCH command, which resets only the
holding registers, and the CI command, which resets
all three CAM blocks and the holding registers. All
resets are one-cycle.

2.3.3 H-Bus Access

There are 32 bidirectional pins available for accessing
the H-Bus. The direction of the pins is selected by the
CAM read and write bits. Data rates for the pins are
selected in accordance with the H.100/H.110 specifica­tions. Unassigned time slots on the H-b us are 3-stated.
Details about rate selection are provided below. Two
bits of the 13-bit address are used to select the CAM
block as indicated in Figure 9. The remaining
11 bits plus a read/write bit form a comparand that is
stored in a CAM location.

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2.3 H-Bus Sec tio n

2.3.4 L-Bus Access

The input and output of the CAM have the appropriate
links to the local stream pins so that the H-Bus streams
may be routed to and from the local bus streams. The
LBS register (Section 2.2.4 LBS: Local Stream Control,
0x0C) programs the local stream rates even if
accessed by the CAMs. To address the local bus CAM
block, the two most significant address bits of the phys­ical address are set to the appropriate values as
described in Figure 9. The other bits form the com­parand along with a read/write bit. When the CAM is
outputting data to the local bus, it has priority over the
local bus memory. In other words, if both the local bus
and H-Bus access the same local stream and time slot,
the H-Bus data memory will provide the actual data,
not the local connection.

2.3.5 H-Bus Rate Selection and Connection
Address Format

Operating rates are selected in a manner similar to the
local side. Two registers, HSH and HSL, shown below,
define the operation of the 32 streams. Again, SGx
refers to stream groups: HSH holds SGh—SGe where
SGh programs streams 28—31, SGg programs
streams 24—27, SGf programs streams 20—23, and
SGe programs streams 16—19. HSL holds S Gd—SGa
where SGd programs streams 12—15, SGc programs
streams 8—11, SGb programs streams 4—7, and SGa
programs streams 0—3.

SGh SGg SGf SGe
SGd SGc SGb SGa

SGn = 00, 3-state
SGn = 01, 2.048 Mbits/s
SGn = 10, 4.096 Mbits/s
SGn = 11, 8.192 Mbits/s

A quick summary:

(continued)

Thirteen bits are required to cover the 5120 possible
time slots, but the MSB, LSB combination is used to
determine which H-Bus CAM is accessed: even H-Bus
(0, 0), odd H-Bus (0, 1). The local H-Bus is accessed
by selecting the upper 2 MSBs, both equal to 1. The
CAM address can be thought of as following this for­mat:

CAM Select Field Time-Slot Field Stream Field

2 bits 7 bits 4 bits

This format is rate independent. The CAM select field is
part of the address mode register (AMR) for CAM com­mands (Section 2.1.3 Address Mode Register and Sec­tion 2.3.2 CAM Operation and Commands). Program­ming examples f or setting up connections can be f ound
in Section 3.2 Basic Connections.

2.4 Clocking Section

The clocking section performs several functions which
are detailed in the following paragraphs. In general,
when the T8100 is a bus master, it will have one or
more companion devices which provi de the basic clock
extraction and jitter attenuation from a source (such as
a trunk). As a slave, the T8100 can work independently
of, or in conjunction with, ex ternal resources. Examples
of different operating modes are provided in Appendix
A. Refer to Figure 12 for a block diagram of the T8100
clocking section.

When the T8100 is used as a bus master, an input
clock of a tolerance of ±32 ppm is required. This can
come from several sources. For example:

■

±32 ppm crystal tolerance is the suggested value if
either the DPLL is used or fallback to the oscill ator is
enabled while mastering the bus. Otherwise, a crys­tal with a lesser tolerance can be used.

■

If a crystal is not used, a 16.384 MHz (±32 ppm toler­ance or less) signal must be provided to the XTALIN
pin, and XTALOUT should be left unconnected.

■

The L_REF inputs can also be used and must con­form to ±32 ppm in a bus master situation.

The CAMs and the pipeline register files operate as
connection memories. The key CAM operation is bas ed
on 11 bits of stream and time slot plus 1 bit of read/
write in the CAM locations compared against the state
counter which tracks the current stream and time slots
(Section 2.2.5 State Counter Operation). Each H-Bus
CAM is looking for matches on 16 of the 32 H-Bus
streams, and the local CAM is looking for a match on
16 local inputs and 16 local outputs per time slot.

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2.4 Clocking Section

THESE INPUTS

FORM

TRANSCEIVERS

WITH THE

CORRESONDING

OUTPUTS

/CT_FRAME_A
/CT_FRAME_B

/FR_COMP

L_REF0

L_REF7

CT_NETREF

CT_C8_A
CT_C8_B

/C16±

/C4

C2

SCLK

SCLKx2

THESE INPUTS

FORM

TRANSCEIVERS

WITH THE

CORRESPONDING

OUTPUTS

XTALIN

* The path for XTALIN

NETREF
SELECT

FRAME

CLOCK

SEL.

divide-by-4

SEL.

NET-

REF

SEL.

÷ BY 8

CLOCK

SEL.
AND

INPUT
STATE
MACH.

DIVIDE

(continued)

FRAME SYNC

BY 4*

is for fallback only.

TODJAT/GP6 FROMDJAT/GP7

GP6
GP7

DJAT BYPASS

(AND GP6/7 ENABLE)

4 MHz

2 MHz

DPLL

RESOURCE

DIVIDE-BY-N

DIVIDE REGISTER

MAIN

DIVIDE-BY-N

DIVIDE REGISTER

(FALLBACK PAT H* )

PRIREFOUT 4MHzIN 3MHzIN TCLKO

NETREF

DIVIDE-BY-N

DIVIDE REGISTER

CLOCK

RESOURCE

SELECT

(continued)

BIT SLIDER
CONTROLS

INTERNAL CONTROL

CLOCKS AND SYNC

PLL #1 BYPASS

PLL #1

x16

x32

RATE SELECT

PLL #2 BYPASS

PLL #2

x 8

x16

RATE SELECT

NETREF
INT/EXT
SELECT

65.536 MHz

TCLK

SELECT

BIT SLIDER

STATE

MACHINES

MEMORY

CLOCK

DIVIDE

BY 2

EN_NETREF

NETREF

EN_A

C8
FRAME
EN_B

C8

FRAME

COMPATIBILITY
CLOCKS DIRECTION

16.384 MHz

2.048 MHz

4.096 MHz

2.048 MHz

4.096 MHz

8.192 MHz
SCSEL

4.096 MHz

8.192 MHz

FRAME

SEC8K
FRAME

2.048 MHz

4.096 MHz

8.192 MHz

16.384 MHz
DPLL#2 ÷ 2

L_SC CTL

TCLK

ENABLE

CT_NETREF
CT_C8_A
/CT_FRAME_A
CT_C8_B
/CT_FRAME_B

/CT16 ±
C2

/C4

SCLK

SCLK2

/FR_COMP

L_SC0

(1 OF 4

L_SC[1:3]

NOT SHOWN)

5-6111F

Figure 12. Clocking Section

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(continued)

2.4 Clocking Section

2.4.1 Clock and NETREF Selection

The inputs to the T8100 clocking come from three
selectors. The clock selector and frame selector oper­ate from a common set of selection options in register
CKM (see Section 2.4.6 Clock Control Register Defini­tions for register details), where FRAMEA is selected
along with clock C8A and FRAMEB is selected along
with clock C8B. Typically, one of the local references
(LREF[0:7]) will be selected when the T8100 is operat­ing as a master, though the local oscillator is also avail­able. As a slave, the most common selections will be
one of the bus types. Each bus type has a state
machine associated with it for determining the frame
sync. All clock inputs are sampled to check for proper
switching. If the expected clock edge does not occur,
and there is no switching on CT_NETREF f or 125 µs, a
bit corresponding to the errant clock is set in the CLK­ERR register (see Section 2.6 Error Registers f or more
details). NETREF can be created from one of the local
references or from the oscillator independent of the
clock generation.

2.4.2 Dividers and Rate Multipliers

The clock and NETREF selections are routed to divid­ers*. In the case of NETREF, the divider is
usually used to reduce a bit rate clock to 8 kHz,
so the most common divisors will be 1, 193
(1.544 MHz/8 kHz), and 256 (2.048 MHz/8 kHz),
although a full range of values (from 1—256) is possi­ble. F or the cloc k selec tor, the signal will most often be
routed through the main divider when the T8100 is
operating as a master or through the resource divider
when operating as a slave. Both the main and resource
dividers are fully programmable.

(continued)

The ultimate destination for the main or resource
divider is intended to be PLL #1. PLL #1 accepts ei ther
a 2.048 MHz or 4.096 MHz input and will rate multiply
up to 65.536 MHz. The divisor of the main or resource
dividers is chosen in conjunction with the rate select of
the PLL, i.e., a divisor which generates a 4.096 MHz
output and a rate selection of x16, or a divisor which
generates a 2.048 MHz output and a rate selection of
x32. This provides a great deal of flexibility in adapting
to a variety of (external) clock adapters and jitter atten­uators while acting as a master, as well as slaving to
several bus types.

A digital PLL that can rate multiply to either 2.048 MHz
or 4.096 MHz from an 8 kHz source in the absence of
an external clock adapter is also provided. PLL #1 can
be bypassed for diagnostic purposes or if an external
clock adapter is used that provides a high-speed output
(65.536 MHz). The input to the DPLL is for an 8 kHz
signal only.

A second rate multiplier is provided for supporting T1
applications. It is optimized around either a 1.544 MHz
or 3.088 MHz input rate which multiplies to 24.704 MHz
and is then divided down to provide 50% duty cycle
clocks of 12.352 MHz, though the di rect 24.704 MHz i s
availab le as w ell . A b ypass is provided so that an exter­nal clock can be buff ered through the TCLK output. The
internal oscillator or the various outputs derived from
PLL #1 can also be selected for the TCLK output.

* If the A clocks have been selected as the clock source through the

CKM register (described in Section 2.4.6 Clock Control Register
Definitions), then the CT_C8A is the signal sent to the main and
resource dividers; likewise, selecting B clocks results in sending
CT_C8B; the
sends the recovered /C16 (derived from differential inputs); select­ing SC2 sends SCLKX2

MVIP

selection sends /C4; the H-

; and SC4/8 sends SCLK to the dividers.

MVIP

selection

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Preliminary Data Sheet
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2 Architecture and Functional Descrip­tion

(continued)

2.4 Clocking Section

2.4.3 State Machines

The purpose of the state machines is to generate
internal control signals for the remainder of the T8100
circuitry and to provide all bus clocks when operating
as a master. The state machines operate from the

65.536 MHz clock generated by PLL #1, and they are
time referenced to the frame sync derived from the
selected clock and frame inputs. As a master, the time
sync is based on the T8100’s own generated frame.

The dominant internal control signals are a noninverted

32.768 MHz clock, an inv erted 16.384 MHz state clock,
and a noninverted 122 ns wide sync pulse centered
around the beginning of a frame. The memories are
synchronized to the 65.536 MHz clock.

2.4.4 Bit Sliding (Frame Locking)

The T8100 generates its own frame signal based on
the incoming clock and frame references and its gener­ated clock signals. When slaving, it is sometimes nec­essary to align the edges of this generated frame
signal to the incoming frame reference.

To accomplish this, the T8100 will compare the
referenced frames with the current state of its clock
state machine, and if the difference exceeds one

65.536 MHz clock cycle, the entire stream will have a
fraction of a bit time removed from each frame; this is
referred to as bit sliding. The process will repeat until
the measurements fall within one clock cycle. The
actual bit sliding will take place by reducing the gener­ated frame by one 65.536 MHz clock cycle at the
beginning of the frame. This means that the frame
edges will phase-align at the rate of approximately

15.26 ns per frame. The maximum phase difference is
slightly less than one frame or 124.985 µs. Thus, it will
require approximately 8000 frames, or 1 second, to
phase-align the frame. This is also mean time interval
error (MTIE) compliant; performing phase adjustment
of 162 ns per 1.326 ms of total sample time. Refer to
the MTIE specifications document (ATT 62411).

(continued)

The alternatives to bit sliding are snap alignment and
no alignment. Snap alignment refers to an instanta­neous phase alignment, i.e., a reset at the frame
boundary . Thi s mode is common to other devices. If no
alignment is chosen, the T8100’s generated frame is
frequency-locked to the incoming frame sync, but not
phase-aligned.

2.4.5 Clock Fallback

The following conditions must be met before fallback is
initiated:

■

Fallback must be enabled in register CKS.

■

Failure of one or m ore of the cl ocks selected through
the CKSEL bits in the CKM register.

■

All clocks which comprise the selection from CKSEL
must be unmasked in register CKW (see Section 2.6
Error Registers).

The T8100 contains a fallback register which enab les a
backup set of controls for the clock resources during a
clock failure. In addition, a fallback state machine pro­vides some basic decision-making for controlling some
of the clock outputs when the feature is enab l ed. While
slaving to the bus, the primary course of action in fall­back is the sw ap between the A-cloc ks and B-clocks as
the primary synchronization sources. A slave may
become a master only under software control; i.e.,
there is no automatic promotion mechanism. As a mas­ter, the T8100 can detect its own failures and remove
its clocks from the bus. If it detects a f ailure on the other
main set (e.g., B master detects failures on the A mas­ter), then it can assume the role as the primary syn­chronization source by driving all compatibility clocks
(H-

MVIP

and SC-Bus). Clock failures are flagged
through the CLKERR1 and CLKERR2 registers (Sec­tion 2.6 Error Registers). Additional fallback details are
discussed in relationship to the clock registers in the
next section. The divide-by-4 block for XTALIN, shown
in Figure 12, is used only f or f al lback . See Figure 13 f or
a diagram of the basic state machine which controls
the A, B, and C (compatibility) clocks.

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2 Architecture and Functional Description

2.4 Clocking Section

2.4.5 Clock Fallback

THE T8100 ENTERS AND

LEAVES THESE STATES

BASED ON REGISTER

COUNTERS

INITIAL

(continued)

(continued)

DIAG_ABC

DIAG_AB

C_ONLY

B_ONLY

DIAGNOSTIC/FORCED CLOCKING
FALLBACK CLOCKING, ASSUMES

FALLBACK ENABLED IN CKS REGISTER

B CLOCKS FAIL

A CLOCKS FAIL

(continued)

B_ERROR

DIAG_ABC

AND C CLOCKS, NO FALLBACK PERMITTED

DIAG_AB

REPROGRAM

B CLOCKS

= DRIVES A CLOCKS, B CLOCKS,

= DRIVES A CLOCKS AND B CLOCKS,

NO FALLBACK PERMITTED

C_ONLY

= DRIVES C CLOCKS ONLY,

NO FALLBACK PERMITTED

B_ONLY

= DRIVES B CLOCKS,

CAN DRIVE

C CLOCKS IN

FALLBACK CONDITION

A_ONLY

= DRIVES A CLOCKS,

CAN DRIVE

C CLOCKS IN

FALLBACK CONDITION

B_MASTER

A_MASTER

= DRIVES B AND C CLOCKS,

ALL CLOCKS SHUT OFF IN

FALLBACK CONDITION

= DRIVES A AND C CLOCKS,

ALL CLOCKS SHUT OFF IN

FALLBACK CONDITION

B_ERROR

WAITING FOR B CLOCKS TO BE

A_ERROR

WAITING FOR A CLOCKS TO BE

= NO CLOCKING,

REPROGRAMMED

= NO CLOCKING,

REPROGRAMMED

B_MASTER

A CLOCKS FAIL

A_ONLY

B CLOCKS FAIL

A_MASTER

B CLOCKS FAIL

A_ERROR

A CLOCKS
FAIL

REPROGRAM

A CLOCKS

5-6112F

Figure 13. A, B, and C Clock Fallback State Diagram

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(continued)

2.4.6 Clock Control Register Definitions

Table 39. CKM: Clocks, Main Clock Selection, 0x00

The first register, 0x00, is the clock main (CKM) register. There are ten registers to control the various aspects of
clocking.

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CKM — PAE PAS CCD CKI CKSEL

Symbol Bit Name/Description

PAE 7 Phase Alignment Enable.

PAE = 0, Retains frequency lock without phase alignment
PAE = 1, Enables phase alignment

PAS 6 Phase Alignment.

PAS = 0, Phase alignment, snap
PAS = 1, Phase alignment, slide

CCD 5 The CCD bit is the compatibility clock direction. This controls the I/O for the compatibility

clocks /C16+/–, /C4, C2, SCLK, SCLKX2
think of the CCD bit (in some respects) as a master/slave

, and /FR_COMP (compatibility frame). The user can

select for the compatibility clocks,
though other registers require proper setup to establish true master or slave operation. The
T8100 will assume control of this bit during a fallback if the previously designated compatibil ity
clock master fails.

CCD = 0, Slave, monitors compatibility signals
CCD = 1, Master, drives compatibility signals

Note:

If bit 4 of the programmable cloc ks register, CKP, is low, then the s tate machines of the
A clock and B clock will assume this is an MC-1 system and interpret the clocks as
/C4(L/R) and FRAME(L/R). If this bit is high, then it interprets the clocks as C8(A/B)
and FRAME(A/B).

CKI 4 CKI is used to invert the output of the clock selector, i.e., the signal which feeds the main

divider, resource divider, and DPLL:

CKI = 0, Normal
CKI = 1, Invert

CKSEL 3—0 The decode for the clock selector (CKSEL) is illustrated below. These selections determine

which input state machine is utilized*:

CKSEL = 0000, Internal oscillator
CKSEL = 0001, CT_NETREF
CKSEL = 0010, A clocks (C8A & FRAMEA); ECTF or MC-1
CKSEL = 0011, B clocks (C8B & FRAMEB); ECTF or MC-1
CKSEL = 0100,
CKSEL = 0101, H-

MVIP

MVIP

CKSEL = 0110, SC-Bus, 2 MHz
CKSEL = 0111, SC-Bus, 4 MHz or 8 MHz
CKSEL = 1000—1111 Selects local references 0—7

* Selecting A clocks synchronizes the T8100 to CT_C8A and /CT_FRAMEA; selecting B clocks synchronizes the T8100 to CT_C8B and

/CT_FRAMEB;
SC4/8 requires SCLK, SCLKX2
with an inversion selected from register CKP. A pictorial view of the various clocks may be seen in Section 4.6.1 Clock Alignment.

MVIP

uses /C4, C2, and /FR_COMP; H-

, and /FR_COMP. MC-1 fallback clocks use the same inputs and state machine as the A clocks and B clocks

MVIP

uses /C16+/–, /C4, C2, and /FR_COMP; SC2 uses SCLKX2 and /FR_COMP;

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2 Architecture and Functional Description

2.4 Clocking Section

2.4.6 Clock Control Register Definitions

Table 40. CKN: Clocks, NETREF Selections, 0x01

Clock register 0x01 is CKN, the CT_NETREF select register. This register selects features for generating and rout­ing the CT_NETREF signal.

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CKN — NOE NIO NDB NRI NRSEL

Symbol Bit Name/Description

NOE 7 The NOE bit enables the NETREF output:

NIO 6 The NIO bit controls the internal/external selector. It selects either the NETREF divider for out-

NDB 5 NDB = 0, TODJAT pin comes from NETREF selector, and FROMDJAT pin

NRI 4 NRI inverts the output of the NETREF selector.

NRSEL 3—0 The NRSEL is similar to CKSEL but with fewer choices:

(continued)

(continued)

NOE = 0, CT_NETREF output disabled (3-state)
NOE = 1, CT_NETREF output enabled (NIO must be low)

puts or the NETREF input. Since the latter is used for routing NETREF to the local clock out­puts, it will automatically prevent the NETREF output from being enabled:

NIO = 0, Select NETREF divider, i.e., NETREF as output
NIO = 1, Select NETREF input (disables NETREF output)

Note:

When the NIO bit is high, general-purpose register (GPR), bits 6 and 7 are available.
(The GPR is discussed in Section 2.5.2 General-Purpose Register.)

goes to NETREF divider

NDB = 1, NETREF selector goes directly to NETREF divider

NRI = 0, Normal
NRI = 1, Invert

NRSEL = 0000, Internal oscillator divided by 8
NRSEL = 0001, Internal oscillator
NRSEL = 0010—0111, (Reserved)
NRSEL = 1000—1111, Local references 0—7

(continued)

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2.4.6 Clock Control Register Definitions

Table 41. CKP: Clocks, Programmable Outputs, 0x02

Clock register 0x02, CKP, is the programmed clocks register. It is used for programming the CT_C8 clocks and
enabling its outputs. It is also used to program the TCLK selector. CT_C8 may be operated as either 8 MHz (nor­mal or inverted) or 4 MHz (normal or inverted). The register format is as follows:

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CKP — PTS C8IS CAE CBE C8C4 CFW

Symbol Bit Name/Description

PTS 7—5 The three PTS bits select the output sent to the TCLK. This output is intended to be used for

C8IS 4 C8IS is used to invert the synchronization on C8A and C8B when they are selected for input.

CAE 3 CAE = 0, Disable CT_C8A & /CT_FRAMEA outputs

CBE 2 CBE = 0, Disable CT_C8B & /CT_FRAMEB outputs

C8C4 1 C8C4 = 0, Inverted 4.096 MHz (MC-1 output mode)

CFW 0 CFW = 0, (Reserved)

(continued)

(continued)

driving framers.

PTS = 000, 3-state
PTS = 001, Oscillator, buffered output
PTS = 010, PLL #2, direct output
PTS = 011, PLL #2, output divided by 2
PTS = 100, 2.048 MHz from state machines
PTS = 101, 4.096 MHz from state machines
PTS = 110, 8.192 MHz from state machines
PTS = 111, 16.384 MHz from state machines

The C8 and FRAME signals, which are also generated internally, are routed to both the
CT_C8A and /CT_FRAMEA and to the CT_C8B and /CT_FRAMEB. The CAE and CBE pins
enable these output pairs independently. The C8C4 pin selects 8.192 MHz or 4.096 MHz sig­nals to be output on C8A and C8B (for supporting for either ECTF or MC-1* applications).
CFW selects the output width of the compatibility frame.

C8IS = 0, MC-1 (A and B clocks inputs interpreted as /C4 with /FRAME)
C8IS = 1, ECTF (A and B clocks inputs interpreted as C8 with /FRAME)

CAE = 1, Enable CT_C8A & /CT_FRAMEA outputs (The T8100 will auto-

matically disable these on an A clock failure.)

CBE = 1, Enable CT_C8B & /CT_FRAMEB outputs (The T8100 will auto-

matically disable these on a B clock failure.)

C8C4 = 1, Noninverted 8.192 MHz (ECTF output mode)

CFW = 1, (Reserved)

(continued)

* MC-1 is a multichassis communication standard based on

Lucent Technologies Inc. 43

MVIP

. The T8100 supports this standard.

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2.4.6 Clock Control Register Definitions

Table 42. CKR: Clocks, Resource Selection, 0x03

Clock register 0x03, CKR, is the clock resources register. It is used for selecting and programming miscellaneous
internal resources, the two PLLs, the DPLL, and the clock resource selector. It is also used to program the
SCLK/SCLKX2

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CKR — CRS P1B P1R P2B P2R SCS

Symbol Bit Name/Description

CRS 7—6 The CRS[7:6] bits are used to select the input to PLL #1.

P1B 5 P1B and P1R control PLL #1.

P1R 4 P1R = 0, PLL #1 rate multiplier = 16

P2B 3 P2B and P2R control PLL #2.

P2R 2 P2R = 0, PLL #2 rate multiplier = 8

SCS 1—0 The SCS[1:0] bits are used to program the outgoing SC-Bus compatibility signals.

clock outputs. The register format is as follows:

(continued)

(continued)

CRS = 00, External input (through the 4 MHz In pin)
CRS = 01, Resource divider
CRS = 10, DPLL @ 2.048 MHz
CRS = 11, DPLL @ 4.096 MHz

P1B = 0, Normal PLL #1 operation
P1B = 1, Bypass PLL #1

P1R = 1, PLL #1 rate multiplier = 32

P2B = 0, Normal PLL #2 operation
P2B = 1, Bypass PLL #2

P2R = 1, PLL #2 rate multiplier = 16

SCS = 00, SC-Bus outputs 3-stated
SCS = 01, SCLK @ 2.048 MHz, SCLKX2
SCS = 10, SCLK @ 4.096 MHz, SCLKX2
SCS = 11, SCLK @ 8.192 MHz, SCLKX2

(continued)

@ 4.096 MHz
@ 8.192 MHz
@ phase shifted 8.192 MHz

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2.4.6 Clock Control Register Definitions

Table 43. CKS: Clocks, Secondary (Fallback) Selection, 0x04

Clock register 0x04 is CKS, the secondary clock selection register. This is also referred to as fallback. Along with
programming the CKS register, CKW and CKS should be programmed last. The register is defined as follows:

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CKS — FRS FTS FF FCSEL

Symbol Bit Name/Description

FRS 7—6 FRS provides an alternate clock resource selection. FTS determines the basic fallback mode.

FTS 5—4 For fallback ty pe select, the two FTS bits are used to enab le the automatic f allbac k. These work

FF 3 FF is used as a test of the fallback, but can also be used as a software-initiated fallback.

FCSEL 2—0 The FCSEL choices are a subset of the CKSEL values from the CKM register above. The list is

* This bypasses the CRS/FRS multiplexer and is the default condition. It is equivalent to letting the T8100 free run on a clock failure. It assumes

PLL #1 has been set for x16. If PLL #1 is set for x32, then use FCSEL = 8 kHz local reference, FRS = 10, and FTS = 10.

Lucent Technologies Inc. 45

(continued)

(continued)

FF forces the use of the FRS, FTS, and FCSEL. FCSEL is used to select an alternate synchro­nization source.

FRS forces the clock resource selector to choose a new source for PLL #1.
FRS = 00, External input (through the 4 MHz In pin)

FRS = 01, Resource divider
FRS = 10, DPLL @ 2.048 MHz
FRS = 11, DPLL @ 4.096 MHz

Note:

in conjunction with the various clocks as described in Section 2.4.5 Clock Fallback. If the C8
input select (C8IS of the CKP register above) is low, then the T8100 is assumed to be in an
MC-1 system. Thus, the A/B clocks can be interpreted as /C4L (or /C4R) for C8A and /C4R (or
/C4L) for C8B.

When one of the selected bits goes high in the CLKERR register (i.e., clock f ailure , see Section

2.6 Error Registers), then clocks are changed to the selection indicated by FCSEL, the A or B
clocks are disabled (if applicable), and the compatibility clocks are either driven or disabled (if
applicable). Note that the change is “sticky”; once the fallback has occurred, it will stay in its
new state until the system is reprogrammed. Clearing the CLKERR registers through the MCR
(Section 2.1.2 Master Control and Status Register) clears the fallback condition. A bit in the
SYSERR register will also note when a fallback has occurred.

presented below:

The decode is the same as that of the CRS bits (in the clock resource register, CKR).

FTS = 00, Fallback from main clock to the oscillator divided b y 4* when mai n c loc k fails.

(Main clock determined by CKSEL bits of the CKM register.)

FTS = 01, Fallback disab led; this is not recommended f or oper ation, it is intended f or ini-

tialization and diagnostic purposes only.
FTS = 10, Fallback from main selection to secondary source (FCSEL).
FTS = 11, Fallback from A or B clock (ECTF/MC-1) to secondary; this also enables the

fallback state machine.

FF = 0, Normal operation
FF = 1, Force use of secondary (fallback) resources

FCSEL = 000, Internal oscillator divided by 4
FCSEL = 001, Internal oscillator
FCSEL = 010, A clocks (C8A & FRAMEA); ECTF or MC-1
FCSEL = 011, B clocks (C8B & FRAMEB); ECTF or MC-1
FCSEL = 100, NETREF
FCSEL = 101—111, Selects local references 1—3

(continued)

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2 Architecture and Functional Description

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2.4.6 Clock Control Register Definitions

Table 44. CK32 and CK10: Clocks, Locals 3, 2, 1, and 0, 0x05 and 0x06

Registers 0x05 and 0x06 set up L_SC0, 1, 2, & 3. The outputs L_SC[3:0] can be used as bit clocks for the local
streams or as a secondary NETREF. These are programmed using CK32 and CK10, which are presented below:

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CK32 — LSC3 LSC2
CK10 — LSC1 LSC0

Register Bit Symbol Name/Description

CK32 7—4 LSC3 LSCn = 0000, Output low
CK32 3—0 LSC2
CK10 7—4 LSC1
CK10 3—0 LSC0

(continued)

(continued)

LSCn = 0001, Local frame
LSCn = 0010, NETREF (Sec8K)
LSCn = 0011, PLL #2 ≠ 2
LSCn = 0100, 2.048 MHz
LSCn = 0101, 4.096 MHz
LSCn = 0110, 8.192 MHz
LSCn = 0111, 16.384 MHz
LSCn = 1000, Output high
LSCn = 1001, Local frame, inverted
LSCn = 1010, NETREF, inverted
LSCn = 1011, PLL #2 ≠ 2, inverted
LSCn = 1100, 2.048 MHz, inverted
LSCn = 1101, 4.096 MHz, inverted
LSCn = 1110, 8.192 MHz, inverted
LSCn = 1111, 16.384 MHz, inverted

(continued)

2.4.7 CKMD, CKND, CKRD: Clocks, Main, NETREF,
Resource Dividers, 0x07, 0x08, and 0x09

The remaining clock registers are used to program the
three dividers. The main divider is programmed
through CKMD; the NETREF divider, through CKND;
and the resource divider, through CKRD. The dividers
are fully programmable, b ut only binary divides (1, 2, 4,
8, etc.) and divide by 193 produce 50% duty-cycle out­puts. All other divisors will produce a pulse equal to
one-half of a (selected) clock cycle in width.

0x00 => Divide by 1 (bypass divider)
0x01 => Divide by 2

:

0xC0 => Divide by 193

:

0xFF => Divide by 256
In general, the register value is the binary equivalent of

the divisor-minus-one; e.g., an intended divisor of 193
is reduced by 1 to 192, so the register is loaded with
the binary equivalent of 192 which is 0xC0.

46 Lucent Technologies Inc.

2.5 Interface Section

2.5.1 Microprocessor Interface

The grouping of the read, write, chip select, and
address latch enable signals, along with the data bus
and the address bus, permit access to the T8100 using

Intel

nonmultiplexed interface (ALE = low),
nonmultiplexed interface (ALE = high), or
plex ed interfac e (ALE = active). ALE controls the micro­processor mode. All control and status registers and
data and connection memory accesses are controlled
through this interface. All accesses are indirect, follow­ing the pin descriptions in Table 1 and Table 2. Pro­gramming examples and a more detailed discussion of
the indirect accesses can be found in Section 3 Using
the T8100.

Motorola

Intel

multi-

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2.5 Interfac e Section

2.5.2 General-Purpose Register

A simple, general-purpose I/O register is availabl e. The
GPR has eight dedicated pins to the T8100. A write to
the register forces it to operate as an output. It remains
as an output until a read from the register is performed
(which 3-states the output). The register powers up in
the input state with a cleared register. The GPR corre­sponds with I/O pins GP[0:7]. GP6 and GP7 are
unavailable if bit 5 of register CKN is low (see Section

2.4.6 Clock Control Register Definitions).

Table 45. FRHA, Frame Group A High Address and Control, 0x21

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FRHA — Rate Type FAI Hi Start

Symbol Bit Name/Description

Rate 7—6 Rate = 00, Frame group disabled, 3-state

Type 5—4 Type = 00, Bit-wide pulse

FAI 3 FAI = 0, Normal pulse

Hi Start 2—0 Hi Start = Upper 3 bits of group start address or programmed output

(continued)

Rate = 01, 2.048 Mbits/s
Rate = 10, 4.096 Mbits/s
Rate = 11, 8.192 Mbits/s

Type = 01, Double bit-wide pulse
Type = 10, Byte-wide pulse
Type = 11, Double byte-wide pulse

FAI = 1, Inverted pulse

2.5.3 Framing Groups

Two groups of frame pulses are available. Each frame
group consists of 12 lines which are enabled sequen­tially after a programmed starting point. They are
denoted as group A and group B. This section
describes framing group A. Framing group B is made
up of similar registers. Each frame group is controlled
by a pair of registers: FRHA and FRLA control the
spacing of the 12 frame pulses, their pulse width,
polarity, and the offset of the first pulse from the frame
boundary.

Table 46. FRHB, Frame Group B High Address and Control, 0x23

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FRHB — Rate Type FAI Hi Start

Symbol Bit Name/Description

Rate 7—6 Rate = 00, Frame group disabled, 3-state

Rate = 01, 2.048 Mbits/s
Rate = 10, 4.096 Mbits/s
Rate = 11, 8.192 Mbits/s

Type 5—4 Type = 00, Bit-wide pulse

Type = 01, Double bit-wide pulse
Type = 10, Byte-wide pulse
Type = 11, Double byte-wide pulse

FAI 3 FAI = 0, Normal pulse

FAI = 1, Inverted pulse

Hi Start 2—0 Hi Start = Upper 3 bits of group start address

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2.5 Interfac e Section

2.5.3 Framing Groups

The 12 outputs of the frame group are pulsed in
sequence, one every 8 bit times, where the bit time is
set by the rate option. Thus, the rate option controls the
spacing between output pulses. The pulse width is set
by the type option, and the pulse polarity is set by the
FAI bit. Note that double byte-wide types will produce
overlapping pulses.

The remaining bits (3 hi-start bits in FRHA and 8 bits of
FRHB) make up an 11-bit start address that sets the
offset of the group’s first output (pin FGA0) relative to
the frame boundary. The offset is in increments of
61 ns (1/16.384 MHz). Thus, 2
to the 11-bit start address allow programming offsets
from 0 ns to 125 µs. Notice that the resolution is less
than 1 bit. For example, if the frame group clock is pro­grammed to 2.048 MHz, the resolution is 0.125 of a bit.

The frame boundary, shown in Figure 19 through Fig­ure 21, is the point where /CT_FRAME is low and
CT_C8 is starting its low-to-high transition.

(continued)

(continued)

11

values corresponding

At zero offset, the rising edge of the first frame group
output is coincident with the rising edge of the 8 MHz,
4 MHz, and 2 MHz of the L_SC[3:0] clocks that occ ur in
the center of the CT_FRAME. This defines the start of
the frame, and the start of the first bit of the first time
slot on both the CT bus and local input and local output
buses.

In addition to sequenced pulses, the frame groups can
be used as simple programmed output regis ters. When
group A is used as a programmed output, the bits are
sent from the FRLA [0x20] and FRHA [0x21] registers.
Bits [0:7] of the programmed output come from bits
[0:7] of FRLA [0x20]. Bits [8:10] of the programmed
output come from the high start (bits [0:2]) of FRHA
[0x21], and bit 11 of the programmed output comes
from the F AI bi t (bit 3) of FRHA [0x21]. When group B is
used as a programmed output, bits 0:7 of the output
come from bits 0:7 of separate register FRPL [0x24],
and bits [8:11] of the output come from bits 0:3 of
another register FRPH [0x25]. The upper nibble of
FRPH [0x25] also has output routing functions associ­ated with it. Register FRPH [0x25] is illustrated below;
see Figure 14 for a diagram of the selection options.

Table 47. FRPH: Frame Group B, Programmed Output, High, 0x25

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

FRPH — FAO X FBO Hi Prog

Symbol Bit Name/Description

FAO 7—6 FAO = 00, Frame group A bits [0:11] on output pins [0:11]

FAO = 01, Programmed output A bits [0:11] on output pins [0:11]
FAO = 10, Frame group A bits [0:5] on output pins [0:5], and frame group B bits [0:5] on

output pins [6:11]

FAO = 11, Programmed output A bits [0:5] on output pins [0:5], and frame group B bits

[0:5] on output pins [6:11]

X 5 X (Reserved)

FBO 4 FBO = 0, Frame group B routed to group B output pins

FBO = 1, Programmed output B routed to group B output pins

Hi Prog 3—0 High Prog = Upper 4 bits of programmed output B

Note:

In the programmed output mode, the rate must not equal 00; otherwise, the outputs
corresponding to the group bits are 3-stated; the rate will have no effect other than
enabling the mode. Type bits have no effect in the programmed modes.

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2.5 Interface Section

2.5.3 Framing Groups

PROGRAMMED OUTPUT A, BITS [0:5]

PROGRAMMED OUTPUT A, BITS [6:11]

PROGRAMMED OUTPUT B, BITS [0:11]

(continued)

(continued)

FRAME GROUP A, BITS [0:5]

FRAME GROUP A, BITS [6:11]

FRAME GROUP B, BITS [0:5]

FRAME GROUP B, BITS [0:11]

(continued)

T8100

INTERNAL

SIGNALS

FAO

FBO

T8100

OUTPUT

PINS

FGA[0:5]

FGA[6:11]

FGB[0:11]

5-6113F

Figure 14. Frame Group Output Options

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2 Architecture and Functional Descrip­tion

(continued)

2.6 Error Registers

Four error registers are present in the T8100:

■

CLKERR1 [0x28]

■

CLKERR2 [0x29]

■

CKW [0x2B]

■

SYSERR [0x2A]

When programming the clock registers , writing to CKW
and CKS should be programmed last.

These are the clock error, watchdog enable, and sys-

The CKW register works in conjunction with the two
registers above and with the cloc k circuitry. It is used to
enable the watchdogs f or the clock lines . CKW uses the
same mapping as CLKERR1 and CLKERR2, so, for
example, a high in bit 7 will enable the watchdogs for
CT_C8A and /CT_FRAMEA. CKW functions as a
masking register for CLKERR1 and CLKERR2. If the
appropriate bit is not set, then a failing clock will not be
reported.

The SYSERR register is shown below, the bits are
ORed together with the CLKERR1 bits which, in turn,
drives the SYSERR pin. The SYSERR bits are sticky
as are the CLKERR1 bits so they must be reset by
clearing the register by setting a bit in the MCR (Sec­tion 2.1 Register/Memory Maps).

tem error registers. The CLKERR1 register is used to
indicate failing clocks, and the CLKERR2 indicates
whether the failure is permanent or transient in nature.
If the clocks fail, i.e., disappear or momentarily drop
out, then corresponding bits in both registers will be
set. If the clock is reestablished, i.e., a transient error,
then the T bit(s) will clear, but the E bit(s) will remain
set. All of the E bits are ORed together and drive the
CLKERR pin.

The clocks listed above are sampled by the

16.384 MHz internal clock. Eff ectiv ely, each clock has a
watchdog. If the clock is switching, the watchdog
clears. If the clocks stop, then the watchdog sets the
appropriate E and T bits. If the clock is reestablished,
then the E bits remain stuck, but the T bits clear with
the watchdog. Since fallback is triggered on the E bits,
a transient clock can force a fallback.

Table 49. SYSERR: System Error Register, 0x2A

Table 49 describes SYSERR:

Name Bit Name/Description

CUE 7 CUE => Even CAM underflow, set by

an unmatched comparison

CUO 6 CUO => Odd CAM underflow, set by

an unmatched comparison

CUL 5 CUL => Local CAM underflow, set by

an unmatched comparison

COE 4 COE => Even CAM overflow, set by a

write to a full CAM

COO 3 COO => Odd CAM overflow, set by a

write to a full CAM

COL 2 COL => Local CAM overflow, set by a

write to a full CAM

Table 48. CLKERR1 and CLKERR2: Error Indicator

and Current Status, 0x28 and 0x29

Table 48 describes both CLKERR1 and CLKERR2:

Name Bit Name/Description

CAE

CAT

CBE
CBT

CFE

CFT

C16E
C16T

C42E

7 CA => Reports failures on CT_C8A

or /CT_FRAMEA

6 CB => Reports failures on CT_C8B

or /CT_FRAMEB

5 CF => Reports failures on

/FR_COMP

4 C16 => Reports failures on /C16+ or

/C16–

3 C42 => Reports failures on /C4 or C2

(RES) 1 RES Reserved bit position

FBE 0 FBE => Fallback enabled, status

which indicates that a clock
error has occurred and fall­back operations are in
effect*.

* This error bit is selective. It will only flag an error if the clocks that

fail correspond to the selected clock mode. For ex am ple, if
mode is selected (in register CKM), the proper fallback mode has
been set (in register CKS), and the
(register CKW, above), then FB E will go high when a failure is
detected on /FR_COMPn, C2, or /C4. Thus, unmasked, failing non-

MVIP

clocks will be flagged in the CLKERR1 and CLKERR2 regis-

ters but will not set the FBE flag in SYSERR.

MVIP

clocks are not masked

MVIP

C42T

SCE

2 SC => Reports failures on SCLK

SCT

SC2E

1 SC2 => Reports failures on

SCLKX2

SC2T

NRE
NRT

0 NR => Reports failures on

CT_NETREF

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2.7 The JTAG Test Access Port

2.7.1 Overview of the JTAG Architecture
Tap

TAP Controller

Instruction Register (JIR)

Boundary-Scan Register (JBSR)

A 5-pin test access port, consisting of input pins TCK, TMS, TDI, TDO,
and TRST, provides the standard interface to the test logic. TRST is an
active-low signal that resets the circuit.

The TAP controller implements the finite state machine which controls the
operation of the test logic as defined by the standard. The TMS input
value sampled on the rising edge of TCK controls the state transitions.
The state diagram underlying the TAP controller is shown below.

A 3-bit scannable JTAG instruction register that communicates data or
commands between the TAP and the T8100 during test or HDS opera­tions.

A 211-bit JTAG boundary-scan register containing one scannab le register
cell for every I/O pin and every 3-state enable signal of the device, as
defined by the standard. JBSR can capture from parallel inputs or update
into parallel outputs for every cell in the scan path. JBSR may be config­ured into three standard modes of operation (EXTEST, INTEST, and
SAMPLE) by scanning the proper instruction code into the i nstruction reg­ister (JIR). An in-depth treatment of the boundary-scan register, its physi­cal structure, and its different cell types is given in Table 51.

(continued)

Bypass Register (JBPR)

2.7.2 Overview of the JTAG Instructions

The JTAG block supports the public instructions as shown in the table below.

Table 50. T8100 JTAG Instruction Set

Instruction

Mnemonics

EXTEST 000 Public — Select B-S register in extest mode

SAMPLE 001 Public — Select B-S register in sample mode
Reserved 010 — — —
Reserved 011 — — —
Reserved 100 — — —
Reserved 101 — — —
Reserved 110 — — —

BYPASS 111 Public — Select BYPASS register

Instruction

Codes

A 1-bit long JTAG bypass register to bypass the boundary-scan path of
nontargeted devices in board environments as defined by the standard.

Public/Private Mode Description

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2.7 The JTAG Test Access Port

2.7.3 Elements of JTAG Logic

Table 51. T8100 JTAG Scan Register

Cell Type Signal Name/Function

66 I CK_3MHZIN
67 O SYSERR
68 O CLKERR

0 CC Controls cells 67:68

69—76 Bdir D[0:7]

1 CC Controls cells 69:76
77 I RESTN
78 O RDY
79 I WRN
80 I RDN
81 I CSN
82 I ALE
83 I A0
84 I A1

85—88 O L_SC[0:3]

44 CC Controls cells 85:88

89—96 I L_REF[0:7]

97 I CK_4MHZIN
98 O PRIREFOUT
45 CC Controls cell 98
99 O TESTOUT1

100 O REFCLK1O

46 CC Controls cells 99, 100

101 Bdir FROMDJAT

43 CC Controls cell 101

102 Bdir TODJAT

42 CC Controls cell 102

103—108 Bdir GP[5:0]

41 CC Controls cells 103—108

109—120 O FGB[11:0]

63 CC Controls cells 109—120

(continued)

(continued)

Cell Type Signal Name/Function

121—132 O FGA[11:0]

64 CC Controls cells 121—132
133 Bdir C16N_MINUSA
134 Bdir C16N_PLUSA
135 Bdir C4N
136 Bdir C2

5 CC Controls cells 133—136

137 Bdir SCLKX2NA

7 CC Controls cell 137

138 Bdir SCLKA

6 CC Controls cell 138
139 Bdir CT_C8_BA
140 Bdir CT_FRAME_BNA

3 CC Controls cells 139—140
141 Bdir FRN_COMPA

4 CC Controls cell 141
142 Bdir CT_NETREF

8 CC Controls cell 142
143 Bdir CT_C8_AA
144 Bdir CT_FRAME_ANA

2 CC Controls cells 143—144

145—176 Bdir CT_D[0:31]

9—40 CC Controls cells 145—176

177—192 O LDO[0:15]

47—62 CC Controls cells 177—192

193 O XCS

0 CC Controls cell 193

194—209 I LDI[0:15]

210 O PMCTCLKO

65 CC Controls cell 65

52 Lucent Technologies Inc.

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2.8 Testing and Diagnostics

There are several testing operations available for the
T8100:

■

JTAG

■

Forced output testing

■

Onboard diagnostics

During manufacturing, the T8100 is run through stan­dard functional and electrical testing.

2.8.1 Testing Operations

JTAG is used primarily to test the array portion of the
T8100. It will not provide coverage for the CAMs, regis­ter files, SRAMs, or PLLs. In JTAG, the manufacturer
provides a drop-in control block and scan-chain which
ties internal points to registers on the periphery of the
T8100, which are, in turn, tied to the I/O pins. Serial bit
patterns are shifted into the T8100 through the TDI pin,
and the results can be observed at the I/O and at a cor­responding JTAG serial output, TDO. Since this JTAG
conforms to the JTAG standard, the TDI and TDO can
be linked to the JTAGs of other devices for systemic
testing. The TTS pin must be low for JTAG operations
to work. The TTS pin has an internal pull-down resistor
that defaults the T8100 to JTAG operations.

2.8.2 Diagnostics

The T8100 has onboard diagnostic modes for testing
the frame groups, SRAMs and CAMs, and some inter­nal structures. These are intended for testing some of
the T8100 resources while it is in an application envi­ronment (rather than a manufacturing test environ­ment).

The diagnostics allow critical internal nodes to be out­put through the frame groups, or to have the frame
groups operated in special cyclical manner, or to pro­vide automatic filling of all memories (including CAMs)
with one of four selected patterns. The diagnostics are
activated and selected using three registers: DIAG1
[0x30], DIAG2 [0x31], or DIAG3 [0x32].

DIAG1 is used to select the frame group pins as either
monitors for internal nodes or normal operation (i.e., as
frame groups or programmed outputs). DIAG1 is also
used to control the memory fill diagnostic.

DIAG2 and DIAG3 modify the normal operation of the
frame groups and the main state counter. Normally, the
frame groups begin their cascade sequence when the
state counter (i.e., the frame-synchronized master
counter of the T8100) reaches a value equal to the
frame group’s starting address. DIAG2 and DIAG3
allow the state counter to be modified for one of two dif­ferent tests.

In forced output testing, the outputs are set to a particu­lar state to measure their dc parameters. This can also
be used in applications for board-level diagnostics.
Forced output testing is selected by setting the TTS
(test type select) pin high. In this mode, the JTAG clock
pin, TCK, will act as an input pin. All outputs will be
enabled, and each output provides either an inverting
or normal response to the input pin. Adjacent pins
alternate inverting and normal function (i.e., a checker­board pattern).

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2.8 Testing and Diagnostics

2.8.2 Diagnostics

The three registers are presented in order below:

DFA DFB DMF DMP DMD

DFC DSB DXF (Res.) DSE DSH

The register fields are interpreted as follows:

DFA—Diagnostics, Frame Pin Selects, Group A:

DFn = 00, Normal operation
DFn = 01, State counter bits [10:0] routed to frame

group pins [10:0], pin 11 = L

DFn = 10, Even CAM hit routed to pin 11, pin 10 has

odd CAM hit, pins [9:0] have local data
memory address

DFn = 11, Pin 11 gets CUE error bit, pin 10 gets CUO

error bit, pin 9 gets CUL error bit, pin 8 gets
COE error bit, pins [5:0] get page pointers—
8 MHz read, 8 MHz write, 4 MHz read,
4 MHz write, 2 MHz read, and 2 MHz write

DFB—Diagnostics, Frame Pin Selects, Group B:

DFn = 00, Normal operation
DFn = 01, State counter bits [10:0] routed to frame

group pins [10:0], pin 11 = L

DFn = 10, CAM state register [1:0] indicating four sub-

states, routed to pins [11:10], and local con­nection memory address routed to pins [9:0]

DFn = 11, Pin 11 gets local CAM hit flag, and pins

[10:0] get CAM state counter

DMF—Diagnostics, Memory, Fill Test Enable:

DMF = 0, Normal operation
DMF = 1, Fill all memories with the pattern selected

by DMP

DMP—Diagnostics, Memory, Fill Test Pattern
Select:

DMP = 00, Checkerboard 0—even locations get 0x55,

odd locations get 0xAA

DMP = 01, Checkerboard 1—even locations get 0xAA,

odd locations get 0x55

DMP = 10, Data locations equal address bits [7:0]

(CAMs are filled with their physical address)

DMP = 11, Data locations equal inverted address bits

[7:0]

(continued)

DSL

(continued)

DMD—Diagnostics, Memory, Done Indicator:

This is a status bit which indicates that the chosen
memory pattern has been written to all locations. Addi­tional writes to the memory are disabled and reads are
enabled. This condition remains until the user clears
this bit.

DFC—Diagnostics, Frame Groups Cycle Test
Mode:

DFC = 0, Normal operation
DFC = 1, Cycle test mode enabled; forces the frame

groups to constantly cycle without waiting for
a frame signal to synchronize the start.

DSB—Diagnostics, State Counter, Break Carry
Bits:

DSB = 0, Normal operation
DSB = 1, Breaks the carry bits between the subsec-

tions of the state counter so that the state
counter is operating as three counters run­ning in parallel. (This can be viewed on the
frame pins using the DFn = 01 selection
described above.) Status counter bits [0:3]
and [4:7] run as modulo-16 counters, and bits
[8:10] run as a modulo-8 counter.

DXF—Diagnostics, External Frame Input:

DXF = 0, Normal operation
DXF = 1, Forces /FR_COMP to act as a direct input

signal for T8100 framing. This effectively
bypasses the internally generated frame sig­nal. The user is again cautioned since the
external frame can operate asynchronously
to the generated clocks if care is not taken.

DSE—Diagnostics, State Counter, Enable Parallel
Load:

DSE = 0, Normal operation
DSE = 1, Forces the state counter to load the value

held in DSH and DSL and continuously cycle
as a modulo-n counter where the n value is
determined by (DSH and DSL). With the DSE
pin high, the state counter is no longer syn­chronized to the frame signal.

DSH—Diagnostics, State Counter, High Bits of Par­allel Load:

DSH = State counter bits [10:8]

DSL—Diagnostics, State Counter, Low Bits of Par­allel Load:

DSL = State counter bits [7:0]

5454 Lucent Technologies Inc.

Preliminary Data Sheet

T8100

RDY

PLLV

DDS

PLLGND

S

VDD = 3.3 V

25

Ω

TANTALUM

10 kΩ50 k

Ω

NETREF,

C8s, AND

FRAMES

33 µF

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3.1 Resets

3.1.1 Hardware Reset

A hardware reset utilizes the (active-low) RESET
On activation, it immediately places all outputs into
3-state. Individual output sections must be reenabled
by setting the appropriate bits high in the MCR register .
Internally, the local memory is in an undefined state, all
CAM empty bits are set, all state machines are reset,
and all registers are cleared to zero.

3.1.2 Software Reset

This is accomplished by setting the MSB of the master
control and status register (see Section 2.1.2 Master
Control and Status Register). The local and H-Bus con­nections are rendered invalid, all registers are cleared
except MCR, CLKERR1, CLKERR2, and SYSERR
(these registers are cleared with separate MCR control
bits); the state machines are also reset. Applying the
value 0xE0 to the MCR is a full software reset. Applying
0x0E enables all pin groups (though i ndividual pins sti ll
require setup). This soft reset is clocked by the crystal
oscillator.

pin.

3.2 Basic Connections

At a minimum, the T8100 requires power, ground, and
a 16.384 MHz crystal (or 16.384 MHz crystal oscilla­tor). It is also recommended that the internal PLLs be
treated as other analog circuits are, so the user should
provide the appropriate filtering between the PLL1V
and V

pins (as well as PLL2VDD and VDD pins). The

DD

RDY pin is operated as an open collector output. It is
actively driven low or into 3-state. The user should
apply a pull-up (e.g., 10 kΩ) to maintain standard
microprocessor interfacing. It is recommended that the
10 kΩ be tied to 3.3 V (since the T8100’s nominal
V

is 3.3 V), but the resistor may also be tied up

OH

to 5 V without damaging the device. PLL connections
are shown in Figure 15. The H.100/H.110 clock
signals, CT_C8_A, CT_C8_B, /CT_FRAME_A,
/CT_FRAME_B, and CT_NETREF each require an
individual external pull-up of 100 kΩ to 5 V or 50 kΩ to

3.3 V.

DD

3.1.3 Power-On Reset

No power-on reset is available. It is expected that the
host microprocessor or applications board will provide
an external control to the RESET

pin for performing a
hardware reset. The PLLs must not be enabled prior to
establishing a stable supply voltage. There are two
methods to accomplish this:

■

Tie the En1 and En2 pins to the same line that drives
the RESET

which forces the PLLs into an off condi-

tion while the T8100 resets asynchronously.

■

Add external capacitors from En1 to ground and from
En2 to ground. (The values of the capacitors should
be 1 µF or greater.) The capacitors will form RC cir­cuits with the En1 and En2 internal pull-ups and will
charge up to enable the PLLs after several millisec­onds. The RC circuit affects the power-on reset for
the PLLs. The long rise time provides some delay.

5-6114.aF

Figure 15. External Connection to PLLs

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3.2 Basic Conn e ctions

(continued)

(continued)

3.2.1 Physical Connections for H.110

Figure 16 shows the T8100 physical connections
required for use in an H.110 environment. There are
electrical differences between H.100 and H.110. For
H.110, external components are required to meet spec­ifications. Figure 16 shows the T8100 NETREF termi­nations and the required terminations for CT_C8A,
CT_FRAMEA, CT_C8B, and CT_FRAMEB. Each sig­nal has a mechanism to short the 33 Ω series resistor
and, in addition, a 10 kΩ pulldown resistor. The 50 kΩ
internal pull-ups on the CT data bus are used for
H.100. For H.110, the DPUE pin should be tied low,
disabling these internal pull-ups. H.110 requires the CT
data bus to hav e pull-ups of 18 kΩ to 0.7 V. The control
leads of the FET switches would typically go to the
microprocessor.

3.2.2 H.100 Data Pin Series Termination

All data bus lines must have a 24 Ω series
resistor, even if only data lines 16—31 are used
at 8.192 Mbits/s.

3.2.3 PC Board Considerations

There are no special requirements for the thermal balls
on the BGA package when designing a printed-circuit
board.

CT_FRAMEA

CT_C8A

CT_FRAMEB

CT_C8B

CT_NETREFB

CT_NETREFA

10 k

10 k

10 k

10 k

V

PULL-UP

V

PULL-UP

Ω

Ω

Ω

Ω

0.7 V

0.7 V

18 k

18 k

33

Ω

CTC8A_SRC

33

Ω

CTC8A_SRC

33

Ω

CTC8B_SRC

33

Ω

=

CTC8B_SRC

Ω

24

Ω

=

CTR_NETB

Ω

24

Ω

CTR_NETA

CT_FRAMEA

LUCENT T8100

CT_C8A

CT_FRAMEB

CT_C8B

CT_NETREF

RDY AND PLL
CONNECTIONS
ARE THE SAME

AS IN H.100

SCLK

SCLKX2

CTD[0:31]

0 Ω DEPOPULATE

0 Ω DEPOPULATE

32

0.7 V

18 k

Ω

SCLK

SCLKX2

24

Ω

CTD[0:31]

DPUE

5-7142F

Figure 16. Physical Connections for H.110

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3.3 Using the LAR, AMR, and IDR for Con­nections

3.3.1 Setting Up Local Connections

Local connections require a physical location in the
local connection memory corresponding to the output
stream and time slot. The location contains a pointer to
a local data memory location which holds the actual
data that has come in or will be sent out. The local
memories are based on 1024 locations, so 10 bits are
required to specify the physical memory location where
a connection is placed or where data is stored. To sim­plify the programming, the user supplies 11 bits in a
stream and time-slot format, which is converted by the
T8100 to the appropriate physical location. Relative to
describing a connection, a data memory location corre­sponds with the FROM stream and time slot, and a
connection memory location corresponds with the TO
stream and time slot. To program a connection, the
user loads the data memory location into the connec­tion memory location, effectively identifying where the
data resides.

The user programs 7 bits of the LAR for the time-slot
value (or 8 bits for pattern mode) and the lowest 4 bits
of the AMR for the stream value; these will then be con­verted to the physical memory address. The upper bits
of the AMR select which field in the connection mem­ory is being written into. Since the connection informa­tion itself is 15 bits, two transfers (i.e., two fields) must
be made to the address in the connection memory.

In each case, the transfer is an indirect write of data to
the indirect data register, the IDR: The first transfer is
the lowest 7 bits (time-slot address) of the desired data
memory location. It is placed in the IDR after the LAR
and AMR have been set up with the appropriate con­nection address.

Table 52. Time-Slot Bit Decoding

Address

Value

0x00 0 0 0
0x01 1 1 1
0x02 2 2 2
0x03 3 3 3
0x04 4 4 4
0x05 5 5 5
0x06 6 6 6
0x07 7 7 7
0x08 8 8 8
0x09 9 9 9
0x0A 10 10 10
0x0B 11 11 11
0x0C 12 12 12
0x0D 13 13 13
0x0E 14 14 14
0x0F 15 15 15
0x10 16 16 16
0x11 17 17 17

::::
0x1E 30 30 30
0x1F 31 31 31
0x20 NA 32 32

::::
0x3E NA 62 62
0x3F NA 63 63
0x40 NA NA 64

::::
0x7E NA NA 126
0x7F NA NA 127

2 Mbits/s

Time Slot

4 Mbits/s

Time Slot

8 Mbits/s

Time Slot

Table 52 illustrates the decoding of the time-slot bits
(address value in the tab le ref ers to the he x v alue of the
7 bits comprising time slot).

When programming the registers for fallback, the CKS
and CKW registers should be programmed last.

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3 Using the T8100

3.3 Using the LAR, AMR, and IDR for Connections

3.3.1 Setting Up Local Connections

(continued)

(continued)

(continued)

Table 53. IDR: Indirect Data Register, Local Connections Only

The second transfer requires that data in the IDR be defined as follows:

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

IDR —

Control Address

XCSPMEFMECHE————

Symbol Bit Name/Description

XCS 7 A programmable bit which is routed to the XCS pin one time slot prior to the data to

which it relates.

PME 6 A high enables the pattern mode; the lower 8 bits of the connection address (time slot

and stream LSB) is routed to the time slot instead of data.

FME 5 A high enables the use of the alternate data buffer; refer to Appendix B for minimum

and constant delay settings.

CHE 4 Enables the time-slot connection; a low in this bit forces 3-state during the time slot.

Address 3—0 All 4 bits are used for the stream address of the desired data memory location.

After the second transfer is made, the entire 15 bits will be loaded into the connection memory; i.e., the second
transfer triggers the actual memory access. Figure 17 shows how the connections are made from the perspective
of the registers and memory contents.

If the user wishes to set up a pattern mode connection, then the first tr ansfer is a full 8 bits (i.e., the pattern), rather
than the 7-bit time-slot value . This pattern byte will be stored in the lo west 8 bits of the selected connec tion memory
location. The pattern byte will be sent instead of a byte from local data memory during the output stream and time
slot which corresponds to the connection memory location.

LOCAL MEMORY PROGRAMMING EXAMPLE: CONNECT FROM 14, 7 TO 3, 29 (STREAM, TIME SLOT)

WRITE TO

TIME-SLOT

FIELD IN

CONNECTION

MEMORY

3, 27
3, 28
3, 29
3, 30
3, 31

FIRST TRANSFER:

AMR LAR IDR

0100 0011 0001 1101 0000 0111

0000 0111

CONTROL/STREAM

WRITE TO

FIELD IN

CONNECTION

MEMORY

CONNECTION

MEMORY

3, 27
3, 28
3, 29
3, 30
3, 31

SECOND TRANSFER:

AMR LAR IDR

0101 0011 0001 1101 0001 1110

0000 01110001 1110

CONNECTION

MEMORY

5-6115aF

Figure 17. Local-to-Local Connection Programming

58 Lucent Technologies Inc.

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3.3 Using the LAR, AMR, and IDR for Connections

3.3.2 Setting Up H-Bus Connections
Table 54. IDR: Indirect Data Register, H-Bus Connections Only

REG R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

IDR —

Symbol Bit Name/Description

R/W

PME 6 Pattern mode enable, similar to above, except the tag byte is output instead of the lower

FME 5 Data buffer selection for setting delay type. (Refer to Appendix B for minimum and constant

Address 4—0 All 5 bits are used for the stream address of the desired data memory location.

The CAM blocks are 256 locations each and the opera­tions for the CAM blocks are selected by AMR (see
Section 2.1.3 Address Mode Register and Section

2.3.2 CAM Operation and Commands). Since the bloc k
address is carried in the AMR, this reduces the number
of bits which are necessary to establish a connection.
Eleven (11) address bits, i.e., bits for stream and time­slot identification, the 8-bit tag (pointer to the H-Bus
data memory), and 3 control bits all need to be written
into the selected CAM block for setting up a connec­tion. (The empty bit is a status bit that is changed inter­nally as a result of operations on the CAM.) Three
transfers, indirect writes through the IDR, are required
to set up a connection in the CAM, though the method
of transfer is different than with the local memory . Sinc e
a specific physi cal address is not alwa ys necessary, the
CAM will automatically fill the first available slot. Thus,
the LAR is not required for setting up the connection.
(See the notes below.) The first transfer after program­ming the AMR requires that the 7 bits which identify the
time-slot number (refer to Section 2.3.5 H-Bus Rate
Selection and Connection Address Format for the
proper format) be loaded into the IDR. The second
transfer uses a similar field description for the IDR as
presented for local connections (Section 3.3.1 Setting
Up Local Connections above). The address field con­tains the stream number (5 bits), and the control field
contains only three control bits.

The third (and final) transfer for CAM connection setup
is the transfer of the 8-bit tag field. The tag is loaded
into the IDR. The connection f or the CAM is actual ly set
up, i.e., the memory access takes place, using a fourth
write. It is an indirect write to the AMR (again through
the IDR) which corresponds with the specific command
and blocks the user requests. All CAM commands

Lucent Technologies Inc. 59

7 Refers to the direction in the CAM data memory. A read sends data to the bus; a write loads

data from the bus.

address bits.

delay setting.)

(continued)

R/W

(continued)

Control Address

PMEFME—————

require that the IDR be loaded with the same command
value as the AMR rather than a don’t care or dummy
value.

Notes:

For the CAMs, pattern mode is a 1/2 connection. Only
the intended output to the H-Bus (or to the local pins)
needs to be specified. The setup is the same as
described above, three transfers to the holding regis­ters followed by the make connection command to the
appropriate CAM block. When the address is matched,
the tag value (from the pipeline SRAM) will be sent as
output to the bus.

Figure 18 illustrates how a CAM connection is made
from the perspective of registers and the memory loca­tions. Note that each half of the connection, that is the
FROM and the TO, requires a separate setup, though
each half will point to the same location in the H-Bus
data memory.

Following Figure 18, some simple programming exam­ples are shown using pseudoassembler code. The
local-to-local and H-Bus-to-local switching examples
from Figure 17 and Figure 18 are reused in code exam­ples #2 and #3. The connections are referred to in
stream, time-slot format.

If an address is to be matched, such as the
break connection command, then only the first
two transfers are required. The tag is unneces­sary for identifying a connection.

The LAR is only used to read or query a spe­cific location (i.e., 0—255) in a particular CAM
block. Refer to Section 2.1.3 Address Mode
Register and Section 2.3.2 CAM Operation
and Commands for details on these com­mands.

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(continued)

3.3 Using the LAR, AMR, and IDR for Connections

3.3.2 Setting Up H-Bus Connections

:

WRITE TO TIME-SLOT

HOLDING REGISTER

WRITE TO CONTROLS/STREAM

HOLDING REGISTER

DIRECTION BIT: FROM

BUS TO DATA MEMORY

WRITE TO TAG

HOLDING REGISTER

(continued)

CAM PROGRAMMING EXAMPLE:

CONNECT FROM H-BUS 14, 7 TO LOCAL 3, 29,

KEEP DATA IN LOCATION 49

FIRST TRANSFER:

AMR LAR (UNUSED) IDR

1011 0000 XXXX XXXX 0000 0111

0000 0111

CTLS/STREAM

SECOND TRANSFER:

AMR LAR (UNUSED) IDR

1011 0001 XXXX XXXX 000 01110

000 01110 0000 0111

CTLS/STREAM

THIRD TRANSFER:

AMR LAR (UNUSED) IDR

1011 0010 XXXX XXXX 0011 0001

000 01110 0000 0111 0011 0001

CTLS/STREAM

TIME SLOT TAG

TIME SLOT TAG

TIME SLOT TAG

(continued)

HOLDING REGISTERS

HOLDING REGISTERS

DATA LOCATION 49

HOLDING REGISTERS

TRANSFER HOLDING

REGISTERS TO NEXT FREE

LOCATION IN EVEN CAM

1110 0000 XXXX XXXX 1110 0000

LOAD CAM:

AMR LAR (UNUSED) IDR (MUST = AMR)

CTLS/STREAM

(LOCATION USED—NOT EMPTY)

000 01110

(LOCATION NOT USED—EMPTY)

TIME SLOT TAG

0011 00010000 0111000 01110

(NOT EMPTY)

0000 0111

EVEN CAM PIPE LINE SRAM

0000 0111
(EMPTY)

HOLDING REGISTERS

LOCATION USED—NOT EMPTY

5-6116F

A. First Half of Connection, H-Bus Side

Figure 18. CAM Programming, H-Bus-to-Local Connection

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(continued)

3.3 Using the LAR, AMR, and IDR for Connections

3.3.2 Setting Up H-Bus Connections

WRITE TO TIME-SLOT

HOLDING REGISTER

WRITE TO CONTROLS/STREAM

HOLDING REGISTER

DIRECTION BIT: TO BUS

FROM DATA MEMORY

WRITE TO TAG

HOLDING REGISTER

(continued)

CAM PROGRAMMING EXAMPLE (CONTINUED):

CONNECT FROM H-BUS 14, 7 TO LOCAL 3, 29,

KEEP DATA IN LOCATION 49

FIRST TRANSFER:

AMR LAR (UNUSED) IDR

1011 0000 XXXX XXXX 0001 1101

0001 1101

CTLS/STREAM

SECOND TRANSFER:

AMR LAR (UNUSED) IDR

1011 0001 XXXX XXXX 100 00011

100 00011 0001 1101

CTLS/STREAM

THIRD TRANSFER:

AMR LAR (UNUSED) IDR

1011 0010 XXXX XXXX 0011 0001

100 00011 0001 1101 0011 0001

CTLS/STREAM

TIME SLOT TAG

TIME SLOT TAG

TIME SLOT TAG

(continued)

HOLDING REGISTERS

HOLDING REGISTERS

DATA LOCATION 49

HOLDING REGISTERS

TRANSFER HOLDING

REGISTERS TO NEXT FREE

LOCATION IN LOCAL CAM

NEXT FREE LOCATION

1110 0011 XXXX XXXX 1110 0011

LOAD CAM:

AMR LAR (UNUSED) IDR (MUST = AMR)

CTLS/STREAM

(LOCATION USED—NOT EMPTY)

100 00011

(LOCATION NOT USED—EMPTY)

TIME SLOT TAG

0011 00010001 1101100 00011

(NOT EMPTY)

0001 1101

LOCAL CAM PIPELINE SRAM

0011 0001
(EMPTY)

HOLDING REGISTERS

LOCATION USED—NOT EMPTY

5-6117F

B. Second Half of Connection, Local Side

Figure 18. CAM Programming, H-Bus-to-Local Connection

(continued)

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3.3 Using the LAR, AMR, and IDR for Connections

3.3.3 Programming Examples

;All programming examples included are in a pseudoassembler format.
;The basic commands used are the “move direct ” and “move indirect.”
;A move direct command is indicated by the letters “MD” followed by
;the register name, then the data. Similarly, a move indirect command
;is indicated by the letters “MI” followed by the register name, then by
;data or another register reference (the register may not be indirect).
;The semicolon delineates comments. Direct data is followed by the
;letter “h” for Hex and “b” for binary.

;*******EXAMPLE #1 - Set Up Clocks, Local Bus, H-Bus, and Framers
;
;*******Misc . Stuff
;
MD,AMR,00h ;D efine control spac e

;
;
;*******Set up Clocks

MD,IDR,0C2h ;Load IDR with values for bit slider on, slave mode,

MI,CKM,IDR ;The data in IDR is moved into CKM via the LAR register.
;
;**NETREF Regi sters
MD,IDR,88h ;Set up NETREF from Local Reference 0, 2.048 MHz bit clock

MI,CKN,IDR ;Move the data to CKN
MD,IDR,0FFh ;Set up NETREF divider with divide-by-256
MI,CKND,IDR ;Move the data to CKND
;
;**Programmable Clocks
MD,IDR,26h ;This selects the oscillator for the TCLKO, A Clock

MI,CKP,IDR ;M ove the data
;
;**Clock Resources
MD,IDR,40h ;Synced to bus so select Resource divider, x16 on PLL #1 &

MI,CKR,IDR ;Make it so
MD,IDR,01h ;Set up Resource divider with divide-by-2 for 4 MHz signal

MI,CKRD,IDR ;Move the data to divider
;

(continued)

(continued)

;all specific register names are equivalent
;to the LAR addresses (from Table 11)

;**Main Clock Re gister

;and synced to ECTF Bus A Clocks

in, divided value
;value out (i.e., 8 kHz), enable the DJAT connections

outputs off, and
;driving ECTF B Clocks

x8 PLL #2, SC Clocks off

into PLL #1

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3.3 Using the LAR, AMR, and IDR for Connections

3.3.3 Programming Examples

;**Secondary Controls (Fallback)
MD,IDR,35h ;Enable ECTF Fallback: Become the new A Clock master on A

MI,CKS,IDR ;Move the data to CKS
MD,IDR,0FFh ;Set up Main divider with divide-by-256
MI,CKMD,IDR ;Move the data to divider

;**Local Clocks
MD,IDR,0E4h ;Local Selected Clock 3 gets inverted 8.192 MHz, LSC2 gets

MI,CK32,IDR ;Move it to CK32
MD,IDR,80h ;LSC1 is high & LSC0 is low
MI,CK10,IDR ;Move it to CK10
;
;*******Set up Lo cal Streams
;
MD,IDR,30h ;8 Streams at 8 Mbits/s
MI,LBS,IDR ;Define input streams per IDR
;
;*******Set up H Bu s Streams
;
MD,IDR,0AAh ;Define H-Bus Streams 0 - 15 for 4 Mbits/s
MI,HSL,IDR ;D o it
;
MD,IDR,0FFh ;Define H-Bus Streams 16-31 for 8 Mbits/s
MI,HSH,IDR ;Engage

(continued)

(continued)

(continued)

Clock failure,
;synchronizes to a bit clock on local reference 1, but
requires the main divider
;with external input (assumes a CLAD is between the
divider and 4MHzIn).

;

2.048 MHz

;*******Set up Fr amers
;
MD,IDR,00h ;This sequence sets up Group A
MI,FRLA,IDR ; to start coincident
MI,FRLB,IDR ; with the Frame
MI,FRPH,IDR ; boundary and Group B
MD,IDR,0F0h ; to start halfway through
MI,FRHA,IDR ; the Frame. The Groups
MD,IDR,0F4h ; operate in normal framing mode
MI,FRHB,IDR ; at 8 Mbits/s and are Double Byte wide.

;Note: FRPH sets up the correct routing.
;
;*******Connect the T8100 to the outside world
;
MD,MCR,0Eh ; Enable H-Bus St reams & Clock, Local Streams,

local

; Clocks including Framers
;
;*******END OF EX AMPLE #1

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3.3 Using the LAR, AMR, and IDR for Connections

3.3.3 Programming Examples

;*******EXAMPLE #2 - Setting up Local Connections
;
; Use 8 Mbits/s rate set up from Example #1...
; Send data from Stream 7/Time Slot 60 to Stream 0/Time Slot 2
; The data is coming from Data Location Stream 07h, Time Slot 3Ch, and is
; being accessed by Connection Memory Location Stream 00h, Time Slot 02h
; in the next frame (unframed operation).
;
MD,LAR,1Dh ;Set up lower address, i.e., Time Slot 29
MD,AMR,43h ; Set up upper address bits (Stream 3), and

MI,IDR,07h ;Put a “7” in the Time Slot field of connection location

;
;Syntactically, “MI,IDR,data” is a special case since IDR is not the final recipient
of the data
;
MD,AMR,53h ;Maintain the same upper address, but get ready to load the

MI,IDR,0001_1110b ;This decodes as follows: XCS bit low, pattern mode off

;
;*******END OF EXAMPLE #2
;*******EXAMPLE #3 - Setting up H-Bus Connections
;
; Use rate set up from Example #1...
; Send data from Stream 14/Time Slot 7 of the H.100 bus to Stream 3/Time Slot 29
; on the Local side. The data is coming in at 4 Mbits/s from E-CAM, and is sent
; out at 8 Mbits/s to through L-CAM. We’re using Data Memory location 49 to hold
; the actual data. LAR is not used for the CAM connection setups; it is used for
; reading specific CAM locations or writing and reading the associated Data
; Memory Locations.
;
;******Set up the “from” connection
;
MD,AMR,0B0h ;Point to the Time-Slot holding register
MI,IDR,07h ;This is the Time-Slot value (7) for the H-Bus address
MD,AMR,0B1h ;Point to the upper bits of the connection
MI,IDR,000_01110b :Set up a write into data memory from ECTF bus,

MD,AMR,0B2h ;Point to tag field
MI,IDR,31h ;Use location 49 of the associated Data RAM to store the data
;
MD,AMR,0E0h ;Write to next free location in the Even CAM
MI,IDR,0E0h ;The command is executed with the indirect to IDR which

(continued)

(continued)

(continued)

point to the

; the Time Slot field of the connection memory

3,29

; remaining connection info (upper bits +

control)

; (not set), frame bit low, time slot enabled,

and stream = 1110b (14)

; disable pattern mode, minimum delay,
; and set stream number equal to 01110b (14).

;uses the same command value as in the AMR.

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3.3.3 Programming Examples

;
;**Optional: Test CAM Busy bit**
TEST:
MD,ACC,MCR ;Move MCR contents into (host’s) accumulator (for example)
AND,01h ;Logical AND, i.e., mask off all but LSB of the MCR register
JNZ TEST ;If the LSB is zero (not busy), continue, else jump back and

;
CONTINUE:
;
;******Set up the “to” connection
;
MD,AMR,0B0h ;Point to the Time-Slot holding register
MI,IDR,1Dh ;This is the Time-Slot value (29) for the Local address
MD,AMR,0B1h ;Point to the upper bits of the connection
MI,IDR,100_00011b :Set up a read from data memory to Local pins,

MD,AMR,0C2h ;Point to tag field
MI,IDR,31h ;Use location 49 of the associated Data RAM to store the data
;
MD,AMR,0E3h ;Write to next free location in the Local CAM
MI,IDR,0E3h ;The command is executed with the indirect to IDR
;
;
;
;**CAM Busy bit can be tested here**
;
;
;*******END OF EX AMPLE #3

(continued)

(continued)

(continued)

;retest

; disable pattern mode, minimum delay, and set
; stream number equal to 00011b (3).

3.2.4 Miscellaneous Commands

These commands (i.e., 0x70, 0xF8, all reset commands in the AMR register) require two writes: first the value is
written to the AMR register; then the same value is written to the IDR register. After writing to the IDR register, the
command will be executed.

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4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso­lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.

Description Symbol Min Max Unit

Supply Voltage V

DD

XTALIN and XTALOUT Pins — V
Voltage Applied to I/O Pins — V
Operating Temperature:

208-pin SQFP
217-pin BGA

Storage Temperature T

—
—

stg

4.2 Handling Precautions

Although protection circuitry has been designed into this device , proper precautions should be taken to avoid expo­sure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM)
and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage
thresholds are dependent on the circuit parameters used to defi ne the model. No industry-wide standard has been
adopted for CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and
therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using
these circuit parameters:

— 3.6 V

SS

– 0.5 VDD + 3.4 V

SS

0

−40

V

DD

70
85

–55 125 °C

V

°C
°C

HBM ESD Threshold Voltage

Device Rating

T8100 2500 V

66 Lucent Technologies Inc.

Preliminary Data Sheet

V

SS

18 pF

18 pF

1 M

Ω

16.384 MH

Z

T8100

XTALIN

XTALOUT

August 1998

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(continued)

4.3 Crystal Oscillator

Table 55. Crystal Oscillator

The T8100 requires a 16.384 MHz clock source. To supply this, a 16.384 MHz crystal can be connected between
the RCLK and XTALOUT pins. External 18 pF, 5% capacitors must be connected from XTALIN and XTALOUT to

. Crystal specifications are shown below. The ±32 ppm tolerance is the suggested value if either the DPLL is

V

SS

used or fallback to the oscillator is enabled while mastering the bus. Otherwise, a crystal with a lesser tolerance
can be used.

Parameter Value

Frequency 16.384 MHz
Oscillation Mode Fundamental, Parallel Resonant
Effective Series Resistance 40 Ω maximum
Load Capacitance 14 pF
Shunt Capacitance 7 pF maximum
Frequency Tolerance and Stability 32 ppm

Table 56. Alternative to Crystal Oscillator

When XTALIN is driven by a CMOS signal instead of an oscillator, it must meet the requirements shown below:

Parameter Value

Frequency 16.384 MHz
Maximum Rise or Fall Time 5 ns
Minimum Pulse Width

Low High

20 ns 20 ns

5-6390(F)

4.4 dc Electrical Characteristics, H-Bus (ECTF H.100 Sp ec., Rev. 1.0)

4.4.1 Electrical Drive Specifications—CT_C8 and /CT_FRAME

Table 57. Electrical Drive Specifications—CT_C8 and /CT_FRAME

= 3.3 and V

V

DD

Parameter Symbol Condition Min Max Unit

Output High Voltage V
Output Low Voltage V
Positive-going Threshold Vt+ — 1.2 2.0 V
Negative-going Threshold Vt– — 0.6 1.6 V
Hysteresis (Vt+ – Vt–) V
Input Pin Capacitance C

PCI-compliant data line I/O cells are used for the CT bus data lines. (See PCI Specification, Rev. 2.1, Chapter 4.)
/C16, /C4, C2, SCLK, SCLKX2

CT_C8 and /CT_FRAME signals, though this is not explicitly stated as a part of the H.100 Specification.

Lucent Technologies Inc. 67

= 0.0 unless otherwise specified.

SS

, and /FR_COMP all use the same driver/receiver pairs as those specified for the

OH

OL

HYS

IN

I

= –24 mA 2.4 3.3 V

OUT

I

= 24 mA –0.25 0.4 V

OUT

—0.4—V
— — 10 pF

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(continued)

4.5 dc Electrical Characteristics, All Other Pins

Table 58. dc Electrical Characteristics, All Other Pins

= 3.3 and V

V

DD

= 0.0 unless otherwise specified.

SS

Description Symbol Min Typ Max Condition Unit

Supply Current I
Supply Voltage V
Input High Voltage V
Input Low Voltage V
Input Current I
Input Capacitance (input only) C
Input Capacitance (I/O pins) C
Input Clamp Voltage V
Output High Voltage V
Output Low Voltage V
Output Short-circuit Current I

* Circuit simulation indicates a worst-case current of 450 mA. This parameter is not tested in production.

DD

DD

IL
IH
I

I

IO

C
OH
OL

OS

— 270 450* — mA

3.0 — 3.6 — V
——0.8 — V

2.0 — — — V
—— 1 — µA
—— 5 — pF
——10 — pF
— — –1.0 — V

2.4 — — — V
——0.4 — V
— — 100 VOH tied to GND mA

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(continued)

4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)

4.6.1 Clock Alignment

FRAME BOUNDARY

/CT_FRAME (A/B)

CT_C8 (A/B)

/FR_COMP

/C16

C2

/C4

SCLK

(2.048 MHz)

(2.048 MHz MODE)

(4.096 MHz MODE)

(4.096 MHz MODE)

(8.192 MHz MODE)

(8.192 MHz MODE)

SCLKx2

SCLK

SCLKx2

SCLK

SCLKx2

5-6119F

Figure 19. Clock Alignment

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4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)

(continued)

(continued)

4.6.2 Frame Diagram

FRAME BOUNDARY

125 µs

/CT_FRAME

CT_C8

CT_DX

TIME

SLOT

Note: Bit 1 is the MSB. Bit 8 is the LSB. MSB is always transmitted first in all transfers.

812345678 123456781

1270

5-6120F

Figure 20. Frame Diagram

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(continued)

4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)

4.6.3 Detailed Timing Diagram

FRAME BOUNDARY

tFS tFH

/CT_FRAME

tFP

tC8H tC8I

CT_C8

tZDO tDOD

DATA OUT

tS127 BIT 8 tS0 BIT 1

tDOZ

tDV

(continued)

1 BIT CELL

2.0 V

0.6 V

2.0 V

0.6 V

tC8P

2.4 V

0.4 V

DATA IN

1.4 V

tSAMP

tDIV

5-6121F

Figure 21. Detailed Timing Diagram

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4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)

(continued)

(continued)

4.6.4 ac Electrical Characteristics, Timing, H-Bus (H.100, Spec., Rev. 1.0)

Table 59. ac Electrical Characteristics, Timing, H-Bus (H.100, Spec., Rev. 1.0)

Symbol Parameter Min Typ Max Unit Notes

— Clock Edge Rate (all clocks) 0.25 — 2 V/ns 1, 2, 4
tC8P Clock CT_C8 Period 122.066 – Φ — 122.074 + Φ ns 2, 4, 5
tC8H Clock CT_C8 High Time 49 – Φ — 73 + Φ ns 2, 4, 6

tC8L Clock CT_C8 Low Time 49 – Φ — 73 + Φ ns 2, 4, 6

tSAMP Data Sample Point — 90 — ns 2, 4, 9

tDOZ Data Output to HiZ Time –20 — 0 ns 2, 3, 4, 7, 11
tZDO Data HiZ to Output Time 0 — 22 ns 2, 3, 4, 7, 11
tDOD Data Output Delay Time 0 — 22 ns 2, 3, 4, 7

tDV Data Valid Time 0 — 69 ns 2, 3, 4, 8, 10

tDIV Data Invalid Time 102 — 112 ns 2, 4

tFP /CT_FRAME Width 90 122 180 ns 2, 4
tFS /CT_FRAME Setup Time 45 — 90 ns 2, 4
tFH /CT_FRAME Hold Time 45 — 90 ns 2, 4

Φ Phase Correction 0 — 10 ns 12

1. The rise and fall times are deter m ined by the edge rate in V/ns. A maximum edge rate is the fastest rate at which a clock transitions.
CT_NETREF has a separate requirement. (See Section 2.4 Clocking Section.)

2. Measuring conditions, data lines: V
edge rate = 1 V/ns measuring conditions, clock and frame lines: Vt+ (test high voltage) = 2.0 V, Vt– (test low voltage) = 0.6 V, input signal
edge rate = 1 V/ns.

3. Test load—200 pF.

4. When RESET is active, every output driver is 3-stated.

5. t C 8P min imum and maximum are under free-run conditions assuming ±32 ppm clock accuracy.

6. N onc umul ative, tC8P requirements still need to be met.

7. Measured at the transmitter.

8. Measured at the receiver.

9. For reference only.

10. tDV = maximum cloc k cab le dela y + max. data cab le dela y + max. data HiZ to output time = 12 ns + 35 ns + 22 ns = 69 ns . Max. c lo c k cab l e
delay and maximum data cable delay are worst-case numbers based on electrical simulation.

11. tDOZ and tZDO apply at every time-slot boundary.

12. F (phase correction) results from PLL timing corrections.

(threshold voltage) = 1.4 V, VHI (test high voltage) = 2.4 V, VLO (test low voltage) = 0.4 V, input signal

TH

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(continued)

4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)

4.6.5 Detailed Clock Skew Diagram

Vt+

CT_C8_A

tSKC8

Vt+

CT_C8_B

Figure 22. Detailed Clock Skew Diagram

CT_C8_A

COMPATIBILITY

CLOCKS

(continued)

Vt+

tSKCOMP

Vt+

Vt–

tSKCOMP

5-6122F

4.3.6 ac Electrical Characteristics, Skew Timing, H-Bus (H.100, Spec., Rev. 1.0)

Table 60. ac Electrical Characteristics, Skew Timing, H-Bus (H.100, Spec., Rev. 1.0)

Symbol Parameter Min Typ Max Unit Notes

tSKC8 Max Skew Between CT_C8 A and B — — ±10

ns 1, 2, 3, 4

±Φ

tSKCOMP Max Skew Between CT_C8_A and An y Compatibility Clock — — ±5 ns 1

1. Test load—200 pF.

2. Assumes A and B master s in adjacent slots.

3. When static skew is 10 ns and, in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum
skew of 30 ns will occur during that clock cycle.

4. Meeting the skew requirements in Table 10 and the requirements of Section 2.3 H-Bus Section could require the PLLs generating CT_C8
to have different time constants when acting as primary and secondar y clock masters.

4.6.7 Reset and Power On

Table 61. Reset and Power On

Symbol Parameter Min T yp Max Unit

tRD Output Float Delay from Reset Active — — 1 µs
tRS Reset Active from Power Good — 5 — µs

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4 Electrical Characteristics

(continued)

4.7 ac Electrical Characteristics, Local Streams, and Frames

Table 62. ac Electrical Characteristics, Local Streams, and Frames

Symbol Description Min Max Condition Unit

tPD Data Propagation Delay 0 20 Load = 50 pF ns

tS Data Setup Time 10 — — ns

tH Data Hold Time 5 — — ns

tOFF Data 3-state Off Time — 20 — ns

tD0 Data Bit 0 3-state –20 0 — ns

LOCAL SELECTED CLOCKS LSC[3:0]

3/4 POINT

(NONINVERTED SHOWN):

16.384 MHz

8.192 MHz

4.096 MHz

3/4 POINT

3/4 POINT

2.048 MHz

LDO

0

LDI

0

LDO

0

LDO

0

tD0

LDO

7

tS tH

LDI

7

tD0

tD0

tPD

LDO

6

LDI

6

LDO

7

tS tH

LDI

7

tPD

LDO

7

tS

tPD

LOCAL DATA STREAMS:

8.192 Mbits/s

8.192 Mbits/s

4.096 Mbits/s

4.096 Mbits/s

2.048 Mbits/s

2.048 Mbits/s

FRAME GROUP:

Note: LDO7 is the MSB, LDO0 is the LSB. MSB is always transmitted first in all transfers.

Figure 23. ac Electrical Characteristics, Local Streams, and Frames

LDI

LDO

5

5

LDI

LDO

4

LDI

4

LDO

6

tPD

tH

7

LDI

LDO

3

LDO

5

6

LDO

6

5-6548F

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4 Electrical Characteristics

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4.8 ac Electrical Characteristics, Microprocessor Timing

4.8.1 Microprocessor Access

Intel

For

write and read cycles, when RDY is low, wait-states are inserted. RDY is brought high when tIACC is met.

This is true for both read and write cycles.

ALE

CS

WR

RDY

(RDY DRIVEN LOW DURING

MEMORY ACCESSES ONLY)

Intel

Multiplexed Write and Read Cycles

A[1:0] D[7:0]AD[7:0]

tAS tAH tDS tDH

tRDY

tIACC

5-6124.bF

ALE

CS

RD

RDY

Figure 24. Microprocessor Access

A[1:0]AD[7:0]

tAS tAH

tRDY

(RDY DRIVEN LOW DURING

MEMORY ACCESSES ONLY)

Figure 25. Microprocessor Access

Intel

Multiplexed Write Cycle

tDV

tIACC

Intel

Multiplexed Read Cycle

D[7:0]

tDI

5-6125.bF

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4 Electrical Characteristics

(continued)

4.8 ac Electrical Characteristics, Microprocessor Timing

4.8.2 Microprocessor Access

A[1:0]

R/W

DS (RD)

CS

DTACK (RDY)

D[7:0]

Motorola

Write and Read Cycles

tAS

tMACC

tDS

(continued)

tAH

tDH

5-6126.bF

A[1:0]

R/W

DS (RD)

CS

DTACK (RDY)

D[7:0]

Figure 26. Microprocessor Access

tAS

tMACC

Figure 27. Microprocessor Access

Motorola

tDV

Motorola

Write Cycle

tAH

tDI

5-6127.bF

Read Cycle

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4.8 ac Electrical Characteristics, Microprocessor Timing

Intel

4.8.3 Microprocessor Access

A[1:0]

CS

WR

RDY

D[7:0]

Figure 28. Microprocessor Access

A[1:0]

CS

Demultiplexed Write Cycle

tAS

tRDY

(RDY DRIVEN LOW
DURING MEMORY
ACCESSES ONLY)

tAS

tIACC

tDS tDH

Intel

Demultiplexed Write Cycle

(continued)

tAH

5-6128.cF

tAH

RD

(RDY DRIVEN LOW

RDY

DURING MEMORY
ACCESSES ONLY)

D[7:0]

Figure 29. Microprocessor Access

tRDY

tIACC

tDV tDI

Intel

Demultiplexed Read Cycle

Table 63. Microprocessor Access Timing (See Figure 24 through Figure 29.)

Symbol Description Min Max Condition Unit

tAS Address Setup Time 7 — Load = 100 pF ns
tAH Address Hold Time 0 — — ns
tDV Data Valid — 13 — ns

tDI Data Invalid 0 11 — ns

Intel

tRDY Active to Ready Low (

tIACC Active to Ready High (

tMACC Active to

DTACK

Low (

) — 14 Memory Access ns

Intel

) 145 255 Memory Access ns

Motorola

)—

145

14

255

Register Access

Memory Access

tDS Data Setup Time 8 — — ns

tDH Data Hold Time 0 — — ns

5-6128.bF

ns

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5 Outline Diagram

5.1 208-Pin Square Quad Flat Package (SQFP)

30.60 ± 0.20

28.00 ± 0.20

Preliminary Data Sheet

August 1998

PIN #1 IDENTIFIER ZONE

1

52

53 104

DETAIL BDETAIL A

157208

156

28.00

± 0.20

30.60

± 0.20

105

3.40 ± 0.20

4.10 MAX

0.50 TYP

1.30 REF

0.25

GAGE PLANE

SEATING PLANE

0.50/0.75

DETAIL A DETAIL B

Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design

efforts, please contact your Lucent Technologies Microelectronics Group Account Manager.

0.25 MIN

0.17/0.27

SEATING PLANE

0.08

0.090/0.200

M

0.10

5-2196(F)

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5 Outline Diagram

(continued)

5.2 217-Pin Ball Grid Array (PBGA)

IDENTIFIER ZONE

TOP VIEW

A1 BALL

MOLD

COMPOUND

PWB

0.36 ± 0.04

23.00 ± 0.20
+0.70

19.50

–0.00

1.17 ± 0.05

19.50

+0.70
–0.00

± 0.20

2.13 ± 0.19

23.00

SIDE VIEW

BOTTOM VIEW

A1 BALL

CORNER

6 Ordering Information

SOLDER BALL0.60 ± 0.10

16 SPACES @ 1.27 = 20.32

U
T
R
P
N

M

L

K

J

H

G

F
E
D
C
B
A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

0.75 ± 0.15

16 SPACES

@ 1.27 = 20.32

SEATING PLANE

0.20

5-6562(F)

Device Part No. Description Package Comcode

T8100- - -SC

T8100- - -BAL

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H.100 Interface 208-Pin SQFP 108125873
H.100 Interface 217-Pin BGA 108194184

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Preliminary Data Sheet

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Appendix A. Application of Clock Modes

In the diagrams that follow, four clock modes are illus­trated using Figure 12, the T8100 clocking diagram, as
the basis of each illustration. The key signal paths are
shown in solid lines, and unused paths with narrow
dashes. Two examples also indicate fallback paths. A
register profile (programming values) for all four exam­ples is on the last page of the appendix.

In Figure 30, the T8100 is operating as a bus master,
so it must link to either an 8 kHz recovered frame refer­ence or 2.048 MHz recovered bit clock reference from
the E1 framers. In addition, the T8100 can provide one
of the basic resource clocks to run the framers. In
this case, the TCLK is selecting the T8100’s

16.384 MHz oscillator. The framers are returning a

2.048 MHz bit clock which is selected through the cloc k
selector. It is not divided, so the main divider is
bypassed (divide-by-1), the clock is smoothed
through an external DJAT, and the smooth 2.048 MHz
signal is routed to PLL #1 through the clock resource
selector. PLL #1 multiplies the 2.048 MHz input up to

65.536 MHz which, in turn, runs the rest of the T8100,
all bus clocks, and the local clocks (if desired). If the
T8100 is not providing NETREF generation, then the
NETREF from the bus is routed to the local clocks via
the NETREF internal/external selector. Since the
NETREF generation resources are not needed here,
the TODJAT and FROMDJAT pins are free for use with
the general-purpose register as bits GP6 and GP7,
respectively.

Figure 31 shows the T1 version of a b us master. In this
scenario, a 1.544 MHz recovered bit clock from the
framers is routed to a multiclock adapter (with built-in
jitter attenuation) which produces smooth 4.096 MHz
and 3.088 MHz outputs. The 4.096 MHz is routed
up to PLL #1 for a times-16 rate multiplication to

65.536 MHz. This drives the bus clocks and the local
clocks. The smooth 3.088 MHz is also rate multiplied
times 8. This produces a 24.704 MHz clock. This is

divided back down to produce a smooth 12.352 MHz
which is fed back to the framers. (PLL outputs produce
one tightly bound edge and one with significant phase
jitter. Dividing a higher-frequency signal based on its
clean edge produces a lower frequency with two clean
edges.)

Figure 32 shows an H­In this example, the C16 differential clocks provide the
main source for PLL #1. The 16.384 MHz signal is
divided down to 4.096 MHz and then rate multiplied up
to 65.536 MHz for driving the rest of the T8100. The
frame sync for the state machines is derived from the
/FRAME and C16 inputs as well as the state informa­tion provided by C2 and /C4.

Note:

The bit slider is enabled for a smooth phase
alignment between the internal frame and the
frame sync.

The bus clocks are not driven, but the local clocks are
available. A path for NETREF is shown as well, also
based on a 2.048 MHz input. The signal is smoothed
and then divided down to an 8 kHz signal via the
NETREF divider . The internal oscillator is again chosen
for routing to the framers via TCLK.

Figure 33 shows an H­cal to the E1 case with regard to slaving, and a
NETREF path is illustrated in this example, too. The
NETREF divider has been changed to accommodate
the 1.544 MHz bit clock rate. The primary difference is
the use of the C16 clock through the main divider to
generate a 2.048 MHz signal which can be routed off­chip and adapted to a 1.544 MHz signal using an exter­nal device. The 1.544 MHz signal is returned to the
T8100 via the 3MHzIN for rate multiplication up to

24.704 MHz and then division to a clean 12.352 MHz
signal which is routed to the framers via TCLK.

MVIP

slave arrangement for E1.

MVIP

slave for T1. This is identi-

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Appendix A. Application of Clock Modes

TODJAT/GP6 FROMDJAT/GP7

GP6
GP7

FRAME SYNC

RESOURCE

DIVIDE-BY-N

DIVIDE REGISTER

DIVIDE-BY-N

DIVIDE REGISTER

(FALLBACK PATH)

DJAT BYPASS

(AND GP6/7 ENABLE)

4 MHz

2 MHz

DPLL

MAIN

PRIREFO 4MHzIN 3MHzIN

2MHz DJAT

CLOCK

RESOURCE

SELECT

DIVIDE REGISTER

/CT_FRAME A
/CT_FRAME B

/FR_COMP

2.048 MHz
LREF0

LREF7

CT_NETREF

CT_C8

CLKB
/C16±

SCLK

SCLK2

XTALIN

/C4

NET­REF
SEL.

÷ BY 8

NETREF
SELECT

FRAME

SEL.

CLOCK

SEL.

CLOCK

SEL.
AND

INPUT
STATE
MACH.

C2

DIVIDE

BY 4

(continued)

NETREF

DIVIDE-BY-N

PLL #1 BYPASS

PLL #1

x32

RATE SELECT

PLL #2 BYPASS

RATE SELECT

NETREF

INT/EXT
SELECT

BIT SLIDER
CONTROLS

x16

PLL #2

x8

x16

65.536 MHz

TCI

SELECT

BIT SLIDER

STATE

MACHINES

DIVIDE

BY 2

TCLK

FRAMERS

EN_NETREF

NETREF

EN_A

C6

FRAME
EN_B

C8

FRAME

COMPATIBILITY

CLOCKS DIRECTION

16.384 MHz

2.048 MHz

4.096 MHz

2.048 MHz

4.096 MHz

8.192 MHz
SCSEL

4.096 MHz

8.192 MHz

FRAME

SEC8K
FRAME

2.048 MHz

4.096 MHz

8.192 MHz

16.384 MHz
DPLL#2-2

L_SC CTL

TCLK

ENABLE

CT_NETREF
CT_C8A
/CT_FRAMEA
CT_C8B
/CT_FRAMEB

/CT16 ±
C2

/C4

SCLK

SCLK2

/FR_COMP

L_SC0

(1 OF 4

L_SC[1:3]

NOT SHOWN)

5-6129aF(r3)

Figure 30. E1, CT Bus Master, Compatibility Clock Master, Clock Source = 2.048 MHz from Trunk

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Appendix A. Application of Clock Modes

TODJAT/GP6 FROMDJAT/GP7

GP6
GP7

FRAME SYNC

RESOURCE

DIVIDE-BY-N

DIVIDE REGISTER

DIVIDE-BY-N

DIVIDE REGISTER

(FALLBACK PATH)

DIVIDE-BY-N

DIVIDE REGISTER

4 MHz

2 MHz

DPLL

MAIN

PRIREFOUT 4MHzIN 3MHzIN

CLOCK

RESOURCE

SELECT

JITTER ATTENUATED

MULTICLOCK ADAPTER

/CT_FRAME_A
/CT_FRAME_B

/FR_COMP

1.544 MHz
L_REF0

L_REF7

CT_NETREF

CT_C8

CLKB
/C16±

/C4

SCLK

SCLK2

XTALIN

C2

(XTALIN STILL DRIVES

OTHER INTERNALS.)

NETREF

SELECT

FRAME

SEL.

CLOCK

SEL.

NET­REF
SEL.

÷ BY 8

CLOCK

SEL.
AND

INPUT
STATE
MACH.

DIVIDE

BY 4

(continued)

NETREF

BIT SLIDER

CONTROL

PLL #1 BYPASS

PLL #1

x16

x32

RATE SELECT

PLL #2 BYPASS

RATE SELECT

PLL #2

x8

x16

NETREF

INT/EXT

SELECT

65.536 MHz

DIVIDE

TCI

SELECT

BIT SLIDER

STATE

MACHINES

BY 2

TCLK

FRAMERS

EN_NETREF

NETREF

EN_A

C6

FRAME

EN_B

C8
FRAME
COMPATIBILITY

CLOCKS DIRECTION

16.384 MHz

2.048 MHz

4.096 MHz

2.048 MHz

4.096 MHz

8.192 MHz
SCSEL

4.096 MHz

8.192 MHz
FRAME

SEC8K

FRAME

2.048 MHz

4.096 MHz

8.192 MHz

16.384 MHz
DPLL#2-2

L_SC CTL

TCLK

ENABLE

CT_NETREF
CT_C8_A
/CT_FRAME_A
CT_C8_B
/CT_FRAME_B

/CT16 ±
C2

/C4

SCLK

SCLK2

/FR_COMP

L_SC0

(1 OF 4

L_SC[1:3]

NOT SHOWN)

5-6130aF(r4)

Figure 31. T1, CT Bus Master, Compatibility Clock Master, Clock Source = 1.544 MHz from Trunk

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Appendix A. Application of Clock Modes

2 MHz DJAT

TODJAT/GP6 FROMDJAT/GP7

GP6
GP7

FRAME SYNC

RESOURCE

DIVIDE-BY-N

DIVIDE REGISTER

DIVIDE-BY-N

DIVIDE REGISTER

(FALLBACK PATH)

DJAT BYPASS

(AND GP 6/7 ENABLE)

4 MHz

2 MHz

DPLL

MAIN

PRIREFOUT 4MHzIN 3MHzIN

DIVIDE REGISTER

CLOCK

RESOURCE

SELECT

DIVIDE-BY-N

CT_FRAME_A
CT_FRAME_B

/FR_COMP

L_REF0

2.048 MHz
L_REF7

CT_NETREF

CT_C8

CLKB
/C16±

SCLK

SCLK2

XTALIN

/C4

NET-

REF
SEL.

÷ BY 8

NETREF
SELECT

FRAME

SEL.

CLOCK

SEL.

CLOCK

SEL.
AND

INPUT
STATE
MACH.

C2

DIVIDE

BY 4

(continued)

NETREF

BIT SLIDER

CONTROLS

PLL #1 BYPASS

PLL #1

x16

x32

RATE SELECT

PLL #2 BYPASS

RATE SELECT

NETREF
SELECT

PLL #2

x8

x16

INT/EXT

65.536 MHz

TCI

SELECT

BIT SLIDER

STATE

MACHINES

DIVIDE

BY 2

TCLK

FRAMERS

EN_NETREF

NETREF

EN_A

C6

FRAME

EN_B

C8

FRAME

COMPATIBILITY

CLOCKS DIRECTION

16.384 MHz

2.048 MHz

4.096 MHz

2.048 MHz

4.096 MHz

8.192 MHz
SCSEL

4.096 MHz

8.192 MHz

FRAME

SEC8K

FRAME

2.048 MHz

4.096 MHz

8.192 MHz

16.384 MHz
DPLL#2-2

L_SC CTL

TCLK

ENABLE

CT_NETREF
CT_C8_A
/CT_FRAME_A
CT_C8_B
/CT_FRAME_B

/CT16 ±
C2

/C4

SCLK

SCLK2

/FR_COM

L_SC0

(1 OF 4

L_SC[1:3]

NOT SHOWN)

5-6131aF(r3)

Figure 32. E1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF

Source = 2.048 MHz from Trunk

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Appendix A. Application of Clock Modes

1.5 MHz DJAT

CT_FRAME_A
CT_FRAME_B

/FR_COMP

L_REF0

1.544 MHz
L_REF7

CT_NETREF

CT_C8

CLKB

/16±

SCLK

SCLK2

XTALIN

/C4

TODJAT/GP6

GP6

NET-

REF
SEL.

÷ BY 8

NETREF
SELECT

FRAME

SEL.

CLOCK

SEL.

CLOCK

SEL.
AND

INPUT
STATE
MACH.

C2

DIVIDE

BY 4

GP7

FRAME SYNC

RESOURCE

DIVIDE-BY-N

DIVIDE REGISTER

DIVIDE-BY-N

DIVIDE REGISTER

(FALLBACK PATH)

DJAT BYPASS

(AND GP6/7 ENABLE)

4 MHz

2 MHz

DPLL

MAIN

PRIREFOUT 4MHzIN 3MHzIN

JITTER ATTENUATED

MULTICLOCK ADAPTER

FROMDJAT/GP7

DIVIDE REGISTER

CLOCK

RESOURCE

SELECT

(continued)

NETREF

DIVIDE-BY-N

PLL #1 BYPASS

RATE SELECT

PLL #2 BYPASS

NETREF
INT/EXT
SELECT

BIT SLIDER

CONTROL

PLL #1

x16

x32

PLL #2

x8

x16

RATE SELECT

65.536 MHz

TCLI

SELECT

BIT SLIDER

STATE

MACHINES

DIVIDE

BY 2

TCLK

FRAMERS

EN_NETREF

NETREF

EN_A

C8

FRAME

EN_B

C8

FRAME

COMPATIBILITY

CLOCKS DIRECTION

16.384 MHz

2.048 MHz

4.096 MHz

2.048 MHz

4.096 MHz

8.192 MHz
SCSEL

4.096 MHz

8.192 MHz

FRAME

SEC8K

FRAME

2.048 MHz

4.096 MHz

8.192 MHz

16.384 MHz
DPLL#2-2

L_SC CTL

TCLK

ENABLE

CT_NETREF
CT_C8_A
/CT_FRAME_A
CT_C8_B
/CT_FRAME_B

/CT16 ±
C2

/C4

SCLK

SCLK2

/FR_COMP

L_SC0

(1 OF 4

L_SC[1:3]

NOT SHOWN)

5-6132aF(r5)

Figure 33. T1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF

Source = 1.544 MHz from Trunk

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Appendix A. Application of Clock Modes

Table 64. Clock Register Programming Profile for the Four Previous Examples

Register Name CT Bus Master (E1) CT Bus Master (T1) CT Bus Slave (E1) CT Bus Slave (T1)

CKM 0010_1000b 0010_1000b 1100_0101b 1100_0101b
CKN 0110_0000b 0110_0000b 1000_1111b 1000_1111b

CKP 0010_0001b 0110_0001b 0010_0000b 0110_0000b

CKR 0001_0000b 0000_0000b 0100_0000b 0100_0000b

CKS 0000_0000b 0000_0000b 0000_0000b 0000_0000b
CK32 1001_0100b 1001_0100b 0010_0100b 0010_0100b
CK10 1101_1111b 1101_1111b 1000_0000b 1011_1101b

CKMD 0000_0000b 0000_0000b 0000_0000b 0000_0111b
CKND 0000_0000b 0000_0000b 1111_1111b 1100_0000b
CKRD 0000_0000b 0000_0000b 0000_0011b 0000_0011b

Watchdog: CKW 0011_1001b 0011_1001b 0011_1001b 0011_1001b

The programming displays how simil ar the four basic modes of operation are. Local outputs (CK32 and CK10) are
obviously not constrained by the mode of operation. The primary difference between E1 and T1 is in the use of the
PLL #2 (which is optional). The primary difference between master and slave is in the clock path to PLL #1, which
is covered by registers CKM, CKR, CKMD, and CKRD.

Note:

The watchdogs have been set up to monitor all CT Bus signals, though fallback (to the oscillator) is shown as
enabled in all examples. It is recommended that the default condition, CKS = 0x00, be used for systems which do
not have specific fallback clocking schemes. Also, while programming the T8100 on powerup, it is recommended
that the watchdogs are disabled (CKW = 0x00) until the dev ice is fully programmed to pre v ent f alse error conditions
(uninitialized clocks, for example) from changing the operating mode.

CKR does include an example of running PLL #1 at X32 for E1 master and X16 for all other cases.

(continued)

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Preliminary Data Sheet

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Appendix B. Minimum Delay and Con­stant Delay Connections

B.1 Connection Definitions

Forward A forward connection is defined as one
Connection in which the output (to) time slot has a

greater v alue than th e input (
slot, or put another way, the delta

between them i s positive.
Reverse A reverse connection is defined as one
Connection in which the input (

a lesser value than the output (to) time

slot, and the delta between them is

negative.

So, for example, going from TS(1) to TS(38) is a for­ward connection, and the TS∆ is +37, but going from
TS(38) to TS(1) is a reverse connection, with a TS∆ of
–37:

where TS∆ = TS(to) – TS(
Similarly, a delta can be introduced for streams which

will have a bearing in certain exceptions (discussed
later):

STR∆ = STR(to) – STR(
There is only one combination which forms a TS∆ of

+127 or –127:
TS∆ = TS(127) – TS(0) = +127, and

TS∆ = TS(0) – TS(127) = –127,
but there are two combinations which form TS∆s of

+126 or –126:
TS∆ = TS(127) – TS(1) = TS(126) – TS(0) = +126, and

TS∆ = TS(1) – TS(127) = TS(0) – TS(126) = –126,
there are three combinations which yield +125 or –125,

and so on.

from

from

from

).

)

from

) time

) time slot has

The user can utilize the TS∆ to control the latency of
the resulting connection. In some cases, the latency
must be minimized. In other cases, such as a block of
connections which must maintain some relative integ­rity while crossing a frame boundary, the required
latency of some of the connections may exceed one
frame (>128 time slots) to maintain the integrity of this
virtual frame.

The T8100 contains several bits for controlling latency.
Each connection has a bit which is used for selecting
one of two alternating data buffers. These bits are set
in the local connection memory for local switc hing or in
the tag register files of the CAM section for H-Bus
switching. There are also 2 bits in the CON register,
address 0x0E, which can control the buffer selec tion on
a chip-wide basis. Bit 1 of the register overrides the
individual FME bits. Bit 0 becomes the global, chip­wide, FME setting.

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Appendix B. Minimum Delay and Con­stant Delay Connections

B.2 Delay Type Definitions

Constant Delay In the T8100, this is a well-defined,

predictable, and linear region of
latency in which the to time slot is at
least 128 time slots after the
slot, but no more than 256 time slots
after the

Mathematically, constant delay latency is described as
follows*, with L denoting latency, and FME set to the
value indicated:

Forward Connections, FME = 1: L = 128 + TS∆ (0 ≤
TS∆ ≤ 127)

Reverse Connections , FME = 0: L = 256 + TS∆ (–127 ≤
TS∆ ≤ 0)

Example: Switching from TS(37) to TS(1) as a con-

stant delay, the delta is –36, so FME is
set to 0 and the resulting latency is 256 –
36 = 220 time slots. Thus, the connec­tion will be made from TS(37) of
Frame(n) to TS(1) of Frame(n + 2).

Simple
Summary:

Use constant delay for latencies of 128
to 256 time slots, set FME = 1 for f orward
connections, set FME = 0 for reverse
connections.

* Since TS∆ = TS(to) – TS(from), the user can modify the equations

to solve for either TS(to) or TS(from).

from

(continued)

time slot.

from

time

Minimum Delay This is the most common type of

switching, but has a shorter range
than constant delay, and the user must
be aware of exceptions caused by
interactions between the T8100's
internal pipeline and the dual buffer­ing. The to time slot is at least three
time slots after the

from

time slot, but

no more than 128 time slots after the

from

time slot. Exceptions exist at

TS∆s of +1, +2, –126, and –127.

Forward Connections, FME = 0: L = TS∆ (3 ≤ TS∆ ≤

127)
Reverse Connections , FME = 1: L = 128 + TS∆ (–125 ≤

TS∆ ≤ 0)
Example: Using the same switching from the

example above, TS(37) to TS(1), the
delta is –36, so FME is set to 1 to effect
the minimum delay (setting to 0 effects
constant delay), and the resulting
latency is 128 – 36 = 92 time slots. The
relative positions of the end time slots
are the same in both minimum and con­stant delay (i.e., they both switch to
TS[1]), but the actual data is delayed by
an additional frame in the constant delay
case.

Simple
Summary:

Use minimum delay for latencies of 3 to
128 time slots, set FME = 0 for forward
connections, set FME = 1 for reverse
connections.

127

255

256

5-6223 (F)

APPLIED DELTA

–127

1

=

E

M

F

0

128

(TIME SLOTS)

129

RESULTING LATENCY

(TIME SLOTS)

0

=

E

M

F

Figure 34. Constant Delay Connections, CON[1:0] = 0X

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Preliminary Data Sheet

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Appendix B. Minimum Delay and Con­stant Delay Connections

B.2 Delay Type Definitions

B.2.1 Exceptions to Minimum Delay

Up until this point in the discussion, the STRDs have
not been discussed because the to and
have been irrelevant in the switching process*. Rather
than try to list the exceptions mathematically, a table is
provided. The latencies in these cases m ay e xceed two
frames due to the interaction of the intrinsic pipeline
delays with the double buffering.

Table 65. Table of Special Cases (Exceptions)

FME Value

TS

0 +1 257 257
0 +2 258 2
1 –126 258 2
1 –127 257 257

Graphically, the minimum delay latency equations are
illustrated below. The exceptions to the minimum delay
have been included in the diagram, connected to the
main function by dashed lines.

∆

Latency for

STR

(continued)

(continued)

< 0

∆

from

streams

Latency for

STR∆ ≥ 0

B.2.2 Lower Stream Rates

The discussion has centered on 128 time-slot frames
which correspond to 8.192 Mbits/s data rates. How
does one make similar predictions for lower stream
rates?

For 4.096 Mbits/s, multiply the to and

from

time-slot
values by two, i.e., time slot 0 at 4.096 Mbits/s corre­sponds to time slot 0 at 8.192 Mbits/s, and time slot 63
at 4.096 Mbits/s corresponds to time slot 126 at 8.192
Mbits/s. Similarly, multiply values by four to convert

2.048 Mbits/s values. The latency equations can then
be applied directly.

* The one universally disallowed connection on the T8100 is a TS∆ of

0 and a STR∆ of 0. This is a stream and time-slot switching to itself.
Loopback on the local bus, e.g., LDO_0 to LDI_0 is permissible.

127

0

=

E

M

F

SPECIAL LONG LATENCY

E

M

F

CONNECTIONS

(SEE TEXT)

1

=

2

2

0

0

(TIME SLOTS)

APPLIED DELTA

–126
–127

2

RESULTING LATENCY

(TIME SLOTS)

127

258

128......256

257

5-6224(F)

Figure 35. Minimum Delay Connections, CON[1:0] = 0X

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August 1998

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T8100

H.100/H.110 Interface and Time-Sl ot Interchanger

Appendix B. Minimum Delay and Con­stant Delay Connections

B.2 Delay Type Definitions

B.2.3 Mixed Minimum/Constant Delay

An interesting mix of delays occurs when the individual
FME bits are overridden and a chip-wide selection for
FME is used. In short, when the T8100 is placed in this
mode, and when register bits CON[1:0] = 10, forward
connections provide minimum delay, reverse connec­tions provide constant delay. When CON[1:0] = 11,
reverse connections provide minimum delay, forward
connections provide constant delay. The latter is inter­esting because, graphically, the TS∆ to latency map-

127

2

(TIME SLOTS)

APPLIED DELTA

(continued)

(continued)

2

0

0

= 0

ME

F

128

RESULTING LATENCY

(TIME SLOTS)

ping appears as a linear monotonic function covering
255 time slots. (Graphs are in the section which fol­lows.) The latency equations follow:

CON[1:0] = 10:
Forward Connections: L = TS∆ (3 ≤ TS∆ ≤ 127).
Reverse Connections: L = 256 + TS∆ (–127 ≤ TS∆ ≤

0).
CON[1:0] = 11:
Forward and Reverse: L = 128 + TS∆ (–125 ≤ TS∆ ≤

127).
Table 65, Table of Special Cases (Exceptions), applies

to the mixed delays in a similar manner. Simply use bit
0 of CON for the FME value in Table 65.

SPECIAL LONG LATENCY

127

CONNECTIONS

(SEE TEXT)

0

=

FME

258

256

–127

–127

129

5-6225(F)

Figure 36. Mixed Minimum/Constant Delay Connections, CON[1:0 = 10]

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Preliminary Data Sheet

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Appendix B. Minimum Delay and Constant Delay Connections

B.2 Delay Type Definitions

B.2.3 Mixed Minimum/Constant Delay

(continued)

127

0

(TIME SLOTS)

APPLIED DELTA

–126

(continued)

0

2

128

RESULTING LATENCY

(TIME SLOTS)

SPECIAL LONG LATENCY

CONNECTIONS

1

=

ME

F

(SEE TEXT)

255

256

–127

258

257

(continued)

5-6226(F)

Figure 37. Extended Linear (Mixed Minimum/Constant) Delay, CON[1:0] = 11

For additional information, contact your Microelectronics Group Account Manager or the following:

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