Datasheet T-51378L025J-FW-P-AA Datasheet (OPTREX)

OP T R E X

LCD Module Technical Specification

T-51378L025J-FW-P-AA

Table of Contents

1. Applications

2. Features

3. Mechanical Specifications

4. Mechanical Drawing of panel

5. Input / Output Terminals

Pixel arrangement and input connector pin No

6.

7. Absolute Maximum Ratings

8. Electrical Characteristics

9. Power Sequence

10. Optical Characteristics

11. Handing Cautions

12. Reliability

13. Indication of Lot Number Label

14.Block Diagram

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First Edition

Feb 7, 2002

Final Revision

******

Checked by (Quality Assurance Div.)

Checked by (Design Engineering

Prepared by (Production Div.)

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Revision History

Rev. Date Page Comment

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1. Application

This technical specification applies to 2.5" color TFT-LCD panel. The 2.5” color TFT LCD
panel is designed for camcorder, digital camera application and other electronic products
which require high quality flat panel displays.

2. Features

. Compatible with NTSC or PAL system
. High Resolution : 112,320 Dots
. Optimum Viewing Direction: 6 o’clock
. Up/Down and Left/Right Image Reversion

3. Mechanical Specifications

Parameter Specifications Unit

Screen Size 2.5 (diagonal) inch

Surface Treatment Anti-Glare

Display Format

Active Area

Dot Pitch

Pixel Configuration Delta

Outline Dimension

Weight

61.6 (W)×49.3 (H)×5.9 (D)

480×234

50.21×37.67

0.105(W)×0.161(H)

28±3

dot
mm
mm

mm

g

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4. Mechanical Drawing of panel:

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5.Input / Output Terminals

Pin No Symbol I/O Description Remark

1 STH1 I/O Start pulse for source driver Note 5-1
2 AV
3 AV
4 V
5 V
6 V
7 V
8 V

SS

DD

B

G

R

SS

DD

I Analog GND for source driver
I Analog power input for source driver Note 5-2
I Video Input B
I Video Input G

Note 5-4
I Video Input R
I Digital GND
I Digital power input Note 5-3

9 CPH1 I Sampling and shift clock for source driver
10 CPH2 I Sampling and shift clock for source driver
11 CPH3 I Sampling and shift clock for source driver
12 STH2 I/O Start pulse for source driver Note 5-1
13 Q2H I Video input rotation control
14 INH I Output enable for source driver
15 R/L I Left/Right Control for source driver Note 5-1
16 V
17 V

COM

COM

I Common electrode voltage

Note 5-4

I Common electrode voltage
18 XOE I Output enable for gate driver
19 CPV I Clock input for gate driver
20 U/D I Up/Down Control for gate driver
21 DIO2 I/O Vertical start pulse
22 DIO1 I/O Vertical start pulse
23 V
24 V
25 V
26 V
27 V

GL

EE

SS

CC

GH

I Gate off voltage(alternative every 1-H) Note 5-4

I Gate driver negative voltage Note 5-6

I GND

I Logic power for gate driver Note 5-3

I Gate on voltage Note 5-7
28 NC - No connection -

Note 5-1 : STH1, STH2 and R/L mode

R/L STH1 STH2 Remark

High(VDD) Input Output Left to Right

Low(0 Volt.) Output Input Right to Left

Note 5-2 : AVDD= +5V (Typ.)

Note 5-5

Note 5-3 : VDD, VCC= +5V(Typ.)
Note 5-4 : V

COM

= 6VPP.

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Phase of the video signal input and V

COM

The relation between these values could refer to 8-1 Operating condition.

100% white

Composite Video

Signal

R,G,B Video

Signal

(

V

,

V

,

V

R

)

G

B

V

i DC

pedestal

V

i AC

V

V

COM

GL

V

COM DC

V

GL DC

V

COM AC

V

GL AC

1H 1H

Fig.1

Liquid crystal transmission of the video signal input, V

V

COM

COM

and timing

H Level L Level

Video Signal Input Maximum Black White

Video Signal Input Minimum White Black

White : maximum transmission / Black : minimum transmission

Note 5-5：DIO1, DIO2 and U/D mode

U/D DIO1 DIO2 Remark

High (VDD) Input Output Down to Up

Low (0 Volt.) Output Input Up to Down

Note 5-6 : VEE= -15V (Typ.).
Note 5-7 : VGH=+15V (Typ.).

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6. Pixel Arrangement and input connector pin NO.

1 48047947865432
1
2
3
4

233
234

B RBGRBGR G

R GRBGRBG B

B RBGRBGR G

R GRBGRBG B

B RBGRBGR G

R GRBGRBG B

1 28

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7. Absolute Maximum Ratings:

P-P

P-P

COM AC

P-P

COM DC

DD

DD

The followings are maximum values , which if exceeded, may cause faulty operation or
damage to the unit.

GND = 0 V，Ta = 25

Parameter Symbol MIN. MAX. Unit Remark

C

Supply Voltage for Source Driver Analog AV

Digital V
Supply Voltage Positive V
for Gate Driver Negative V

VGHV

Analog input voltage V

Video

DD

DD

GH

GL

-0.3 +7 V

-0.3 +7

-0.3 +45 V

-23 +0.3 V

+15 +40 V

GL

-0.3 +7.3 V Notes:7-1
Storage Temperature -30 +85 C
Operation Temperature -20 +80 C Notes:7-2

Notes 7-1 : Analog Input Voltage means VR,VG,VB.
Notes 7-2 : Operating Temperature define that contrast, response time, other display

optical character are Ta=+25.

8. Electrical Characteristics

8-1) Operating Condition

Item Symbol Min. Typ. Max. Unit Remark

+4.5 +5.0 +5.5 V
+3.0 +3.3 +3.6 V

+4.5 +5.0 +5.5 V

+14.5 +15.0 +15.5 V

-15.5 -15.0 -14.5 V

- +6.0 - V

-12.5 -11.0 -9.5 V

- +4.0 +4.2 V

- +2.5 - V DC Component

- +6.0 - V

+0.9 +1.0 +1.1 V

+0.7 V

- - +0.3 V

- - V
V

Power Supply

Video Signal

(VR, VG, VB)

V

COM

V
V

AV

V

V

V
V

V
V

V
V

H Level V

L Level V

CC
DD

DD

GH

EE

GL AC

GL DC

i AC

i DC

IH

IL

Note 8-1 : STH1,STH2,CPH1,CPH2,CPH3,Q2H,INH,CPV,XOE,DIO1,DIO2

AC Component
of V

GL

DC Component
of V

GL

AC Component
Note 8-2

AC Component
of V

COM

DC Component
of V

COM

Note 8-1

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Note 8-2：Both NTSC and PAL system Video Signal input waveform is based on 8 steps

4.0｡ﾓ0.2V

gray

scale.

White

Black

White

Black

4.0±0.2V

White

Black

White

8-2)Current Consumption (GND=AVSS=0V)

Parameter Symbol Condition Min. Typ. Max. Unit Remark

Current for Driver

I

AI

I
I

I
I

GH
GL

CC,

DD
DD
EE

VGH=+15V - 0.026 0.03 mA

VGL=-12V - 0.35 0.4 mA VGLcenter voltage
VCC=+5V - 0.1 0.15 MA

AVDD=+5V - 1.73 1.83 mA

VDD=+5V - 0.66 0.7 mA

VEE=-15V - 0.1 0.15 mA

8-3) Backlight driving & Power Consumption

Ta= 25

C

Pin No Symbol Description Remark

1 VL1 Input terminal (Hi voltage side)
3 VL2 Input terminal (Low voltage side) Note 8-3

Note 8-3 : Low voltage side of backlight inverter connects with Ground of inverter circuits.

Ta= 25

C

Parameter Symbol Min. Typ. Max. Unit Remark
Lamp voltage V
Lamp current I
Lamp frequency P

℃

Kick-off voltage(25
Kick-off voltage(0

℃

)

)

Vs - 400 Vrms
Vs - 520 Vrms

L

L

L

- 235 - Vrms IL=3mA

- 3 - mA

25 35 45 KHz Note 8-4

Note 8-4 : The wave form of lamp driving voltage should be as closed to a perfect SIN

wave as possible.

Power Consumption

Ta= 25

C

Parameter Symbol Conditions TYP. MAX Unit Remark

LCD Panel Power Consumption 18.5 W Note 8-5
Backlight Lamp Power Consumption 0.71 W Note 8-6
Total Power Consumption 0.73 W

Note 8-4：The power consumption forbacklight is not included.

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Note 8-5：The power consumption forbacklight is not included.
Note 8-6：Backlight lamp power consumption is calculated by I

8-4) Input / Output Connector

A) LCD Module Connector

FFC Down Connector,
28 Pins
Pitch : 0.5 mm

B) Backlight Connector

JST BHR-03VS-1
Pin No. : 3
Pitch : 4 mm

×

VL.

L

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8-5) Timing Characteristics Of Input Signals

DCOM

DRGB

Characteristics Symbo

Min. Typ. Max. Unit Remark
1Field Scanning Period t1V - 262.5 - H
1Line Scanning Period t1H - 63.5 - µs
Source Driver Operating Frequency fhc 1.0 3.14 5.0 MHz

Signal Sampling Pulse Width tchw 200 317.7 1000 ns
Signal Sampling Pulse Delay tchd 95.3 105.9 116.5 ns tchd 12,23
Signal Sampling Pulse Width(H) tchwh 142.9 158.8 174.7 ns
Signal Sampling Pulse Delay(L) tchwl 142.9 158.8 174.7 ns
Source Start Signal Pulse Width tshw 90 317.7 630* ns *tshset=tshhld
Source Start Signal Setup Time tshset 20 158.8 - ns
Source Start Signal Hold Time tshhld 20 158.8 - ns
Source Output Enable Pulse Width tohw 1.0 2.0

- µs
Source Start Signal Rising Time tss - 9.8 - µs
Video Input Signal Start Point tvs - 10.0 - µs
Phase Difference Between

toc 1.5 2.3 - µs
Gate Clock Period tcvw 10 63.5 - µs
Gate Clock Pulse Width(H) tcvwh 10 31.7 48 µs
Gate Clock Pulse Width(L) tcvwl 10 31.7 48 µs
Gate Start Signal Pulse Width tsvw 5 63.5 126** µs **tsvset=tsvhld
Gate Start Signal Setup Time tsvset 5 53.2 - µs
Gate Start Signal Hold Time tsvhld 5 10.3 - µs
Phase Difference Between

Phase Difference Between SYNC&OEH

tosp - 4 - µs

tohs - 1.4 - µs
Gate Output Enable Pulse Width toev - 2.5 - µs
V

Delay Time t

COM

RGB Delay Time t

- - 3 µs

- - 2 µs

Vertical Display Start tsv - 3 - tH

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8-6) Signal Timing Waveforms

Fig. 8‑1 Vertical Start Line for NTSC

2nd display period

286285284283282

(285H519H)

265 266 267 268 269

HD

1st display period

VD

(22H256H)

tsvw

t1V=262.5H

2 3 4 5 6 7 19 20 21 22 23

Xout

DIO

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2nd display period

Fig. 8‑1 Vertical Start Line for PAL

* * o d d f i e l d : S c a n l i n e s 1 4 n + 61 4 n + 1 2 ( n = 2 , 3 , 4 . . ) a r e n o t d i s p l a y e d .

e v e n f i e l d : S c a n l i n e s 1 4 n + 1 21 4 n + 2 0 ( n = 2 , 3 , 4 . . ) a r e n o t d i s p l a y e d .

340339338337336

(339H611H)

312 313 314 315 316

HD

1st display period

VD

(28H299H)

tsvw

t1V=312.5H

624 625 1 2 3 4 25 26 27 28 29

Xout

DIO

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1 2161197

Fig. 8‑2 Horizontal Start Pixel

t1H=199 CPHclk=63.5u sec

1 2 3199198 160

Tshw

Invalidity data Validity data Invalidity data

STH1,2

CPH1

R,G,B

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STH1,2

V

tcvw

Fig. 8‑3 Detail Horizontal Timing

tcvwl

tcvwh

tss tshw

HD

T-51378L025J-FW-P-AA

tosp

DCOM

tohwtohs

INH

toc

CPV

toev

XOE

t

Q2H

OPTREX CORPORATION

COM

V

DRGB

t

R,G,B

tvs

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tchw

Fig. 8‑4 Sampling Clock Timing

R3 (B3)

G2 (R2)

R2 (B2)

B1 (G1) B2 (G2)

G1 (R1)

R1 (B1)

tchwh tchwl

tshw

tshset tshhld

tchd23

tchd12

CPH 1

CPH 2

CPH 3

STH 1,2

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tcvw

Fig. 8‑5 Vertical Shift Clock Timing

tsvw

tsvset tsvhld

tcvwh tcvwl

CPV

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Vertical timing (From up to down)

Fig. 8‑6(a) Vertical Timing (From Up to Down)

ODD FIELD

EVEN FIELD

RGB

BRG

tsv

Display on panel first line

V(R,G,B)

V(R,G,B)

HD

VD

DIO2

Q2H

COM

V

(Odd field)

V

COM

(Even field)

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Vertical timing (From down to up)

Fig. 8‑6(b) Vertical Timing (From Down to Up)

EVEN FIELD

BRG

RGB

tsv

Display on panel first line

HD

V(R,G,B)

V(R,G,B)

ODD FIELD

T-51378L025J-FW-P-AA

VD

Q2H

DIO1

COM

V

(Odd field)

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COM

V

(Even field)

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9. Power on Sequence(Voltage source)
The Power on Sequence only effect by VCC,VSS,VDD,VEEand V

V

GH

VDD,V

CC

VSS(0V)

V

EE

the others do not care.

GH,

OFF OFF

T1

T2

RGB‑Video signal

ON

Logic signal

V

COM,VGL

T3

T4

1) 10ms≦T1<T2

2) 0ms<T3≦T4≦10ms

10. Optical Characteristics

10-1) Specification

Ta = 25

Parameter Symbol Condition MIN. TYP. MAX. Unit Remarks

Viewing Horizontal
Angle Vertical

θ

θ

(to 12

o’clock)

θ

(to 6

CR≧10

±

45

±

50

10 15 deg

30 35 deg

deg

Note 10-3

o’clock)
Contrast Ratio CR 110 150 Note 10-1
Response time Rise Tr

Fall Tf

θ=0°

φ=0°

30 ms
50 ms

Note 10-4

Transmission Ratio T 7.5 8.0 8.5 %
Uniformity U 65 70
Brightness 170 220 cd/m2Note 10-2
White
Chromaticity

Lamp Life Time

+25

℃

X
Y

Tc

θ=0°

0.250

0.260
6650 6850 7050

10,000 hr

0.300

0.310

0.350

0.360

Note 10-2

C

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Luminance when LCD is White

B

Tr

Tf

Note 10-1：CR

＝

Luminance when LCD is Black
Contrast Ratio is measured in optimum common electrode voltage.
The test configurations of contrast ratio see section 10-2.

Note 10-2 : 1.Topcon BM-7(fast) luminance meter 1°field of view is used in the testing

(after 20~30 minutes operation).

2.Lamp current : 3mA

3.Inverter model : TDK-347.

Note 10-3 : The definition of viewing angle diagrams :

normal

(

q = 0)

12

observer

q

3

LCD panel

9

f

: Viewing direction

q

: Viewing angle

Note 10-4 : The definitions of response time:

White White

Black

100%

90%

rightness

ABC

6

f

10%

0%

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10-2) Test Configuration

BM-7(fast)

500mm

Caution: 1. Environmental illumination≦1 lux

Caution: 1. Environmental illumination

2. Before test CR, Vcom voltage must be
adjusted carefully to get the best CR.

2. Before test CR, Vcom voltage must

｡ ﾘ

1 lux

be adjusted carefully to get the best
CR.

R,G,B signal

Pattern

generator

Ÿ

LCD Display

input

LCD

Backlight

Testing Point Testing Point

Pattern A Pattern B

Ÿ

R, G, B Waveform of Pattern A at Testing Point

16ms 16ms

RGB
waveform

Vcom

Vw=TBDV +/- 0.2V

Ÿ

R, G, B Waveform of Pattern B at Testing Point

16ms 16ms

Vb=TBDV +/- 0.2V

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RGB
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Vcom

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11. Handling Cautions
11-1) Mounting of module

a) Please power off the module when you connect the input/output
connector.
b) Please connect the ground pattern of the inverter circuit surely. If the

connection is not perfect, some following problems may happen possibly.

1.The noise from the backlight unit will increase.

2.The output from inverter circuit will be unstable.

3.In some cases a part of module will heat.

c) Polarizer which is made of soft material and susceptible to flaw must be

handled carefully.

d) Protective film (Laminator) is applied on surface to protect it against

scratches and dirt. It is recommended to peel off the laminator before
use and taking care of static electricity.

11-2) Precautions in mounting

a) When metal part of the TFT-LCD module (shielding lid and rear case) is

soiled, wipe it with soft dry cloth.

b) Wipe off water drops or finger grease immediately. Long contact with

water may cause discoloration or spots.

c) TFT-LCD module uses glass which breaks or cracks easily if dropped or

bumped on hard surface. Please handle with care.

d) Since CMOS LSI is used in the module. So take care of static electricity

and earth yourself when handling.

11-3) Adjusting module

a) Adjusting volumes on the rear face of the module have been set optimally

before shipment.

b) Therefore, do not change any adjusted values. If adjusted values are

changed, the specifications described may not be satisfied.

11-4) Others

a) Do not expose the module to direct sunlight or intensive ultraviolet rays

for many Hours.
b) Store the module at a room temperature place.
c) The voltage of beginning electric discharge may over the normal voltage

because of leakage current from approach conductor by to draw lump

read lead line around.
d) If LCD panel breaks, it is possibly that the liquid crystal escapes from the

panel. Avoid putting it into eyes or mouth. When liquid crystal sticks on

hands, clothes or feet. Wash it out immediately with soap.
e) Observe all other precautionary requirements in handling general

electronic components.
f) Please adjust the voltage of common electrode as material of attachment

by 1 module.

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12. Reliability

No. Test Item Test Condition

1 High Temperature Storage Test Ta = +85C, 240 hrs
2 Low Temperature Storage Test Ta = -30C, 240 hrs
3 High Temperature Operation Test Ta = +80C, 240 hrs
4 Low Temperature Operation Test Ta = -20C, 240 hrs

5
6

7

8

9

High Temperature & High

Humidity Operation Test

Thermal Cycling Test

(non-operating)

Vibration Test

(non-operating)

Shock Test

(non-operating)

Electrostatic Discharge Test

(non-operating)

Ta = +60C, 95%RH, 240 hrs

C

→

-25

30 min 5min 30 min

Test Period: 6 Cycles for each direction of X, Y, Z

Direction:±X,±Y,±Z

Air:±15KV; Contact:±8KV

10 times/point, 4 points/panel face

C

→

+25

Frequency：10 ~ 55 H

Amplitude：1.0 mm

Sweep time: 11 mins

Cycle: 3 times

+70C, 200 Cycles

100G, 6ms

150pF, 330

Z

Ω

Ta: ambient temperature

[Criteria]

Under the display quality test conditions with normal operation state, there should be no

change which may affect practical display function.

13. Indication of Lot Number Label
a) Indicated contents of the label

Lot number

OOO-OOOOOO

XXXXXXXXX

Internal number

Contents of lot number : SB9—STC OEM product

5th—Production year : 1999Þ9, 2000ÞA, 2001Þ1……..
6th—Production month : 1, 2, 3,….9, A, B, C
7th~10th—Serial numbers : 0001~9999

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14. Block Diagram

LCD Panel

H Driver
(Source)

28 PIN Input

V Driver

(Gate)

Inverter

Back‑light

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