Datasheet T35L6432A-5Q, T35L6432A-5T Datasheet (Taiwan Memory Technology)

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A10

VSS

A11

A12

A13

A14

A15

MODE

T35L6432A

SYNCHRONOUS
BURST SRAM

FEATURES

¡EFast Access times: 4.5, 5, 6, 7, and 8ns
¡EFast clock speed: 125,100, 83, 66, and 50 MHz
¡EProvide high performance 3-1-1-1 access rate

¡EFast
¡ESingle 3.3V +10%/-5% power supply
¡ECommon data inputs and data outputs
¡EBYTE WRITE ENABLE and GLOBAL WRITE

control

¡EThree chip enables for depth expansion and

address pipelining

¡EAddress, control, input, and output pipelined

registers

¡EInternally self-timed WRITE CYCLE
¡EWRITE pass-through capability
¡EBurst control pins ( interleaved or linear burst

sequence)

¡EHigh density, high speed packages
¡ELow capacitive bus loading
¡EHigh 30pF output drive capability at rated access

time

¡ESNOOZE MODE for reduced power standby
¡E Single cycle disable ( PentiumTM BSRAM

compatible )

OPTIONS

TIMING MARKING

4.5ns access/8ns cycle -4.5
5ns access/10ns cycle -5
6ns access/12ns cycle -6
7ns access/15ns cycle -7
8ns access/20ns cycle -8

Package
100-pin QFP Q
100-pin TQFP T

Part Number Examples

PART NO. Pkg. BURST SEQUENCE

T35L6432A-5Q Q Interleaved

T35L6432A-5T T Linear (MODE=GND)

access times: 4.5, 5 and 6ns

(MODE=NC or VCC)

64K x 32 SRAM

3.3V supply, fully registered inputs and
outputs, burst counter

PIN ASSIGNMENT (Top View)

A7

A6

CE

NC

DQ17

2

DQ18

3

VCCQ

4

VSSQ

5

DQ19

6

DQ20

7

DQ21

8

DQ22

9

VSSQ

10

VCCQ

11

DQ23

12

DQ24

13

NC

14

VCC

15

NC

16

VSS

17

DQ25

18

DQ26

19

VCCQ

20

VSSQ

21

DQ27

22

DQ28

23

DQ29

24

DQ30

25

VSSQ

26

VCCQ

27

DQ31

28

DQ32

29

NC NC

30

31 41403938373635343332 4948474645444342 50

A4

A5

BW2

BW3

BW4

CE2

9596 88 87 86 85 84 83 82 819091929394 89100 99 98 97

100-pin QFP

100-pin TQFP

A0

A1

A2

A3

BW1

NC

NC

CE2

or

VCC

VSS

GENERAL DESCRIPTION

The Taiwan Memory Technology Synchronous
Burst RAM family employs: high-speed, low power
CMOS design using advanced triple-layer
polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two
high valued resistors.

The T35L6432A SRAM integrates 65536 x 32
SRAM cells with advanced synchronous peripheral
circuitry and a 2-bit counter for internal burst
operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include
all addresses, all data inputs, address-pipelining

CLK

NC

NC

GW

BWE

OE

ADSC

ADSP

ADV

A9

A8

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

NC

NC1
DQ16
DQ15

VCCQ
VSSQ

DQ14
DQ13
DQ12
DQ11

VSSQ
VCCQ

DQ10

DQ9
VSS

NC

VCC

ZZ
DQ8
DQ7

VCCQ
VSSQ

DQ6
DQ5
DQ4
DQ3

VSSQ
VCCQ

DQ2
DQ1

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: DEC. 1998
to change products or specifications without notice. Revision: A

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3, BW

4

BWE

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ADSP

ADSC

ADV

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1

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2

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3

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4

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1,BW

2, BW

3

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4

BWE

GW

GENERAL DESCRIPTION (continued)

chip enable (CE), depth- expansion chip enables
(

and CE2),burst control inputs
(
(
global write (

enable (
control (MODE). The data outputs (Q), enabled
by

with either address status processor (
address status controller (
Subsequent burst addresses can be internally
generated as controlled by the burst advance pin
(

registered on-chip to initiate self-timed WRITE
cycle. WRITE cycles can be one to four bytes

,

, and

), write enables

, and

), and

).

Asynchronous inputs include the output

),Snooze enable (ZZ) and burst mode

, are also asynchronous.

Addresses and chip enables are registered

) or

) input pins.

).

Address, data inputs, and write controls are

T35L6432A

wide as controlled by the write control inputs.
Individual byte write allows individual byte to be
written.
controls DQ9-DQ16.

24.

being LOW.
bytes to be written. WRITE pass-through
capability allows written data available at the
output for the immediately next READ cycle.
This device also incorporates pipelined enable
circuit for easy depth expansion without penalizing
system performance. The T35L6432A operates
from a 3.3V +10%/-5% power supply. The device
is ideally suited for Pentium
PC

 systems and for systems that are benefited

from a wide synchronous data bus.

controls DQ1-DQ8.

controls DQ17-DQ

controls DQ25-DQ32.

, and

can be active only with

being LOW causes all

, 680X0, and Power

FUNCTIONAL BLOCK DIAGRAM

14

DO D1 Q1
COUNTER

& LOGIC

CLR

PIPELINED

ENABLE

16

A0

BINARY

A1

Q0

A0-A15

MODE

ADV
CLK

ADSC

ADSP

BWE

BW4

BW3

BW2

BW1

GW

CE

CE2
CE2

OE

16

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

WRITE REGISTER

BYTE 4

BYTE 3

BYTE 2

BYTE 1

REGISTER

ENABLE

ADDRESS

REGISTER

A1'

A0'

8

8

8

8

16

BYTE 4

WRITE DRIVER

BYTE 3

WRITE DRIVER

BYTE 2

WRITE DRIVER

BYTE 1

WRITE DRIVER

8

8

8

8

64K x 8 x 4

MEMORY

ARRAY

32 32

4

SENSE

AMPS

OUTPUT

REGISTERS

OUTPUT

BUFFERS

32

INPUT

REGISTERS

DQ1

DQ32

¡E
¡E

¡E

Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin

descriptions and timing diagrams for detailed information.

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: DEC. 1998
to change products or specifications without notice. Revision: A

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2

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3

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3

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4

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4

BWE

BWE

GW

BWE

BWn

CE

ADSP

CE

2

OE

ADV

ADSP

CE

ADSC

T35L6432A

PIN DESCRIPTIONS

QFP PINS SYM. TYPE DESCRIPTION

32-37, 44-49, A0- Input- Addresses: These inputs are registered and must meet the setup and

81, 82, 99, 100, A15 Synchronous hold times around the rising edge of CLK. The burst counter -

generates internal addresses associated with A0 and A1,during
burst cycle and wait cycle.

93-96

conditioned by

87

88

89 CLK Input- Clock: This signal registers the addresses, data, chip enables, write

98

92

97 CE2 Input- Synchronous Chip Enable: This active HIGH input is used to enable

86

83

84

85

Input- Byte Write: A byte write is LOW for a WRITE cyle and HIGH for

Synchronous a READ cycle.

DQ16.
Data I/O are high impedance if either of these inputs are LOW ,

Input- Write Enable: This active LOW input gates byte write operations

Synchronous and must meet the setup and hold times around the rising edge of

CLK.

Input- Global Write: This active LOW input allows a full 32-bit WRITE

Synchronous to occur independent of the

the setup and hold times around the rising edge of CLK.

Synchronous control and burst control inputs on its rising edge. All synchronous

inputs must meet setup and hold times around the clock's rising
edge.

Input- Synchronous Chip Enable: This active LOW input is used to enable

Synchronous the device and conditions internal use of

sampled only when a new external address is loaded.

Input- Synchronous Chip Enable: This active LOW input is used to enable

Synchronous the device. This input is sampled only when a new external address

is loaded. This input can be used for memory depth expansion.

Synchronous the device. This input is sampled only when a new external address

is loaded. This input can be used for memory depth expansion.

Input Output enable: This active LOW asynchronous input enables the

data output drivers.

Input- Address Advance: This active LOW input is used to control the

Synchronous internal burst counter. A HIGH on this pin generates wait cycle

(no address advance).

Input-

Synchronous being LOW, causes a new external address to be registered and a

Input- Address Status Controller:This active LOW input causes device to

Synchronous be deselected or selected along with new external address to be

Address Status Processor: This active LOW input, along with

READ cycle is initiated using the new address.

registered. A READ or WRITE cycle is initiated depending upon
write control inputs.

controls DQ17-DQ24.

controls DQ1-DQ8.

being LOW.

and

controls DQ9-

controls DQ25-DQ32.

lines and must meet

. This input is

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

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T35L6432A

PIN DESCRIPTIONS (continued)

QFP PINS SYM. TYPE DESCRIPTION

31 MODE Input- Mode: This input selects the burst sequence. A LOW on this pin

Static selects LINEAR BURST. A NC or HIGH on this pin selects

INTERLEAVED BURST. Do not alter input state while device is
operating.

64 ZZ Input Snooze Enable: This active HIGH asynchronous input causes the

device to enter a low-power standby mode in which all data in the
memory arry is retained.

2,3,6-9,12,13, 18, DQ1- Input/ Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is
19,22-25,28,29,52, DQ32 Output DQ9-DQ16. Third Byte is DQ17-DQ24. Fourth Byte is DQ25­53,56-59,62,63,68, DQ32. Input data must meet setup and hold times around the

69,72-75,78,79, rising edge of CLK.

15,41,65,91 VCC Supply Power Supply: 3.3V +10%/-5%
17,40,67,90 VSS Ground Ground: GND

4,11,20,27,54,

61,70,77

5,10,21,26,55,

60,71,76

1,14,16,30,38,39, NC - No Connect: These signals are not internally conntected.

42,43,50,51,66,80

VCCQ I/O Supply Output Buffer Supply: 3.3V +10%/-5%

VSSQ I/O Ground Output Buffer Ground: GND

Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

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INTERLEAVED BURST ADDRESS TABLE (MODE = NC/VCC)

T35L6432A

First Address

(external)

A...A00 A...A01 A...A10 A...A11
A...A01 A...A00 A...A11 A...A10
A...A10 A...A11 A...A00 A...A01
A...A11 A...A10 A...A01 A...A00

Second Address

(internal)

Third Address

(internal)

Fourth Address

(internal)

LINEAR BURST ADDRESS TABLE (MODE = GND)

First Address

(external)

A...A00 A...A01 A...A10 A...A11
A...A01 A...A10 A...A11 A...A00
A...A10 A...A11 A...A00 A...A01
A...A11 A...A00 A...A01 A...A10

Second Address

(internal)

Third Address

(internal)

Fourth Address

(internal)

PARTIAL TRUTH TABLE FOR READ/WRITE

Function

READ H H X X X X
READ H L H H H H
WRITE one byte H L L H H H
WRITE all byte H L L L L L
WRITE all byte L X X X X X

WRITE PASS-THROUGH TRUTH TABLE

PREVIOUS CYCLE PRESENT CYCLE NEXT CYCLE

OPERATION

Initiate WRITE cycle, all bytes

Address= A(n-1), data= D(n-1) Register A(n), Q= D(n-1)

Initiate WRITE cycle, all bytes

Address= A(n-1), data= D(n-1) Q = D(n-1) previous cycle

Initiate WRITE cycle, all bytes

Address= A(n-1), data= D(n-1) Q = HIGH-Z previous cycle

Initiate WRITE cycle, one bytes

Address= A(n-1), data= D(n-1) Q = D(n-1) for one byte previous cycle

Note: 1. Previous cycle may be any cycle(non-burst, burst, or wait).

2.

3.

Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

is LOW for individual byte WRITE.

= LOW yields the same result for all-byte WRITE operation.

2,3

All L

2,3

All L

2,3

All L

ONE L

2

OPERATION

Initiate READ cycle L H L Read D(n)

No new cycle H H L No carry-over from

No new cycle H H H No carry-over from

No new cycle H H L No carry-over from

OPERATION

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CE2

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WRITE

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2, BW

3

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4

BWE

GW

WRITE

BW

1

BW

2

BW

3

BW

4

OE

OE

OE

ADSP

TRUTH TABLE

T35L6432A

OPERATION

Snooze Cycle, Power Down None X X X H X X X X X X High-Z
READ Cycle, Begin Burst External L L H L L X X X L L-H Q
READ Cycle, Begin Burst External L L H L L X X X H L-H High-Z
WRITE Cycle, Begin Burst External L L H L H L X L X L-H D
READ Cycle, Begin Burst External L L H L H L X H L L-H Q
READ Cycle, Begin Burst External L L H L H L X H H L-H High-Z
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H High-Z
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
READ Cycle, Continue Burst Next H X X L X H L H H L-H High-Z
WRITE Cycle, Continue

Burst
WRITE Cycle, Continue
Burst
READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z
READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z
WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D

ADDRESS

USED

None H X X L X L X X X L-H High-Z
None L X L L L X X X X L-H High-Z
None L H X L L X X X X L-H High-Z
None L X L L H L X X X L-H High-Z
None L H X L H L X X X L-H High-Z

Next X X X L H H L L X L-H D

Next H X X L X H L L X L-H D

CE2 ZZ

CLK DQ

Note: 1. X means "don't care." H means logic HIGH. L means logic LOW.

more byte write enable signals
equals LOW.

2.

3. All inputs except

4. Suspending burst generates wait cycle.

5. For a write operation following a read operation.

6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.

7.

Taiwan Memory Technology, Inc. reserves the right P. 6 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

= enables write to DQ1-DQ8.

DQ17-DQ24.

of CLK.

required setup time plus High-Z time for
time.

= LOW along with chip being selected always initiates an internal READ cycle at the L-H

edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge

of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.

= H means all byte write signal are HIGH.

=enables write to DQ25-DQ32.

must meet setup and hold times around the rising edge ( LOW to HIGH)

(

= enables write to DQ9-DQ16.

and staying HIGH throughout the input data hold

or

must be HIGH before the input data

) and

= L means any one or

are LOW, or

= enables write to

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DESCRIPTION

SYM.

TYP

ADSC

ADSP

ADV

GW,BWE

T35L6432A

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Supply Relative to VSS.

…………-0.5V to +4.6V

I/O Supply Voltage VccQ ........... Vss -0.5V to Vcc

V

......................................... -0.5V to Vcc +0.5V

IN

Storage Temperature (plastic)...... -55

Junction Temperature ..........….................. +150

Power Dissipation ........................................ 1.6W

Short Circuit Output Current...................... 100mA

°C to +150°C

°C

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS

(0°C ≤ Ta ≤ 70°C; VCC = 3.3V +10%/-5% unless otherwise noted)

DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES

Input High (Logic) voltage V
Input Low (Logic) voltage V
Input Leakage Current
Output Leakage Current Output(s) disabled, 0V

Output High Voltage IOH = -4.0 mA V
Output Low Voltage IOL = 8.0 mA V
Supply Voltage Vcc 3.1 3.6 V 1

0V

≤ VIN ≤ VCC

≤ V

OUT

≤ VCC

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.

2 VCCQ + 0.3 V 1, 2

-0.3 0.8 V 1, 2

-2 2

-2 2

2.4 V 1, 11

0.4 V 1, 11

µA
µA

I

I

IH

IL

LI

LO

OH
OL

14

M A X

CONDITIONS

Power Supply
Current:

Operating = MAX; outputs open
Power Supply

Current: Idle

CMOS Standby Device deselected; VCC = MAX; all I

TTL Standby

MAX;CLK frequency = 0
Clock Running

Device selected; all inputs
≥ VIH; cycle time ≥

Device selected;

,

other
inputs

≤VIL or≥VIH; VCC = MAX;

t

cycle time ≥

inputs
all inputs static; CLK frequency =0

Device deselected; all inputs
or

≥ VIH; all inputs static; VCC =

Device deselected; all inputs
or

≥ VIH; VCC =MAX; CLK cycle

time ≥

KC MIN: outputs open

≤ VSS + 0.2 or ≥ VCC - 0.2;

t

KCMIN

≤VIL or

t

KC MIN; VCC

,

≥ VIH; all

≤ V

≤ V

Icc 200 300 270 230 190 150 mA 3, 12, 13

I

SB1

,

SB2

I

SB3

IL

I

SB4

IL

-4.5 -5 -6 -7 -8 UNITS NOTES

56 155 140 125 115 110 mA 12, 13

0.5 5 5 5 5 5 mA 12, 13

15 25 25 25 25 25 mA 12, 13

30 81 81 76 66 51 mA 12, 13

Taiwan Memory Technology, Inc. reserves the right P. 7 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

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Still air, soldered on 4.25x

1.125 inch 4-layer PCB

MIN

UNITS

ADSC

ADSP

ADV

BW1

BW4

BWE

GW

CE2

ADSC

ADSP

ADV

BW1

BW4

BWE

GW

CE2

T35L6432A

CAPACITANCE

DESCRIPTION CONDITIONS SYM. TYP MAX UNITS NOTES

Input Capacitance
Input/ Output Capacitance(DQ) VCC = 3.3V C

TA = 25

°C; f = 1 MHz

THERMAL CONSIDERATION

DESCRIPTION CONDITIONS SYM. QFP TYP UNITS NOTES

C

I

O

3 4 pF 4
6 7 pF 4

Θ

JA

20

°C/W

Θ

JB

AC ELECTRICAL CHARACTERISTICS (Note 5) (0°C≤T

DESCRIPTION -4.5 -5 -6 -7 -8

SYM. MIN MAX

Clock

Clock cycle time t
Clock HIGH time t
Clock LOW time t

Output Times

Clock to output valid t
Clock to output invalid t
Clock to output in Low-Z t
Clock to output in High-Z t
OE to output valid t
OE to output in Low-Z t
OE to output in High-Z t

Setup Times

Address t

,

Address Advance (
Byte Write Enables

(

~

Data-in t
Chip Enables(CE,

Hold Times

Address t

Address Advance (
Byte Write Enables

(

~

Data-in t
Chip Enables(CE,

,

,

,

,

,

)

)

)

,CE2)

)

)

)

,CE2)

KC
KH
KL

KQ
KQX
KQLZ
KQHZ
OEQ
OELZ
OEHZ

AS

t

ADSS

t

AAS

t

WS

DS

t

CES

AH

t

ADSH

t

AAH

t

WH

DH

t

CEH

8 10 12 15 20 ns
3 4 4 5 6 ns
3 4 4 5 6 ns

4.5 5 6 7 8 ns
2 2 2 2 2 ns
2 3 3 3 3 ns 6, 7

4.5 5 5 6 6 ns 6, 7

4.5 5 5 5 6 ns 9
0 0 0 0 0 ns 6, 7

3 4 5 6 6 ns 6, 7

2.5 3 3 3 3 ns 8, 10

2.5 3 3 3 3 ns 8, 10

2.5 3 3 3 3 ns 8, 10

2.5 3 3 3 3 ns 8, 10

2.5 3 3 3 3 ns 8, 10

2.5 3 3 3 3 ns 8, 10

0.5 0.5 0.5 0.5 0.5 ns 8, 10

0.5 0.5 0.5 0.5 0.5 ns 8, 10

0.5 0.5 0.5 0.5 0.5 ns 8, 10

0.5 0.5 0.5 0.5 0.5 ns 8, 10

0.5 0.5 0.5 0.5 0.5 ns 8, 10

0.5 0.5 0.5 0.5 0.5 ns 8, 10

MAXMINMAX MINMAX MINMAX

1

≤70°C; VCC=3.3V +10%/-5%)

A

°C/W

NOTES

Taiwan Memory Technology, Inc. reserves the right P. 8 Publication Date: DEC. 1998
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AC TEST CONDITIONS

Input pulse levels 0V to 3.0V
Input rise and fall times 1.5ns
Input timing reference levels 1.5V
Output reference levels 1.5V
Output load See Figures 1 and 2

Notes:

1. All voltages referenced to VSS (GND).

2. Overshoot: VIH
Undershoot: V

3. Icc is given with no output current. Icc increases
with greater output loading and faster cycle
times.

4. This parameter is sampled.

5. Test conditions as specified with the output
loading as shown in Fig. 1 unless otherwise
noted.

6. Output loading is specified with CL = 5 pF as in
Fig. 2.

7. At any given temperature and voltage condition,
t

KQHZ is less than tKQLZ and tOEHZ is less

t

OELZ.

than

≤ +3.6 V for t ≤

≤ -1.0 V for t ≤ tKC/2.

IL

t

KC/2.

T35L6432A

8. A READ cycle is defined by byte write enables
all HIGH or

enables being active for the required setup and
hold times. A WRITE cycle is defined by at one
byte or all byte WRITE per READ/WRITE
TRUTH TABLE.

9.

is a "don't care" when a byte write enable is

sampled LOW.

10.This is a synchronous device. All synchronous
inputs must meet specified setup and hold time,
except for "don't care" as defined in the truth
table.

11.AC I/O curves are available upon request.

12."Device Deselected means the device is in
POWER-DOWN mode as defined in the truth
table. "Device Selected" means the device is
active.

13.Typical values are measured at 3.3V, 25
20ns cycle time.

14.MODE pin has an internal pull-up and exhibits
an input leakage current of

LOW along with chip

°C and

± 10µA.

OUTPUT LOADS

DQ

Z0 = 50

Fig.1 OUTPUT LOAD EQUIVALENT

DQ

351

Fig.2 OUTPUT LOAD EQUIVALENT

Vt = 1.5V

50

3.3V

30 pF

317

5 pF

Taiwan Memory Technology, Inc. reserves the right P. 9 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

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T35L6432A

SNOOZE MODE

SNOOZE MODE is a low current, “power
down” mode in which the device is deselected and
current is reduced to I

The duration of

SB2.

SNOOZE MODE is dictated by the length of time
the ZZ pin is in a HIGH state. After entering
SNOOZE MODE, the clock and all other inputs are
ignored. The ZZ pin (pin 64) is an asynchronous,
active HIGH input that causes the device to enter

SNOOZE MODE ELECTRICAL CHARACTERISTICS

DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES

Current during
SNOOZE MODE

ZZ HIGH to
SNOOZE MODE time t

SNOOZE MODE
Operation Recovery Time t

ZZ

≥ V

IH

SNOOZE MODE. When the ZZ pin becomes a
logic HIGH, I

t

ZZ is met. Any access pending when entering

is guaranteed after the setup time

SB2

SNOOZE MODE is not guaranteed to successfully
complete. Therefore, SNOOZE MODE must not
be initiated until valid pending operations are
completed.

I

SB2

ZZ 2(tKC)

RZZ 2(tKC)

5 mA

ns 4

ns 4

SNOOZE MODE WAVEFORM

CL K

CE

t

RZZ

Z Z

t

ZZ

I

SUPP LY

Note: 1. The CE signal shown above refers to a TRUE state on all chip selects for the device.

2. All other inputs held to static CMOS levels (VIN

I

ZZ

DON'T CARE

≤ Vss + 0.2 V or ≥ Vcc -0.2 V).

I

SUPPLY

Taiwan Memory Technology, Inc. reserves the right P. 10 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

TE

C

H

t

CE

2

CE

2

CE

CE

2

OE

READ TIMING

CLK

t

A D SSt A DS H

A D SP

A DSC

t

A St A H

t KHt

T35L6432A

KC

KL

t

A DS St A D SH

A D DRES S

G W , BW E ,

BW 1- B W 4

CE

(N O T E 2 )

A DV

O E

Q

t

CESt CEH

t

(NOTE3)

Hig h-Z

W St WH

t

KQ LZ

t

Sing le RE A D

t

A A St A A H

AD V susp e nds bu rs t.

t

t

O EQ

KQ

t

OEHZ

t

OELZ

KQ X

(NOTE1)

BURST REA D

t

Q (A1) Q (A2) Q(A2+1) Q(A2+2) Q(A2+3 ) Q (A2+1)

KQ

A 3A 2A 1

Burst continued wi th
new b ase add re ss.

Des elect cycle.

Q(A2)

Burst wr a ps a round
to its inita l sta te.

t
t

Q(A 3)

DON'T CARE

UNDEFINED

Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst

address following A2.

2.

and CE2 have timing identical to CE. On this diagram, when CE is LOW,

CE2 is HIGH. When

is HIGH,

is HIGH and CE2 is LOW.

is LOW and

3. Timing is shown assuming that the device was not enabled before entering into this sequence.
does not cause Q to be driven until after the following clock rising edge.

KQHZ

K QX

Taiwan Memory Technology, Inc. reserves the right P. 11 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

TE

C

H

t

CE

2

CE

2

CE

CE

2

OE

ADV

GW

GW

BWE

BW1

BW4

WRITE TIMING

CLK

t

A DS St A DS H

A DS P

A DSC

t

t KHt

A St A H

KC

KL

t

A D SSt A D SH

A DS C exte n ds burs t.

t

A D SSt A D SH

T35L6432A

A DD RESS

BW E,

BW 1- BW 4

G W

CE

(NO TE 2 )

A DV

O E

D

Q

A 3A 2A 1

BYTE WRIT E sign als a r e
ign or ed for first cy cle w hen

A DS P initialte s bu r st.

t

W St WH

t

CESt CEH

(NOTE 3)

t

D St DH

Hig h-Z

BURST RE A D Exte nd e d BURST W RIT E

D(A1) D(A2) D(A2+1) D(A2+2) D(A2+3) D(A3+1)D(A3)

t

O EHZ

Sing le W RITE

(NOTE 1)

(NOTE5)

AD V susp nd s bu rst .(NOTE4)

D(A2+1) D (A3+2)

BURST W RIT E

t WSt

t

A A St A A H

WH

DON'T CARE
UNDEFINED

Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst

address following A2.

2.

3.

and CE2 have timing identical to CE. On this diagram, when CE is LOW ,

and CE2 is HIGH. When

is HIGH ,

is HIGH and CE2 is LOW.

is LOW

must be HIGH before the input data setup and hold HIGH throughout the data hold time. This
prevents input/output data contention for the time period to the byte write enable inputs being
sampled.

4.

5. Full width WRITE can be initiated by

must be HIGH to permit a WRITE to the loaded address.

LOW or

HIGH and

,

-

LOW.

Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

TE

C

H

t

CE

2

CE

CE

2

CE

CE2

ADSP

ADSC

ADV

GW

ADSP

ADSC

READ/WRITE TIMING

KC

CL K

t KHt

KL

t

A DSSt A DSH

A DS P

A DSC

t

A St A H

T35L6432A

A DDRE SS

BW E

BW 1- B W 4

CE

(NO T E 2 )

A DV

O E

A 2 A 6

t WSt

t

CE St CEH

t

t

OEHZ

DSt

Sing le W RITE

KQ

D

High-Z D(A3) D(A5) D(A6)

t

KQLZ

Q

High -Z

Q(A1) Q(A 2) Q(A3 ) Q(A4) Q(A4+1) Q(A4+3)Q(A4+2)

Back-to-Back READs Pass-through

A 4

WH

t

DH

t

OELZ

t

KQ

REA D

(NOT E1)

BURST REA D

A5A 3A 1

Back-to-Back

DON'T CARE
UNDEFINED

WRITEs

Note: 1. Q(A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst

address following A4.

2.

3. The data bus (Q) remains in High-Z following a WRITE cycle unless an

and CE2 have timing identical to CE. On this diagram, when

and CE2 is HIGH. When

is HIGH,

is HIGH and CE2 is LOW.

is LOW,

,

is LOW

or

cycle is performed.

4.

5. Back-to-back READs may be controlled by either

is HIGH.

or

.

Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

TE

C

H

PACKAGE DIMENSIONS
100-LEAD QFP SSRAM (14 x 20 mm)

Preliminary T35L6432A

SYMBOL DIMENSIONS IN INCHES DIMENTION IN MM

A 0.130(MAX) 3.302(MAX)
A1
A2 0.004(MIN) 0.102(MIN)

b 0.012+0.004-0.002 0.300+0.102-0.051
D
E

e

HD'

HE'

L'

L1'

t 0.006+0.004-0.002 0.150+0.102-0.051

y 0.004(MAX) 0.102(MAX)

£c

Taiwan Memory Technology, Inc. reserves the right P.14 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

0.112¡Ó0.005 2.845¡Ó0.127

0.551¡Ó0.005 14.000¡Ó0.127
¡Ó0.005 20.000¡Ó0.127

0.787

0.026¡Ó0.006 0.650¡Ó0.152
¡Ó0.008 17.200¡Ó0.203

0.677
¡Ó0.008 23.200¡Ó0.203

0.913

0.032¡Ó0.008 0.800¡Ó0.203
¡Ó0.008 1.600¡Ó0.203

0.063

0¡C~12

¡C

0¡C~12

¡C

TE

C

H

PACKAGE DIMENSIONS
100-LEAD TQFP SSRAM (14 x 20 mm)

Preliminary T35L6432A

SYMBOL DIMENSIONS IN INCHES DIMENTION IN MM

A 0.063(MAX) 1.600(MAX)

¡Ó0.005 1.400¡Ó0.050

A1
A2 0.002(MIN) 0.050(MIN)
b 0.013+0.002-0.004 0.320+0.060-0.100
D
E
e
HD'
HE'
L'
L1'
t
y 0.003(MAX) 0.080(MAX)

£c

Taiwan Memory Technology, Inc. reserves the right P.15 Publication Date: DEC. 1998
to change products or specifications without notice. Revision:A

0.055

¡Ó0.004 14.000¡Ó0.100

0.551

¡Ó0.004 20.000¡Ó0.100

0.787

¡Ó0.006 0.650¡Ó0.152

0.026

¡Ó0.004 16.000¡Ó0.100

0.630

0.866¡Ó0.004 22.000¡Ó0.100
¡Ó0.006 0.600¡Ó0.150

0.024
¡Ó0.006 1.000¡Ó0.150

0.039
¡Ó0.002

0.006

0¡C~7

¡C

0.150+0.050-0.060

¡C

0¡C~7