Datasheet T2316405A, T2316407A Datasheet (Taiwan Memory Technology)

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CAS

CAS

Preliminary T2316407A

T2316405A

DRAM

FEATURES

•

Industry-standard x 4 pinouts and timing

functions

•

power supply : T2316405A 2.6V(±0.2V)

T2316407A 3.3V(±0.3V)

•

All device pins are TTL- compatible.

• 2048-cycle refresh in 32 ms.

•

Refresh modes:

RAS

(CBR) and HIDDEN.

•

Extended data-out (EDO) PAGE MODE

access cycle.

OPTION

TIMING MARKING

50ns (For T2316407A only) -50
60ns (For T2316407A only) -60
70ns (For T2316407A only) -70

10 0ns (For T2316405A only) -10

PACKAGE

26/24 -pin SOJ J
26/24 -pin TSOP-II S

PIN ARRANGEMENT (

Vcc

I/O1

I/O2

WE

RAS

NC

A10

A0
A1
A2
A3

Vcc

1
2
3
4
5

6

9
10
11
12
13

RAS

only,

CAS

BEFORE

Top View)

26

Vss

25

I/O4

24

I/O3

23

CAS

22

OE

SOJ

&

TSOP-II

21

198
18
17
16
15
14

A9

A8
A7
A6
A5
A4
Vss

4M x 4 DYNAMIC RAM

EDO PAGE MODE

GRNERAL DESCRIPTION

The T2316405A and T2316407A is a randomly
accessed solid state memory containing 16,777,216
bits organized in a x 4 configuration. It offers Fast
Page mode with Extended Data Output (EDO).

During READ or WRITE cycles, each of the 4
memory bits (1 bit per I/O) is uniquely addressed
through the 22 address bits, which are entered 11
bits (A0-A10) at a time.
bits and

A READ or WRITE cycle is selected with
the
READ mode while a logic LOW on
WRITE mode. During a WRITE cycle, data -in is
latched by the falling edge of
whichever occurs last. When
to
output pins remain open (High-Z) until the next

CAS

When WE falls after
Write cycle). OE must be taken HIGH to disable
the data-outputs prior to applying input data.

The four data inputs and four data outputs are
routed through four pins using common I/O, and pin
direction is controlled by

CAS

latches the latter 11 bits.

WE

input. A logic HIGH on

going LOW ( EARLY WRITE cycle), the

cycle.

A Late Write or Read-Modify -Write occurs.

RAS

latches the first 11

WE

goes Low prior

was taken LOW (Late

WE

and OE.

WE

WE

or

dictates
dictates

,

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: APR 2001
to change products or specifications without notice. Revision:0.B

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BLOCK DIAGRAM

WE

CAS

NO.2 CLOCK

GENERATOR

COLUMN­ADDRESS

11

BUFFER(11)

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10

RAS

PIN DESCRIPTION

11

BUFFERS (11)

REFRESH

CONTROLLER

REFRESH

COUNTER

11

ROW-

ADDRESS

NO.1 CLOCK
GENERATOR

T2316405A

Preliminary T2316407A

11

CONTROL

LOGIC

ROW

DECODER

1

2048

10

2048

2048

2048

2048

SELECT

COMPLEMENT

DATA-IN
BUFFER

DATA-OUT

BUFFER

COLUMN

DECODER

1024

SENSE AMPLIFIERS

I/O GATING

4096 x 1024 x 4

MEMORY

(2 of 4096)

ROW SELECT

1024

ARRAY

4

4

4

4

(1 of 2)

ROW TRANSFER

(1 of 2)

Vcc

Vss

IO1
IO2

IO3
IO4

OE

PIN NO. SYM. TYPE DESCRIPTION

8~12,15~19,21 A0-A10 Input Address In put

5 RAS

23

4 WE

22 OE

Input Row Address Strobe
Input Column Address Strobe
Input Write Enable
Input Output Enable

2,3,24,25 I/O1 -I/O4 Input/ Output Data Input/ Output

1,13 Vcc Supply Power

14,26 Vss Ground Ground

6 NC No Connect

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: APR 2001
to change products or specifications without notice. Revision:0.B

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ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on Any Pin Relative To Vss VT -0.5 to 4.6 V
Supply Voltage Relative To Vss Vcc -0.5 to 4.6 V

Preliminary T2316407A

T2316405A

Short circuit Output Current I
Power Dissipation PT 1 W
Operating Temperature T
Storage Temperature T

RECOMMENDED DC OPERATING CONDITIONS

(Ta = 0 to +70°°C) For T2316405A-10 only

Parameter Symbol Min. Typ Max. Unit Notes

Vss 0 0 0 V

Supply Voltage

Vcc 2.4 2.6 2.8 V 1
Input High Voltage VIH 2.0 - Vcc+0.3V V 1
Input Low Voltage VIL -0.3 - 0.8 V 1

(Ta = 0 to +70°°C) For T2316407A-50/60/70 only

Parameter Symbol Min. Typ Max. Unit Notes

Vss 0 0 0 V

Supply Voltage

Vcc 3.0 3.3 3.6 V 1

50 mA

out

0 to 70

OPR

-55 to 125

stg

°
°

C
C

Input High Voltage VIH 2.0 - Vcc+0.3V V 1
Input Low Voltage VIL -0.3 - 0.8 V 1

Notes : 1. All voltages referenced to Vss

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: APR 2001
to change products or specifications without notice. Revision:0.B

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T2316405A

RAS

CAS

RAS

CAS

DC CHARACTERISTICS

(Ta = 0 to 70

) T2316405A -10 Vcc = 2.6V ±0.2V, Vss = 0V

°°

C

Preliminary T2316407A

T2316407A-50/60/70 Vcc = 3.3V ±0.3V, Vss = 0V

-50 -60 -70 -10

Parameter Symbol

Input Leakage Current ILI -5 5 -5 5 -5 5 -5 5 uA

Output Leakage
Current

Output High Voltage VOH 2.0 - 2.0 - 2.0 - 2.0 - V

Min Max Min Max Min Max Min Ma

ILO -5 5 -5 5 -5 5 -5 5 uA

x

Unit

Test Condition

0V≤ Vin ≤ Vcc+ 0.3V
Other pins = 0V

0V≤ Vout≤ Vcc
Dout = disable
High Iout= -2.0mA

Output Low Voltage VOL - 0.8 - 0.8 - 0.8 - 0.8 V

Operating Current Icc1 - 95 - 90 - 80 - 50 mA

Standby Current Icc2 - 2 - 2 - 2 - 2 mA

Standby Current Icc3 - 0.5 - 0.5 - 0.5 - 0.5 mA

EDO Page Mode
Current

RAS

-only refresh

Current

CAS

Before

Refresh Current

RAS

Icc4 - 95 - 90 - 80 - 50 mA

Icc5 - 95 - 90 - 80 - 50 mA

Icc6 - 95 - 90 - 80 - 50 mA

Low Iout=2.0mA

,

cycling

tRC=min
TTL interface,

RAS,CAS

D

OUT

CMOS interface,

RAS, CAS
RAS

cycling, tPC= min

CAS

cycling, tRC = min

tRC= min

=High-Z

=VIL,

=VIH,

,

=VIH,

> Vcc-0.2V

CAS

cycling,

Note: Icc depends on output load condition when the device is selected.
Icc max is specified at the output open condition, Icc is specified as an average current.

CAPACITANCE

(Ta =25°C, f = 1M HZ, T2316405A -10 Vcc = 2.6V, T2316407A-50/60/70 Vcc = 3.3V)

RAS

Parameter Symbol Typ Max Unit

Input Capacitance

(address)

Input Capacitance

RAS,CAS,WE,OE

(

Output Capacitance

(data-in/out)

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to change products or specifications without notice. Revision:0.B

)

CI1 - 5 pF

CI2 - 7 pF

C

- 7 pF

I/O

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T2316405A

CAS

CAS

CAS

CAS

CAS

RAS

10,16

AC CHARACTERISTICS

TEST CONDITIONS:
T2316405A-10 Vcc = 2.6V ±0.2V , T2316407A-50/60/70 Vcc = 3.3V ±0.3V
VIH/VIL=2.0/0.8V,VOH/VOL=2.0/0.8V
Input rise and fall times: 2ns , Output Load: 2TTL gate + CL (100pF)

(note 1,2,3) (Ta = 0 to 70°C)

Preliminary T2316407A

-50 -60 -70 -10 AC CHARACTERISTICS

Min Max Min Max Min Max Min Max

84 104 124 180 ns

108 135 160 240 ns

20 25 30 40 ns
56 68 78 120 ns

50 60 70 100 ns
13 15 20 25 ns
13 15 20 25 ns
25 30 35 50 ns 8

30 35 40 55 ns

50 10K 60 10K 70 10K 100 10K ns

100

50

K

8 10 13 25 ns

30 40 50 70 ns

8 10K 10 10K 13 10K 25 10K ns
38 40 45 100 ns
10 10 10 10 ns
12 37 14 45 14 50 25 75 ns

5 5 5 5 ns

0 0 0 0 ns

8 10 10 15 ns

10 25 12 30 12 35 20 50 ns

0 0 0 0 ns

8 10 13 20 ns

21 24 27 45 ns
25 30 35 50 ns

0 0 0 0 ns 14

0 0 0 0 ns

0 0 0 0 ns

0 0 0 0 ns

0 12 0 15 0 20 0 25 ns

60

100

K

70

100

K

100

or

SYM

RC
RWC
PC
PCM

t

RAC

t

CAC

t

OAC
AA

t

ACP

t

RAS

t

RASC

t

RSH

tRP
t

CAS

t

CSH

tCP
t

RCD

t

CRP
ASR

RAH

t

RAD
ASC

CAH

tAR

t

RAL
RCS

t

RCH

t

RRH

t

CLZ

t

OFF1

PARAMETER

Read or Write Cycle Time t
Read Write Cycle Time t
EDO-Page-Mode Read or Write Cycle Time t
EDO-Page-Mode Read-Write Cycle Time t

Access Time From
Access Time From
Access Time From OE

Access Time From Column Address t
Access Time From

RAS

Pulse Width

RAS

Pulse Width (EDO Page Mode)

RAS

Hold Time

RAS

Precharge Time
Pulse Width

CAS

Hold Time

Precharge Time (EDO Page Mode)
RAS
CAS

Row Address Setup Time t
Row Address Hold Time t

RAS

Column Address Setup Time t
Column Address Hold Time t
Column Address Hold Time (Reference to

RAS

Column Address to
Read Command Setup Time t
Read Command Hold Time Reference to

Read Command Hold Time Reference to

RAS

Output Buffer Turn-off Delay From

Taiwan Memory Technology, Inc. reserves the right P. 5 Publication Date: APR. 2001
to change products or specifications without notice. Revision:0.B

CAS

to

RAS

to

to Column Address Delay Time

)

to Output in Low -Z

RAS
CAS

Precharge

Delay Time
Precharge Time

RAS

Lead Time

CAS

100

K

UNIT Notes

4
5
13

ns

7

8

9,14

9

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T2316405A

RAS

WE

RAS

CAS

OE

CAS

OE

RAS

AC CHARACTERISTICS

(continued)

Preliminary T2316407A

PARAMETER

Output Buffer Turn-off to
Write Command Setup Time t

Write Command Hold Time t
Write Command Hold Time (Reference

RAS

to
Write Command Pulse Width tWP

Write Command to
Write Command to

Data-in Setup Time tDS
Data-in Hold Time tDH

Data-in Hold Time (Reference to

Column Address to WE Delay Time

Transition Time (rise or fall) tT
Refresh Period (2048 cycles) t

Modify -Write Cycle

Refresh Cycle
Data Output Hold After

Output Disable Delay From

)

to

CAS

to

to

CAS

Setup Time (CBR REFRESH)

CAS

Hold Time (CBR REFRESH)

OE

Hold Time From WEDuring Read-

OE

Low to
High Hold Time From

OE

High Pulse Width
Setup Prior to

Delay Time

WE

Delay Time

Precharge Time

CAS

High Setup Time

OE

RAS

Lead Time

CAS

Lead Time

During Hidden

CAS

WE

RAS

)

High

Returning Low

SYM

t

OFF2
WCS
WCH

t

WCR

t

RWL

t

CWL

t

DHR

t

RWD

t

AWD

t

CWD

REF

t

RPC

t

CSR

t

CHR

t

OEH

t

OES

t

OEH

C
t

OEP

t

ORD

t

COH

t

WHZ

-50 -60 -70 -10 AC CHARACTERISTICS

Min Max Min Max Min Max Min Max

0 12
0
8

21

8

10

8
0

8
21
64
39
26

2 50
32 32 32 32 ms

5

5

8

8

5

5
10

5

5

10 15 20 25 ns

15 0 20 0 25 ns

0

0 0 ns

0

13 15 ns

10

27 40 ns

24

10 15 ns

10

13 25 ns

10

13 25 ns

10

0 0 ns

0

13 20 ns

10

27 45 ns

24

94 130 ns

79

59 80 ns

49

44 55 ns

34

50 2 50 2 50 ns

2

5 5 ns

5

10 10 ns

10

10 10 ns

10

13 25 ns

10

5 5 ns

5

5 5 ns

5

10 10 ns

10

10 13 ns

7

5 5 ns

5

UNIT Notes

16
11,14

14

14
14
14
12
12

11
11
11
2,3

6
6
15

Taiwan Memory Technology, Inc. reserves the right P. 6 Publication Date: APR. 2001
to change products or specifications without notice. Revision:0.B

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T2316405A

RAS

≥

≥

≥

≥

RAS

WE

Notes:

1. An initial pause of 200us is required after
power-up followed by eight
cycles (
device operation is assured. The eight
cycle wake-ups should be repeated any time
the t

2. VIH(2.0V) and VIL(0.8V) are reference
levels for measuring timing of input signals.
Transition times are measured between
V

IH(2.0V)

3. In addition to meet the transition rate
specification, all input signals must transit
between VIH and VIL in a monotonic manner.

4. Assume that t
greater than the maximum recommended value
shown in this table, t
amount that t

5. Assume that t

6. Enables on-chip refresh and address counters.

7. Operation within the t
that t
specified as a reference point only; if t
greater than the specified t
access time is controlled by t

8. Operation within the t
t

RAC

specified as a reference point only; if t
greater than the specified t
access time is controlled by tAA.

9. Either t
READ cycle.

10. t

OFF1

output achieves the open circuit condition; it is
not a reference to V

RAS

only or CBR) before proper

refresh requirement is exceeded.

REF

and V

IL(0.8V)

< t

RCD

RCD

RCD

(max) can be met. t

RAC

(max) can be met. t

or t

RCH

(max) defines the time at which the

RCD

RAC

exceeds the value shown.

t

RCD

RCD

RAD

must be satisfied for a

RRH

or VOL.

OH

RAS

refresh

.

(max). If t

will increase by the

(max) .

(max) limit ensures

RCD

(max) limit,

RCD

.

CAC

limit ensures that

RAD

(max) limit,

RAD

is

RCD

(max) is

is

RCD

(max) is

is

RAD

Preliminary T2316407A

11. t

12. These parameters are referenced to

13. During a READ cycle, if OE is low then taken

14. WRITE command is defined as

15. LATE WRITE and READ-MODIFY-WRITE

16. The I/Os open during READ cycles once

, t

WCS

restrictive operating parameters in LATE
WRITE and READ -MODIFY-WRITE cycles

only. If t
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire

cycle. If t
t

(min) and t

AWD
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of I/O (at access time and until

or OE go back to VIH) is indeterminate.

OE

held high and WE taken low after
goes low result in a LATE WRITE (OE­controlled) cycle.

leading edge in EARLY WRITE cycles and

leading edge in LATE WRITE or READ-

MODIFY-WRITE cycles.

HIGH before

OE

if
WRITE or READ-MODIFY-WRITE
operation is not possible.

cycles must have both t
(OE high during WRITE cycle) in order to
ensure that the output buffers will be open
during the WRITE cycles.

t

OFF1

is tied permanently low, a LATE

or t

RWD

WCS

RWD

OFF2

, t

≥ t

CAS

occur.

and t

AWD

(min), the cycle is an

WCS

t

(min), t

RWD

OFF2

t

CWD

WE

and t

CWD

goes high, I/O goes open,

are

CWD

AWD

(min), the

CAS

and

CAS

CAS

going low.

met

OEH

Taiwan Memory Technology, Inc. reserves the right P. 7 Publication Date: APR. 2001
to change products or specifications without notice. Revision:0.B

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T2316405A

Preliminary T2316407A

READ CYCLE

t

R C

t

R A S

V

IH

RAS

V

CAS

ADD R

WE

I/O

OE

IL

t

C R P

V

IH

V

IL

t

t

A S R

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

t

R A D
R A H

t

R C D

t

A R

t

A S C

t

R C S

t

C SH

t

R SH

t

C A S

t

R AL

t

C A H

C O L U M N R O WRO W

t

A A

t

R AC

t

C AC

t

C L Z

t

O A C

EARLY WRITE CYCLE

t

R P

t

R R H

t

RC H

N O T E 1
t

OF F 1

V A L ID D A T A

t

O F F 2

O P E NO P E N

Note: t

V

IH

RAS

V

IL

t

C R P

V

IH

CAS

V

IL

t

t

A S R

V

IH

ADD R

V

IL

V

IH

WE

V

IL

V

IOH

I/O

V

IOL

V

IH

OE

V

IL

is referenced from the rising edge of

OFF1

R A D

t

R A H

t
t

t

RC D

t

A R

t

A S C

t

WC S

t

D S

V A L ID D A T A

RAS

R C
R A S

C O L U M N R O WR O W

or

t

t

C S H

t

R S H

t

C A S

t

R A L

t

C A H

t

C W L

t

R W L

t

W C R

t

W C H

t

W P

t

D H R

t

D H

CAS

, whichever occurs last.

R P

DON'T CARE

UNDEFINED

2

Taiwan Memory Technology, Inc. reserves the right P. 8 Publication Date: APR. 2001

to change products or specifications without notice. Revision:0.B

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RAS

CAS

ADDR

Note: 1. t

2. t

TE

(LATE WRITE and READ -MODIFY-WRITE CYCLES)

V

IH

RAS

V

IL

t

C R P

V

IH

CAS

V

IL

t

V

IH

ADDR

V

IL

V

IH

WE

V

IL

V

IOH

I/O

V

IOL

V

IH

OE

V

IL

V

IH

RAS

V

IL

t

C R P

V

IH

CAS

V

IL

t

R A D

t

A S RtR A H

V

IH

V

IL

V

IH

WE

V

IL

V

OH

I/O

V

OL

V

IH

OE

V

IL

is referenced from the rising edge of

OFF1

can be measured from falling edge of

PC

CAS

to rising edge of

t

A R

t

R AD

t

A SR

R A H

EDO-PAGE-MODE READ CYCLE

t

C S H

t

R C D

t

A R

t

A S C

C O L U M N R O WR O W

t

R C S

t

C L Z

CAS

. Both measurements must meet the t

READ WRITE CYCLE

t

R WC

t

R A S

t

C S H

t

R SH

t

C A S

t

R AL

t

C A H

t

R WD

t

C WD

t

A WD

t

A A

t

R A C

t

C AC

VALID D

t

OA C

t

R A S C

t

P C

t

C P

t

A S CtC A H

C O L U M N

t

A A

t

A C P

t

t

VA L ID

D A T A

C A C

C O H

or

CAS

to falling edge of

OUT

t

OF F 2

t

C A S

VA LID

DAT A

t

, whichever occurs last.

t

t

C A H

t

A A

t

R A C

t

C A C

t

t

A SC

t

R C S

C A S

O A C
t

O E S

t

RC D

t

C L Z

C O L U M N RO WRO W

T2316405A

Preliminary T2316407A

t

R P

t

C WL

t

R WL

t

WP

tDHt

D S

O F F 2

V A LID D

t

C P

t

A S CtC A H

C O L U M N

t

C L Z

t

O E H C

t

O E P

IN

CAS

O P E NO P E N

t

OE H

t

R P

t

t
t
t

t

A A

A C P

C A C

t

O A C

R S H
C A S

t

R A L

t

O E S

t

R C H

V AL ID

D A T A

t

O F F 2

t

C P N

DON'T CARE

UNDEF I NE D

, or from rising edge of

specification.

PC

t

R R H

N O T E 1

t

O F F 1

O P E NO P E N

2

Taiwan Memory Technology, Inc. reserves the right P. 9 Publication Date: APR. 2001

to change products or specifications without notice. Revision:0.B

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T2316405A

Preliminary T2316407A

EDO-PAGE-MODE EARLY -WRITE CYCLE

V

IH

RAS

V

CAS

ADDR

WE

I/O

IL

t

C R P

V

IH

V

IL

t

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

OE

V

IL

A S RtR A H

t

t

C S H

R A D

t

R C D

t

A R

t

A S CtC A H

t

W C S

t

DS

V AL ID D A T A

t

C A S

C O L U M N C O L U M N C O L U M N RO WRO W

t

C W L

t

W C H

t

W P

t

W C R

t

D H R

t

D H

t

t

P C

t

C P

t

A S CtC A H

t

W C S

t

D StD H

VA L ID D A T A

R A S C

t
t
t

t

C A S

C W L
W C H
W P

t

C P

t

A S CtC A H

t

W C S

t

D S

VALID DATA

t

R A L

t

C W L

t

W C H

t

t

t
t

W P

D H

R S H
C A S

t

R W L

t

C P N

EDO-PAGE-MODE READ -WRITE CYCLE

RAS

CAS

ADDR

WE

I/O

OE

(LATE WRITE and READ -MODIFY-WRITE CYCLES)

t

R A S C

V

IH

V

IL

t

C R P

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

t

A S RtR A H

t
t

A R
R A D

t

R A C

t

R C D

t

A S CtC A H

C O L U M N RO WRO W

t

R C S

t

A A

t

C A C

t

C L Z

t

t

C S H

O A C

t

t

A W D

t

C W D

t

R W D

t

t

VALI D

D

C A S

C W L

t

W P

t

D H

D S

O UT

VAL ID

D

I N

t

O F F 2

t

C PtC A S

t

A S CtC A H

C O L U M N

t

A A

t

A C P

t

C A C

t

C L Z

t

O A C

t

P C M

t
t

t

A W D
C W D

C W L
t

t

t

DS

V ALI D

D

OUT

W P

DH

VALI D

D

I N

t

O F F 2

t

C P

t

A S CtC A H

C O L U M N

t

A A

t

A C P

t

C A C

t

C L Z

t

O A C

t

A W D

t

C W D

t

t

D S

VALI D

D

OUT

t

R S H

t

C A S

R A L

V ALI D

D

I N

t

O F F 2

t

O E H

t

t

t

W P

D H

t

t

C W L

O P E NO P E N

R P

t

C P N

R W L

D ON 'T CAR E

UNDEF I NE D

t

Note:

2

Taiwan Memory Technology, Inc. reserves the right P.10 Publication Date: APR. 2001

can be measured from falling edge to falling edge of

PC

CAS

. Both measurements must meet the tPC specification.

CAS

, or from rising edge to rising edge of

to change products or specifications without notice. Revision:0.B

TE

C

H

tm

T2316405A

RAS

OE,WE

Preliminary T2316407A

EDO-PAGE-MODE READ-EARLY-WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

V

IH

RAS

V

CAS

ADDR

WE

I/O

OE

IL

t

C R P

V

IH

V

IL

t

R A D

t

A S RtR A H

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

t

C S H

t

R C D

t

A R

t

AS C

C O L U M N ( A ) C O L U M N ( B ) C O L U M N ( N )

t

R C S

t

R AC

O P E N

t

P C

t

C A S

t

C A H

t

A A

t

C A C

t

V A L ID D A T A ( A )

OA C

t

C P

t

A S CtC A H

t

A C P

t

R A SC

t

A A

t

C A C

t

C O H

t

C A S

t

R C H

t

P C

t

t

WH Z

V A L ID

D A T A ( B )

C P

t

AS CtC A H

t

W C S

t

VALID DATA

t

D StD H

IN

WC H

t

t

R SH

t

C A S

R A L

t

R P

t

C P

R O WR O W

ONLY REFRESH CYCLE

(ADDR=A0-A10;

V

IH

RAS

V

IL

V

IH

CAS

V

IL

V

IH

ADDR

V

IL

V

OH

I/O

V

OL

t

t

C R P

A S R

t

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=DON‘T CARE)

t

t

R A S

RC

O P E N

t

R P C

t

R P

RO WR O W

DON'T CARE

UNDEFINED

2

Taiwan Memory Technology, Inc. reserves the right P.11 Publication Date: APR. 2001

to change products or specifications without notice. Revision:0.B

C

H

tm

T2316405A

WE

OE

Note: 1. t

TE

Preliminary T2316407A

CBR REFRESH CYCLE

(A0-A10;

t

R P

V

I H

R A S

V

IL

V

I H

C A S

V

IL

I/O

V

I H

WE

V

IL

V

IH

R A S

V

IL

V

IH

C A S

V

IL

V

IH

A D D R

V

IL

V

OH

I /O

V

OL

V

IH

OE

V

IL

is referenced from the rising edge of

OFF1

t

R P C

t

C P N

t

C R P

t

A S RtR A H

t

C S R

t

W R PtW R H

t

C H R

HIDDEN REFRESH CYCLE

t

t

R A D

R O W

O P E N V A L I D D A T A

(

(R E A D)

t

R C D

A R

t

R A S

t

OE

t

R A S

=HIGH;

t

R A L

A S CtC A H

C O L U M N

t

A A

t

R A C

=DON‘T CARE)

t

R P

t

R P CtC S R

O P E N

t

W R PtW R H

=LOW)

t

R P

t

R S H

t

C A C

t

C L Z

t

O A C
t

ORD

RAS

or

CAS

, whichever occurs last.

t

C H R

t

R A S

(R E F R E S H )

t

R A S

t

C H R

t

O F F 2

N O T E 1

t

O FF 1

O P E N

Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: APR. 2001
to change products or specifications without notice. Revision:0.B

TE

C

H

tm

T2316405A

Preliminary T2316407A

PACKAGE DIMENSIONS
24-LEAD SOJ DRAM (300 mil)

SYMBOL DIMENSIONS IN INCHES DIMENTIONS IN MM

A 0.673±0.002 17.09±0.05

B 0.300±0.002 7.62±0.13
C 0.060±0.002 1.52±0.05

D 0.050±0.001 1.27±0.03

E 0.063±0.001 1.63±0.03

F 0.015±0.002 0.38±0.05

G 0.036±0.002 0.91±0.05

H 0.050±0.002 1.27±0.05

I 0.018±0.002 0.46±0.05
J 0.028±0.002 0.71±0.05

K 0.336±0.003 8.53±0.08

L 0.010±0.001 0.25±0.03

M 0.029±0.002 0.74±0.05

N 0.268±0.003 6.81±0.08
O 0.300±0.002 7.62±0.05

P 0.042±0.001 1.07±0.03

Q 0.129±0.004 3.28±0.10

y 0.004(MAX) 0.102(MAX)

Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: APR. 2001
to change products or specifications without notice. Revision:0.B

TE

C

H

tm

T2316405A

Preliminary T2316407A

PACKAGE DIMENSIONS
24-LEAD TSOP II DRAM (300 mil)

"A"

SYMBOL DIMENSIONS IN INCHES DIMENTIONS IN MM

A 0.047(MAX) 1.20(MAX)
A1 0.004±0.002 0.10±0.05
A2 0.039±0.002 1.00±0.05

b 0.016±0.004 0.41±0.11

D 0.675±0.005 17.14±0.13

E 0.368±0.003 9.22±0.20

E1 0.300±0.005 7.62±0.13

e 0.050 1.27

L’ 0.020±0.004 0.50±0.10

L1’ 0.031 0.80

y 0.002±0.002 0.05±0.05

θ

Taiwan Memory Technology, Inc. reserves the right P. 14 Publication Date: APR. 2001
to change products or specifications without notice. Revision:0.B

1°~ 5° 1°~ 5°