Datasheet T2316162A Datasheet (Taiwan Memory Technology)

tm

TE

CH

T2316162A

DRAM

FEATURES

Industry-standard x 16 pinouts and timing

•

functions.

Single 5V (±10%) power supply.

•

All device pins are TTL- compatible.

•

1K-cycle refresh in 16ms.

•

Refresh modes:

•

RAS

(CBR) and HIDDEN.

Extended data-out (EDO) PAGE MODE access

•

RAS

only,

CAS

BEFORE

cycle.

BYTE WRITE and BYTE READ access cycles.

•

OPTION

TIMING MARKING

45ns -45
50ns -50
60ns -60

PACKAGE

42-pin SOJ J
44/50-pin TSOPII S

1024K x 16 DYNAMIC RAM

EDO PAGE MODE

GENERAL DESCRIPTION

The T2316162A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316162A has both
BYTE WRITE and WORD WRITE access cycles

CAS

via two
Extended Data Output.
The T2316162A
determined by the first
by the last to transition back high. Use only one of
the two
during WRITE will result in a BYTE WRITE.

CASL
data into the lower byte (DQ0~DQ7), and
transiting low will write data into the upper byte
(DQ8~DQ15).

pins. It offers Fast Page mode with

CAS

function and timing are

CAS

to transition low and

CAS

and leave the other staying high

transiting low in a WRITE cycle will write

CASH

PIN ASSIGNMENT ( Top View )

V

DD

1

DQ0

V
DQ0
DQ1
DQ2
DQ3

V
DQ4
DQ5
DQ6
DQ7

NC

NC
WE
RAS

NC

NC

V

DD

1

2

3

4

5

DD

6

7
8

9

10
11
12
13
14
15
16

A0

17

A1

18

A2

19

A3

20

DD

21

Vss

42

DQ15

41

DQ14

40

DQ13

39

DQ12

38

Vss

37

DQ11

36

DQ10

35

DQ9

34

DQ8

33

NC

32

CASL

31

CASH

30

OE

29

A9

28

A8

27

A7

26

A6

25

A5

24

A4

23

Vss

22

DQ1
DQ2
DQ3

VDD
DQ4
DQ5
DQ6
DQ7

WE
RAS

V

2
3
4
5
6
7
8
9
10

NC

11

NC

15

NC

16
17
18

NC

19

NC

20

A0

21

A1

22

A2

23

A3

24

DD

25

TM Technology Inc. reserves the right P. 1 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

Vss

50

DQ15

49

DQ14

48

DQ13

47

DQ12

46

Vss

45

DQ11

44

DQ10

43

DQ9

42

DQ8

41

NC

40

NC

36

CASL

35

CASH

34

OE

33

A9

32

A8

31

A7

30

A6

29

A5

28

A4

27

Vss

26

TE

tm

FUNCTIONAL BLOCK DIAGRAM

CH

T2316162A

WE

RAS

CASL

CASH

NO.2 CLOCK

GENERATOR

COLUMN.
ADDRESS

10
A0
A1
A2

A3
A4

A5
A6
A7

A8
A9

CONTROLLER

10

REFRESH

REFRESH

COUNTER

ADDRESS

BUFFERS(10)

NO.1 CLOCK

GENERATOR

CAS

BUFFER

10

ROW.

CONTROL

LOGIC

10

ROW

DECODER

10

1024

DATA-IN BUFFER

COLUMN

DECODER

1024

SENSE AMPLIFIERS

I/O GATING

1024x 16

1024x 1024 x 16

MEMORY

ARRAY

DQ0

16

DATA-OUT

BUFFER

1
6

16

.
.

DQ15

OE

Vcc

Vss

PIN DESCRIPTIONS

SYM. TYPE DESCRIPTION

A0-A9 Input Address Input

RAS

CASH

CASL

WE

OE

DQ0 – DQ15 Input/ Output Data Input/ Output

Vcc Supply Power, 5V
Vss Ground Ground

NC - No Connect

TM Technology Inc. reserves the right P. 2 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

Input Row Address Strobe
Input Column Address Strobe /Upper Byte Control
Input Column Address Strobe /Lower Byte Control
Input Write Enable
Input Output Enable

TE

tm

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any pin Relative to VSS.... -1V to +7V

Operating Temperature, Ta (ambient).....

Storage Temperature (plastic)...... -55°C to +150°C

Power Dissipation ........................................ 1.2W

Short Circuit Output Current........................ 50mA

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS

(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)

DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES

Supply Voltage Vcc 4.5 5.5 V 1
Supply Voltage Vss 0 0 V
Input High (Logic) voltage VIH 2.4 Vcc+1 V 1
Input Low (Logic) voltage VIL -1.0 0.8 V 1
Input Leakage Current

Output Leakage Current
Output High Voltage IOH = -5 mA VOH 2.4 Vcc V

Output Low Voltage IOL = 4.2 mA VOL 0 0.4 V

CH

T2316162A

*Stresses greater than those listed under "Absolute
Maxi mum Rat ings" ma y caus e per manent damag e
to the device. This is a stress rating only and

………0°C to +70°C

0V ≤ VIN ≤ 7V
0V ≤ V

Output(s) disabled

OUT

≤ 7V

functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.

ILI -10 10 uA

ILO -10 10 uA

Note: 1.All Voltages referenced to Vss

DESCRIPTION CONDITIONS SYM. -45 -50 -60 UNITS NOTES

Operating Current
TTL Standby Current

RAS-only refresh Current

EDO Page Mode Current tPC = min I

CAS Before RAS Refresh

Current
CMOS Standby Current

1. Icc depends on output load condition when the device is selected.

Note:

Icc max is specified at the output open condition.

2. Address can be changed twice or less while

3. Address can be changed once or less while

RAS,CAS cycling , tRC = min

TTL interface,

CAS=VIH, D

t

RC = min I

t

RC = min Icc5 190 180 170 mA

CMOS interface,

0.2V

RAS,

=High-Z

OUT

RAS,CAS>Vcc-

RAS

CAS

= VIL.

= VIH.

Icc1 190 180 170 mA 1,2
I

2 2 2 mA

cc2

190 180 170 mA 2

cc3

150 140 130 mA 1,3

cc4

I

1.0 1.0 1.0 mA 1

cc6

MAX

TM Technology Inc. reserves the right P. 3 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

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tm

CAPACITANCE

(Ta =25°C, Vcc =5V ±10 %)

Input Capacitance (address) CI1 - 5 pF 1
Input Capacitance (clocks) CI2 - 7 pF 1
Output Capacitance (data-in, data-out) CDQ - 10 pF 1

1. Capacitance measured with Boonton Meter or effective capacitance measuring method.

Note:

AC ELECTRICAL CHARACTERISTICS

(Ta =0 to 70°C, Vcc=5V ±10 %, Vss=0V)
Test Conditions

CH

T2316162A

Parameter Symbol Typ Max Unit Notes

(note 14)

(note 29)

AC CHARACTERISTICS

PARAMETER

Read or Write Cycle Time tRC 80 84 110 ns
Read Write Cycle Time t
EDO-Page-Mode Read or Write Cycle Time tPC 16 20 25 ns 22
EDO-Page-Mode Read-Write Cycle Time t

RAS
CAS
OE

CAS

RAS

Precharge

Lead Time

Access Time From
Access Time From
Access Time From

Access Time From Column Address tAA 19 25 30 ns
Access Time From

RAS

Pulse Width

RAS

Pulse Width (EDO Page Mode)

RAS

Hold Time

RAS

Precharge Time

CAS

Pulse Width

CAS

Hold Time

CAS

Precharge Time (EDO Page Mode)
RAS
CAS

Row Address Setup Time t
Row Address Hold Time t

RAS

Column Address Setup Time t
Column Address Hold Time t
Column Address Hold Time (Reference to

RAS

Column Address to

CAS

to

to

to Column Address Delay Time

)

Delay Time

RAS

Precharge Time

SYM

RWC

PCM

t

RAC

t

CAC

t

OAC

t

ACP

t

RAS

t

RASC

t

RSH

tRP 28 30 40 ns
t

CAS

t

CSH

tCP 5 6 10 ns 23
t

RCD

t

CRP
ASR

RAH

t

RAD
ASC

CAH

tAR 35 38 45 ns

t

RAL

MIN MAX MIN MAX MIN MAX

105 113 140 ns

46 58 70 ns 22
45 50 60 ns 4

11 13 15 ns 5,20
11 13 15 ns 13,20

22 27 35 ns 20
45 10K 50 10K 60 10K ns

45 100K 50 100K 60 100K ns

11 13 15 ns 27

6 10K 8 10K 15 10K ns 26
40 40 60 ns 19

10 34 12 37 20 45 ns 7,18
5 5 5 ns 19
0 0 0 ns

5 8 10 ns

8 26 10 28 12 30 ns 8
0 0 0 ns 18

6 8 10 ns 18

19 23 30 ns

-45

-50 -60
UNIT Notes

TM Technology Inc. reserves the right P. 4 Publication Date:APR. 2002
to change products or specifications without notice. Revision:E

TE

tm

AC ELECTRICAL CHARACTERISTICS

CH

T2316162A

(

continued

)

PARAMETER

Read Command Setup Time t
Read Command Hold Time Reference to
Read Command Hold Time Reference to

CAS

to Output in Low-Z

Output Buffer Turn-off Delay From

RAS

Output Buffer Turn-off to
Write Command Setup Time t

Write Command Hold Time t
Write Command Hold Time (Reference to

RAS

)

Write Command Pulse Width tWP 6 8 15 ns 15
Write Command to
Write Command to

Data-in Setup Time tDS 0 0 0 ns 12,20
Data-in Hold Time tDH 6 8 10 ns 12,20

Data-in Hold Time (Reference to

RAS

Column Address to

CAS
Transition Time (rise or fall) tT 2.5 50 2.5 50 2.5 50 ns 2,3
Refresh Period (1024 cycles) t

RAS

CAS

CAS

OE
Modify-Write Cycle

OE

OE

OE

OE
Refresh Cycle

Last
Returning High

Data Output Hold After
Output Disable Delay From

WE

to

WE

to

CAS

to
Setup Time (CBR REFRESH)
Hold Time (CBR REFRESH)

Hold Time From

Low to
High Hold Time From
High Pulse Width
Setup Prior to

CAS

CAS

Going Low to First

RAS
CAS

Delay Time

WE

Delay Time

Precharge Time

WE

High Setup Time

CAS

CAS

CAS

OE

Lead Time
Lead Time

RAS

Delay Time

During Read-

CAS

High

During Hidden

CAS

Returning Low

WE

CAS
RAS

)

or

t
t
t
t

t

t

t
t

t
t
t
t

t
t
t
t

t
t
t
t

t

t
t

SYM

RCS
RCH

RRH
CLZ
OFF1

OFF2
WCS

WCH
WCR

RWL
CWL

DHR
RWD
AWD
CWD

REF
RPC

CSR
CHR
OEH

OES
OEHC
OEP
ORD

CLCH

COH
WHZ

MIN MAX MIN MAX MIN MAX

0 0 0 ns 15,18

0 0 0 ns 9,15,19
0 0 0 ns 9

3 3 3 ns 20

3 15 3 15 3 15 ns 10,17,

8 8 15 ns 17,28

0 0 0 ns 11,15,1

6 8 10 ns 15,27

35 38 45 ns 15

9 9 10 ns 15
8 8 10 ns 15,19

35 38 45 ns

61 64 85 ns 11

35 39 55 ns 11

27 27 40 ns 11,18

16 16 16 ms

10 10 10 ns
10 10 10 ns 1,18

10 10 10 ns 1,19
6 10 15 ns 16

5 5 5 ns

3 5 10 ns

2 5 10 ns

0 0 0 ns

6 10 10 ns 21

4 5 5 ns

3 7 3 10 3 15 ns

-45

-50 -60 AC CHARACTERISTICS
UNIT Notes

20

8

TM Technology Inc. reserves the right P. 5 Publication Date:APR. 2002
to change products or specifications without notice. Revision:E

TE

tm

Notes:

1. Enables on-chip refresh and address counters.

2. VIH(2.4V) and VIL(0.8V) are reference levels
for measuring timing of input signals.
Transition times are measured between V

(2.4V)

3. In addition to meet the transition rate
specification, all input signals must transit
between VIH and VIL in a monotonic manner.

4. Assume that t
greater than the maximum recommended value
shown in this table, t
amount that t

5. Assume that t

6. If
data-out will be maintained from the previous
cycle. To initiate a new cycle and clear the

data-out buffer,
pulsed high.

7. Operation within the t
that t
specified as a reference point only; if t
greater than the specified t
access time is controlled by t

8. Operation within the t
t

RAC

specified as a reference point only; if t
greater than the specified t
access time is controlled by tAA.

9. Either t
READ cycle.

10. t

OFF1

output achieves the open circuit condition; it is
not a reference to VOH or VOL.

11. t

WCS

restrictive operating parameters in LATE
WRITE and READ-MODIFY-WRITE cycles
only. If t
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. If t
t

AWD
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state

of I/O (at access time and until

RAS
OE

goes low result in a LATE WRITE(
controlled) cycle.

CH

T2316162A

and V

IL (0.8V)

RCD

RCD

RCD

is low at the falling edge of

CAS

(max) can be met. t

RAC

(max) can be met. t

or t

RCH

(max) defines the time at which the

, t

(min) and t

or OE go back to VIH) is indeterminate.

held high and WE taken low after

RWD

WCS

RWD

, t

≥

.

< t

RAC

exceeds the value shown.

t

≥

CAS

RRH

AWD

t

WCS

≥

CWD

(max). If t

RCD

will increase by the

(max) .

RCD

and

RAS

(max) limit ensures

RCD

RCD

CAC

limit ensures that

RAD

RAD

RAD

must be satisfied for a

and t

(min), the cycle is an

t

RWD

≥

(min), t

t

CWD

RCD

must be

(max) is

RCD

RCD

(max) limit,

.

(max) is

RAD

(max) limit,

CWD

AWD

(min), the

CAS

IH

is

,

RAS

is

is

are

≥

and

CAS

-

OE

12. These parameters are referenced to
leading edge in EARLY WRITE cycles and

leading edge in LATE WRITE or READ-

WE

MODIFY-WRITE cycles.

13. During a READ cycle, if
HIGH before
if

WRITE or READ-MODIFY-WRITE operation
is not possible.

14. An initial pause of 100ms is required after
power-up followed by eight
cycles (
device operation is assured. The eight

cycle wake-ups should be repeated any time
the t

15. WRITE command is defined as

16. LATE WRITE and READ-MODIFY-WRITE
cycles must have both t

(
ensure that the output buffers will be open
during the WRITE cycles.

17. The I/Os open during READ cycles once
t

OFF1

18. The first

19. The last

20. Output parameter (I/O) is referenced to
corresponding
and IO9~16 by

21. Last falling

22. Last rising

CAS

23. Last rising

24. First IOs controlled by the first

25. Last IOs controlled by the last

26. Each

27. Last

28. All IOs controlled, regardless

CASH

29. Data outputs are measured with a load of 50pF.
The output reference levels are VOH/VOL
=2.0V/0.8V; The input levels are VIH/VIL=

3.0V/0V.

is tied permanently low, a LATE

OE

RAS

refresh requirement is exceeded.

REF

high during WRITE cycle) in order to

OE

or t

OFF2

CAS

CAS

CAS

CAS

edge.

CAS

must meet minimum pulse width.

CAS

to go low.

CAS

.

goes high, I/O goes open,

CAS

only or CBR) before proper

occur.

edge to transition low.

edge to transition high.

input, IO1~8 by

CAS

CASH

edge to first rising

edge to next cycle's last rising

edge to first falling

is low then taken

OE

WE

and t

OFF2

.

CAS

CAS

refresh

RAS

going low.

OEH

CASL

CAS

CAS

to go low.

to go high.

CASL

CAS

RAS

met

edge.

edge.

and

TM Technology Inc. reserves the right P. 6 Publication Date:APR. 2002
to change products or specifications without notice. Revision:E

tm

V

RAS

CAS

ADDR

ADDR

WE

I/O

OE

RAS

CAS

WE

V

V

V

V
V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

IH
IL

IH
IL

IH

IL

IH
IL

IO H
IO L

IH
IL

IH

TE

CH

T2316162A

READ CYCLE

t

RC

t

RAS

t

t

CRP

t

ASR

t

RAD

t

RAH

t

RCD

t

AR

t

ASC

COLUMNROW ROW

t

RCS

EARLY WRITE CYCLE

IH
IL

t

CRP

IH
IL

IL

IH
IL

t

ASR

t

RAH

t

RAD

t

RCD

t

AR

t

ASC

COLUM NROW ROW

t

WCS

t

DS

t

t

RAL

t

CAH

t

t

RAC

t

CAC

t

CLZ

t

RC

t

RAS

CSH
RSH

t

CAS

AA

t

RAL

t

CAH

t

OAC

t

CSH

t

RSH

t

CAS

t

CW L

t

RW L

t

WCR

t

WCH

t

WP

t

DHR
t

DH

VAILD DATA

t

OFF2

t

RRH

t

RCH

NOTE1

t

OFF1

t

t

CRP

RP

OPENOPEN

t

RP

V

I/O

OE

IO H

V

IO L

V

IH

V

IL

VALID DATA

DON'T CARE

UNDEFINED

Note: 1. t

is referenced from the rising edge of RAS or CAS , whichever occurs last.

OFF1

TM Technology Inc. reserves the right P. 7 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

tm

V

RAS

V

WE

I/O

OE

V
V

V
V

V
V

V

V

V
V

CAS

ADDR

IH
IL

IH
IL

IH
IL

IH
IL

IO H

IO L

IH
IL

TE

CH

T2316162A

READ WRITE CYCLE

t

DS

VAILD D

t
t

CWL
RWL

t

WP

t

DH

IN

t

OEH

(LATE WRITE and READ-MODIFY-WRITE CYCLES)

t

RWC

t

RAS

t

CSH

t

RSH

t

CRP

t

ASR

t

AR

t

RAD

t

RAH

t

t

RCS

ASC

t

RCD

t

CAS

t

RAL

t

CAH

t

RWD

t

CWD

t

AWD

t

AA

t

RAC

t

CAC

t

CLZ

VAILD D

OUT

t

OAC

t

OFF2

t

CRP

t

RP

ROWCOLUMNROW

RAS

CAS

ADDR

WE

I/O

OE

Note: 1. t

2. t

EDO-PAGE-MODE READ CYCLE

t

RASC

V

IH

V

IL

t

CRP

V

IH

V

IL

t

t

ASRtRAHtASC

V

IH

V

IL

V

IH

V

IL

V

IO H

V

IO L

V

IH

V

IL

OFF1

can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of

PC

ROW COLUMN COLUMN COLUMN ROW

is referenced from the rising edge of

RAD

OPEN OPEN

CAS to rising edge of RAS . Both measurements must meet the t

t

t

t

RCS

RCD

AR

t

CSH

t

CAH

t

t

AA

t

RAC

t

CAC

CLZ

t

CAS

t

OAC

t

OES

VAILD

DATA

RAS

t

CP

t

ASCtCAH

t

COH

or

CAS

t

PC

t

AA

t

ACP

t

CAC

t

CAS

VAILD

DATA

t

OFF2

t

OEP

t

CP

t

ASC

t

OEHC

t

CLZ

, whichever occurs last.

PC

t

RSH

t

CAS

t

RAL

t

CAH

t

AA

t

ACP

t

CAC

VAILD

t

OES

DATA

t

OAC

specification.

t

t

RP

t

CRP

t

CPN

t

RRH

RCH

NOTE1

t

OFF1

t

OFF2

DON 'T CA RE

UNDEFINED

TM Technology Inc. reserves the right P. 8 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

tm

CASL,CASH

CASL ,CASH

TE

CH

T2316162A

EDO-PAGE-MODE EARLY-WRITE CYCLE

RAS

ADDR

WE

I/O

OE

t

RASC

V

IH

V

IL

t

CRP

V

IH

V

IL

t

ASRtRAH

V

IH

V

IL

V

IH

V

IL

V

IO H

V

IO L

V

IH

V

IL

t

CSH

t

RAD

t

RCD

t

AR

t

ASCtCAH

COLUM N COLUM N COLUMN ROWROW

t

WCS

t

DS

VA L ID DAT A

t

CAS,tCLCH

t

CW L

t

WCH

t

WP

t

WCR

t

DHR

t

DH

t

PC

t

t

CP

CAS,tCLCH

t

ASCtCAH

t

t

WCS

t

VALID DATA VALID DAT A

CW L

t

WCH

t

WP

DStDH

t

CP

t

ASCtCAH

t

WCS

t

DStDH

t

RSH

t

CAS,tCLCH

t

RAL

t

CW L

t

WCH

t

WP

t

RW L

t

RP

t

CPN

EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE CYCLES)

VALID
D

IN

t

OFF2
t

OEH

t

t

t

DH

t

RP

t

t

RW L

CW L

WP

OPENOPEN

CPN

RAS

ADDR

WE

I/O

OE

t

RASC

V

IH

V

IL

t

CRP

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IO H

V

IO L

V

IH

V

IL

t

AR

t

RAD

t

ASRtRAH

t

RAC

t

CSH

t

RCD

t

ASCtCAH

COLUMN ROWROW

t

RCS

t

AA

t

CAC

t

CLZ

t

OAC

t

CAS, tCL C H

t

RW D

t

CW L

t

WP

t

AW D

t

CW D

t

DH

t

DS

VALID

VALID

D

D

IN

OUT

t

OFF2

t
t

t

PCM

tCPt

CAS, tCL C H

t

ASCtCAH

COLUM N

t

AW D

t

CW D

t

AA

t

ACP

CAC
CLZ

t

OAC

t

CW L

t

WP

t

DH

t

DS

VALID
D

OUT

VALID
D

IN

t

OFF2

t

CP

t

ASCtCAH

COLUM N

t

AA

t

ACP

t

CAC

t

CLZ

t

OAC

t

RSH

t

CAS, tCL C H

t

RAL

t

AW D

t

CW D

t

DS

VALID
D

OUT

DON'T CARE

Note: 1. t

UNDEFINE D

can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of

PC

CAS. Both measurements must meet the tPC specification.

TM Technology Inc. reserves the right P. 9 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

tm

V

IH

RAS

V

IL

V

IH

CAS

V

IL

V

IH

ADDR

V

IL

V

IH

WE

V

IL

V

IO H

I/O

V

IO L

V

IH

OE

V

IL

TE

CH

T2316162A

EDO-PAGE-MODE READ-EARLY-WRITE CYCLE

(Psuedo READ-MODIFY-WRITE)

t

RASC

t

t

CRP

t

ASRtRAH

t

RAD

CSH

t

RCD

t

AR

t

ASC

COLUMN (A) COLUMN(B) COLUMN(N)

t

RCS

t

RAC

OPEN

t

AA

t

CAH

t

t

t

PC

t

CAS

CAC

OAC

t

CP

t

ASCtCAH

t

AA

t

ACP

t

CAC

t

COH

VALID D ATA (A)

t

CAS

t

RCH

t

PC

t

CP

t

WHZ

VALID

DATA (B)

t

ASCtCAH

t

WCS

tDSt

VALID DATA

IN

t

WCH

DH

t
t

t

RAL

RSH
CAS

t

t

RP

CP

ROWROW

CASL,CASH

RAS

ADDR

I/O

V
V

V
V

V
V

V
V

IH
IL

IH
IL

IH
IL

OH
OL

ONLY REFRESH CYCLE

RAS

(ADDR=A0-A8 ;

t

CRP

t

ASR

t

RAH

OE,WE

t

RAS

=DON‘T CARE)

t

RC

t

RPC

OPEN

t

RP

ROWROW

DON'T CARE

UNDEFINED

TM Technology Inc. reserves the right P. 10 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

tm

TE

CH

T2316162A

CBR REFRESH CYCLE

(A0-A8 ;

=DON‘T CARE)

OE

CASH,CASL

CASL,CASH

RAS

I/O

WE

RAS

ADDR

I/O

OE

V
V

V
V

V
V

V
V

V
V

V
V

V
V

V
V

IH

IL

IH

IL

IH

IL

OH
OL

IH

IL

t

CHR

t

RAS

t

RP

IH
IL

IH
IL

IH
IL

t

RPC

t

CPN

t

CSR

t

RP

t

RPCtCSR

OPEN

t

CHR

t

RAS

HIDDEN REFRESH CYCLE

t

CRP

t

ASRtRAH

ROW

=HIGH ;

(

WE

(READ)

t

RAS

t

RAL

COLUMN

t

AA

t

RS H

t

CLZ

t

RCD

t

AR

t

RAD

OPEN VA LID DATA

t

ASCtCAH

t

RAC

t

CAC

OE

t

OAC

t

ORD

=LOW)

t

RP

(R EFRESH)

t

RAS

t

CHR

t

OFF2

NOTE1

t

OFF1

OPEN

DON'T CAR E

UNDEFINED

Note: 1. t

is referenced from the rising edge of RAS or CAS , whichever occurs last.

OFF1

TM Technology Inc. reserves the right P. 11 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

TE

tm

PACKAGE DIMENSIONS
42-LEAD SOJ DRAM (400 mil)

CH

T2316162A

SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM

A 0.128~0.148 3.251~3.759
A1 0.025(MIN) 0.635(MIN)
A2 0.105~0.115 2.657~2.920

B 0.026~0.032 0.660~0.813

b 0.015~0.020 0.381~0.508
c 0.007~0.013 0.178~0.330

D 1.070~1.080 27.178~27.432

E 0.395~0.405 10.033~10.287

e 0.050 1.270

E1 0.435~0.445 11.049~11.303

L 0.082(MIN) 2.083(MIN)

y 0.004(MAX) 0.102(MAX)

TM Technology Inc. reserves the right P. 12 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

TE

tm

PACKAGE DIMENSIONS
44/50L LEAD TSOPII DRAM (400 mil)

CH

T2316162A

"

"

SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM

A 0.047 1.200(MAX)
A1 0.002~0.006 0.050~0.150
A2 0.037~0.041 0.950~1.050

b 0.012~0.018 0.300~0.450
c 0.005~0.008 0.120~0.210

D 0.820~0.830 20.820~21.080

E 0.455~0.471 11.560~11.960

e 0.031 0.800

E1 0.395~0.405 10.030~10.290

L 0.016~0.024 0.400~0.600

L1 0.031 0.800

θ

TM Technology Inc. reserves the right P. 13 Publication Date: APR. 2002
to change products or specifications without notice. Revision:E

0°~5° 0°~5°