Page 1
tm
TE
CH
T2316160A
DRAM
FEATURES
Industry-standard x 16 pinouts and timing
•
functions.
Single 5V (±10%) power supply.
•
All device pins are TTL- compatible.
•
1K-cycle refresh in 16ms.
•
Refresh modes:
•
RAS
(CBR) and HIDDEN.
BYTE WRITE and BYTE READ access cycles.
•
RAS
only,
CAS
BEFORE
OPTION
TIMING MARKING
45ns -45
60ns -60
PACKAGE
42-pin SOJ J
44/50-pin TSOPII S
1024K x 16 DYNAMIC RAM
FAST PAGE MODE
GENERAL DESCRIPTION
The T2316160A is a randomly accessed solid state
memory containing 16,777,216 bits organized in a
x16 configuration. The T2316160A has both
BYTE WRITE and WORD WRITE access cycles
CAS
via two
Extended Data Output.
The T2316160A
determined by the first
by the last to transition back high. Use only one of
the two
during WRITE will result in a BYTE WRITE.
CASL
write data into the lower byte (DQ0~DQ7), and
CASH
pins. It offers Fast Page mode with
CAS
function and timing are
CAS
to transition low and
CAS
and leave the other staying high
to transition low in a WRITE cycle will
transiting low will write data into the
PIN ASSIGNMENT ( Top View )
V
DQ0
DQ1
DQ2
DQ3
V
DQ4
DQ5
DQ6
DQ7
NC
NC
WE
RAS
NC
NC
V
DD
1
2
3
4
5
DD
6
7
8
9
10
11
12
13
14
15
16
A0
17
A1
18
A2
19
A3
20
DD
21
Vss
42
DQ15
41
DQ14
40
DQ13
39
DQ12
38
Vss
37
DQ11
36
DQ10
35
DQ9
34
DQ8
33
NC
32
CASL
31
CASH
30
OE
29
A9
28
A8
27
A7
26
A6
25
A5
24
A4
23
Vss
22
upper byte (DQ8~DQ15).
V
DD
1
DQ0
2
DQ1
3
DQ2
4
DQ3
5
DD
V
6
DQ4
7
DQ5
8
DQ6
9
DQ7
10
NC
11
NC
15
NC
16
WE
17
RAS
18
NC
19
NC
20
A0
21
A1
22
A2
23
A3
24
V
DD
25
Vss
50
DQ15
49
DQ14
48
DQ13
47
DQ12
46
Vss
45
DQ11
44
DQ10
43
DQ9
42
DQ8
41
NC
40
NC
36
CASL
35
CASH
34
OE
33
A9
32
A8
31
A7
30
A6
29
A5
28
A4
27
Vss
26
Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: APR. 2002
to change products or specifications without notice. Revision:A
Page 2
TE
tm
FUNCTIONAL BLOCK DIAGRAM
CH
T2316160A
WE
RAS
CASL
CASH
NO.2 CLOCK
GENERATOR
COLUMN.
ADDRESS
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CONTROLLER
10
REFRESH
REFRESH
COUNTER
ADDRESS
BUFFERS(10)
NO.1 CLOCK
GENERATOR
CAS
BUFFER
10
ROW.
CONTROL
LOGIC
10
ROW
DECODER
10
1024
DATA-IN BUFFER
COLUMN
DECODER
1024
SENSE AMPLIFIERS
I/O GATING
1024x 16
1024x 1024 x 16
MEMORY
ARRAY
DQ0
16
DATA-OUT
BUFFER
16
16
.
.
DQ15
OE
Vcc
Vss
PIN DESCRIPTIONS
SYM. TYPE DESCRIPTION
A0-A9 Input Address Input
RAS
CASH
CASL
WE
OE
DQ0 – DQ15 Input/ Output Data Input/ Output
Vcc Supply Power, 5V
Vss Ground Ground
NC - No Connect
Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: APR. 2002
to change products or specifications without notice. Revision:A
Input Row Address Strobe
Input Column Address Strobe /Upper Byte Control
Input Column Address Strobe /Lower Byte Control
Input Write Enable
Input Output Enable
Page 3
TE
tm
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS…... -1V to +7V
Operating Temperature, Ta (ambient).. 0°C to +70°C
Storage Temperature (plastic)...….. -55°C to +150°C
Power Dissipation .......................…….............. 1.2W
Short Circuit Output Current.............…........... 50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)
DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES
Supply Voltage Vcc 4.5 5.5 V 1
Supply Voltage Vss 0 0 V
Input High (Logic) voltage VIH 2.4 Vcc+1 V 1
Input Low (Logic) voltage VIL -1.0 0.8 V 1
Input Leakage Current
Output Leakage Current
Output High Voltage IOH = -5 mA VOH 2.4 Vcc V
Output Low Voltage IOL = 4.2 mA VOL 0 0.4 V
CH
T2316160A
*Stresses greater than those listed under "Absolute
Maxi mum Rat ings" ma y caus e per manent damag e
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
reliability.
0V ≤ VIN ≤ 7V
0V ≤ V
Output(s) disabled
OUT
≤ 7V
ILI -10 10 uA
ILO -10 10 uA
Note: 1.All Voltages referenced to Vss
DESCRIPTION CONDITIONS SYM. -45 -60 UNITS NOTES
Operating Current
TTL Standby Current
RAS-only refresh Current
Fast Page Mode Current tPC = min I
CAS Before RAS Refresh
Current
CMOS Standby Current
1. Icc depends on output load condition when the device is selected.
Note:
Icc max is specified at the output open condition.
2. Address can be changed twice or less while
3. Address can be changed once or less while
RAS,CAS cycling , tRC = min
TTL interface,
CAS=VIH, D
t
RC = min I
t
RC = min Icc5 190 170 mA
CMOS interface,
0.2V
RAS,
=High-Z
OUT
RAS,CAS>Vcc-
RAS
CAS
= VIL.
= VIH.
Icc1 190 170 mA 1,2
I
2.0 2.0 mA
cc2
190 170 mA 2
cc3
150 130 mA 1,3
cc4
I
1.0 1.0 mA 1
cc6
MAX
Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: APR. 2002
to change products or specifications without notice. Revision:A
Page 4
TE
tm
CAPACITANCE
CH
T2316160A
(Ta =25°C, Vcc =5V, f = 1M HZ)
Parameter Symbol Typ Max Unit
Input Capacitance (address) CI1 - 5 pF
Input Capacitance (
Output Capacitance (data-in/out) C
RAS,CAS,WE,OE
) CI2 - 7 pF
- 10 pF
I/O
AC CHARACTERISTICS
(note 1,2,3) (Ta = 0 to 70°C)
TEST CONDITIONS:
Vcc=5V ±10%, VIH/VIL=2.4/0.8V,VOH/VOL=2.0/0.8V
Input rise and fall times: 2ns
Output Load: 2TTL gate + CL (100pF)
AC CHARACTERISTICS -45 -60
PARAMETER SYM MIN MAX MIN MAX UNIT Notes
Read or Write Cycle Time t
Read Write Cycle Time t
Fast-Page-Mode Read or Write Cycle Time t
Fast-Page-Mode Read-Write Cycle Time t
RAS
CAS
OE
CAS
Precharge
Access Time From
Access Time From
Access Time From
Access Time From Column Address tAA 19 30 ns 8
Access Time From
RAS
Pulse Width
RAS
Pulse Width (Fast Page Mode)
RAS
Hold Time
RAS
Precharge Time
CAS
Pulse Width
CAS
Hold Time
CAS
Precharge Time
RAS
CAS
Row Address Setup Time t
Row Address Hold Time t
RAS
Column Address Setup Time t
CAS
to
to
to Column Address Delay Time
Delay Time
RAS
Precharge Time
RC
RWC
PC
PCM
t
RAC
t
CAC
t
OAC
t
ACP
t
RAS
t
RASC
t
RSH
tRP 28 40 ns
t
CAS
t
CSH
tCP 6 10 ns
t
RCD
t
CRP
ASR
RAH
t
RAD
ASC
85 110 ns
105 140 ns
26 35 ns
70 85 ns
45 60 ns 4
11 15 ns 5
11 15 ns 13
22 35 ns
45 10K 60 10K ns
45 100K 60 100K ns
11 15 ns
10 10K 15 10K ns
40 60 ns
10 34 20 45 ns 7
5 5 ns
0 0 ns
5 10 ns
8 26 12 30 ns 8
0 0
Taiwan Memory Technology, Inc. reserves the right P. 4
to change products or specifications without notice. Revision:A
Publication Date: APR. 2002
Page 5
TE
tm
AC CHARACTERISTICS
AC CHARACTERISTICS -45 -60
PARAMETER SYM MIN MAX MIN MAX UNIT Notes
Column Address Hold Time t
Column Address Hold Time (Reference to
Column Address to
Read Command Setup Time t
Read Command Hold Time Reference to
Read Command Hold Time Reference to
CAS
to Output in Low-Z
Output Buffer Turn-off Delay From
Output Buffer Turn-off OE to
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time (Reference to
Write Command Pulse Width tWP 7 15 ns 14
Write Command to
Write Command to
Data-in Setup Time tDS 0 0 ns 12
CH
T2316160A
RAS
RAS
CAS
Lead Time
Lead Time
Lead Time
(continued)
CAS
RAS
CAS
or
RAS
RAS
RAS
6 10 ns
CAH
tAR 35 45 ns
)
t
RAL
RCS
t
RCH
t
RRH
t
CLZ
t
OFF1
t
OFF2
t
WCS
t
WCH
t
)
WCR
t
RWL
t
CWL
19 30 ns
0 0 ns 14
0 0 ns 9,14
0 0 ns 9
3 3 ns
3 15 3 15 ns 10,16
8 15 ns 16
0 0 ns 11,14
6 10 ns
35 45 ns 14
9 10 ns 14
8 10 ns 14
Data-in Hold Time tDH 6 10 ns 12
t
RAS
Data-in Hold Time (Reference to
RAS
Column Address to
CAS
Transition Time (rise or fall) tT 2.5 50 2.5 50 ns 2,3
Refresh Period (1024 cycles) t
RAS
CAS
CAS
OE
OE
WE
to
to
to
Setup Time (CBR REFRESH)
Hold Time (CBR REFRESH)
Hold Time From
Setup Prior t o
Delay Time
WE
Delay Time
CAS
Precharge Time
WE
RAS
WE
Delay Time
During Read-Modify-Write Cycle
During Hidden Refr esh Cycle
)
35 45 ns
DHR
t
RWD
t
AWD
t
CWD
REF
t
RPC
t
CSR
t
CHR
t
OEH
t
ORD
61 85 ns 11
35 55 ns 11
27 40 ns 11
16 16 ms
10 10 ns
10 10 ns 6
10 10 ns 6
6 15 ns 15
0 0 ns
Taiwan Memory Technology, Inc. reserves the right P. 5
to change products or specifications without notice. Revision:A
Publication Date: APR. 2002
Page 6
TE
tm
Notes:
1. An initial pause of 200us is required after
power-up followed by eight
cycles (
device operation is assured. The eight
cycle wake-ups should be repeated any time
the t
2. VIH(2.4V) and VIL(0.8V) are reference levels
for measuring timing of input signals.
Transition times are measured between
V
IH(2.4V)
3. In addition to meet the transition rate
specification, all input signals must transit
between VIH and VIL in a monotonic manner.
4. Assume that t
greater than the maximum recommended value
shown in this table, t
amount that t
5. Assume that t
6. Enables on-chip refresh and address counters.
7. Operation within the t
that t
specified as a reference point only; if t
greater than the specified t
access time is controlled by t
8. Operation within the t
t
RAC
specified as a reference point only; if t
greater than the specified t
access time is controlled by tAA.
9. Either t
READ cycle.
10. t
OFF1
output achieves the open circuit condition; it is
not a reference to V
CH
T2316160A
RAS
refresh
RAS
only or CBR) before proper
RAS
refresh requirement is exceeded.
REF
and V
IL(0.8V)
< t
RCD
exceeds the value shown.
RCD
≥
RCD
(max) can be met. t
RAC
(max) can be met. t
or t
RCH
(max) defines the time at which the
RRH
.
(max). If t
RCD
will increase by the
RAC
t
(max) .
RCD
(max) limit ensures
RCD
RCD
CAC
limit ensures that
RAD
RAD
RAD
must be satisfied for a
or VOL.
OH
RCD
(max) is
RCD
RCD
(max) limit,
.
(max) is
RAD
(max) limit,
is
is
is
11. t
12. These parameters are referenced to
13. During a READ cycle, if
14. WRITE command is defined as
15. LATE WRITE and READ-MODIFY-WRITE
16. The I/Os open during READ cycles once
, t
WCS
restrictive operating parameters in LATE
WRITE and READ-MODIFY-WRITE cycles
only. If t
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. If t
t
(min) and t
AWD
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of I/O (at access time and until
RAS
or OE go back to VIH) is indeterminate.
OE
held high and
goes low result in a LATE WRITE (
controlled) cycle.
leading edge in EARLY WRITE cycles and
WE
leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
taken HIGH before
open, if
WRITE or READ-MODIFY-WRITE
operation is not possible.
low.
cycles must have both t
OE
(
ensure that the output buffers will be open
during the WRITE cycles.
t
OFF1
OE
high during WRITE cycle) in order to
or t
, t
RWD
t
≥
WCS
RWD
is tied permanently low, a LATE
occur.
OFF2
and t
AWD
(min), the cycle is an
WCS
t
≥
CWD
WE
CAS
(min), t
RWD
t
≥
CWD
taken low after
OE
is low then
goes high, I/O goes
and t
OFF2
CWD
AWD
(min), the
CAS
WE
OEH
are
≥
and
CAS
OE
-
CAS
going
met
Taiwan Memory Technology, Inc. reserves the right P. 6
to change products or specifications without notice. Revision:A
Publication Date: APR. 2002
Page 7
tm
17
RAS
CAS
ADDR
WE
I/O
OE
TE
CH
T2316160A
READ CYCLE
t
V
V
V
V
V
V
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
OH
OL
IH
IL
t
CRP
t
ASR
RC
t
RAS
t
RCD
t
t
RAD
t
RAH
AR
t
ASC
t
RCS
COLUMN ROWROW
EARLY WRITE CYCLE
t
CSH
t
RSH
t
CAS
t
RAL
t
CAH
t
AA
t
RAC
t
CAC
t
CLZ
t
OAC
t
RP
t
RRH
t
RCH
NO TE1
t
OFF1
VALID DATA
t
OFF2
OPENOPEN
Note: t
V
IH
RAS
V
IL
t
CRP
V
IH
CAS
V
IL
t
t
ASRtRAH
V
WE
I/O
OE
V
V
V
V
V
V
V
IH
IL
IH
IL
IO H
IO L
IH
IL
ADDR
is referenced from the rising edge of
OFF1
RAD
t
RC
t
RAS
t
RCD
t
AR
t
ASC
COLUMN ROWROW
t
WCS
t
DS
VALID DATA
RAS
or
t
RP
t
CSH
t
RSH
t
CAS
t
RAL
t
CAH
t
CW L
t
RW L
t
WCR
t
WCH
t
WP
t
DHR
t
DH
, whichever occurs last.
CAS
DON'T CARE
UNDEFINED
Taiwan Memory Technology, Inc. reserves the right P.
7
Publication Date:APR. 2002
to change products or specifications without notice. Revision:A
Page 8
tm
28
RAS
CAS
ADDR
WE
I/O
OE
RAS
CAS
ADDR
WE
I/O
OE
TE
CH
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IO H
V
IO L
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
T2316160A
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
t
RW C
t
RAS
t
CSH
t
RSH
t
RAL
t
CAH
t
AA
t
RAC
t
CAC
t
t
CAS
t
RW D
t
CW D
t
AW D
OAC
VALID D
t
OUT
OFF2
t
DS
VALID D
t
CW L
t
RW L
t
WP
t
DH
IN
t
OEH
t
CRP
t
ASRtRAH
t
AR
t
RAD
OPEN
t
t
ASC
t
RCS
RCD
COLUMN ROWROW
t
CLZ
FAST-PAGE-MODE READ CYCLE
t
RASC
t
CRP
t
ASRtRAH
t
CSH
t
RCD
t
t
RAD
AR
t
ASC
t
RCS
OPEN OPE N
t
CLZ
t
CAS
t
CAH
COLUMN ROWROW
t
AA
t
RAC
t
CAC
t
OAC
t
OFF1
VALID
DATA
t
OFF 2
t
PC
t
CP
t
ASCtCAH
COLUMN
t
CLZ
t
t
AA
ACP
t
CAC
t
OAC
t
CAS
t
OFF1
VALID
DATA
t
OFF2
t
CP
t
ASCtCAH
COLUMN
t
AA
t
ACP
t
CAC
t
CLZ
t
OAC
t
RSH
t
CAS
OPEN
t
RAL
VALID
DATA
t
t
OFF2
RP
t
RCH
t
OFF1
t
t
CPN
RP
t
RRH
DON'T CARE
Note: 1. t
2. t
is referenced from the rising edge of RAS or CAS , whichever occurs last.
OFF1
can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of
PC
CAS to rising edge of CAS . Both measurements must meet the t
Taiwan Memory Technology, Inc. reserves the right P.
specification.
PC
8
Publication Date:APR. 2002
UNDEFINED
to change products or specifications without notice. Revision:A
Page 9
tm
TE
CH
RAS
CAS
ADDR
WE
I/O
OE
RAS
CAS
ADDR
WE
I/O
OE
T2316160A
FAST-PAGE-MODE EARLY-WRITE CYCLE
t
RASC
V
IH
V
IL
t
CRP
V
IH
V
IL
t
ASRtRAH
V
IH
V
IL
V
IH
V
IL
V
IO H
V
IO L
V
IH
V
IL
t
t
RAD
CSH
t
RCD
t
AR
t
ASCtCAH
t
WCS
t
DS
VALID DA TA
t
t
CAS
COLUMN COLUMN COLUMN ROWROW
t
CW L
t
WCH
t
WP
t
WCR
t
DHR
t
DH
PC
t
CP
t
ASCtCAH
t
WCS
t
DStDH
VALID D ATA
t
CAS
t
CW L
t
WCH
t
WP
t
CP
t
t
t
VALID DATA
t
RSH
t
CAS
t
RAL
ASCtCAH
t
CW L
t
WCS
WCH
t
WP
t
DStDH
RW L
t
CPN
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
VALID
D
IN
t
OFF2
t
OEH
t
CW L
t
WP
t
DH
t
RP
t
CPN
t
RW L
OPENOPEN
t
RASC
V
IH
V
IL
t
CRP
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IO H
V
IO L
V
IH
V
IL
t
AR
t
RAD
t
ASRtRAH
t
RAC
t
t
RCD
t
ASCtCAH
COLUMN ROWROW
t
RCS
t
AA
t
CAC
t
CLZ
t
OAC
CSH
t
RW D
t
AW D
t
CW D
t
CAS
t
CW L
t
WP
t
DH
t
DS
VALID
D
OUT
VALID
D
IN
t
OFF2
tCPt
t
ASCtCAH
COLUMN
t
AA
t
ACP
t
CAC
t
CLZ
t
OAC
t
PCM
CAS
t
AW D
t
CW D
t
CW L
t
WP
t
DH
t
DS
VALID
D
OUT
VALID
D
IN
t
OFF2
t
CP
t
ASCtCAH
COLUMN
t
AA
t
ACP
t
CAC
t
CLZ
t
OAC
t
AW D
t
CW D
t
t
DS
VALID
D
OUT
t
RSH
t
CAS
RAL
DON'T CARE
Note:
can be measured from falling edge to falling edge of
t
PC
CAS
. Both measurements must meet the t
specification.
PC
UNDEF INED
CAS
, or from rising edge to rising edge of
Taiwan Memory Technology, Inc. reserves the right P. 9 Publication Date: APR. 2002
to change products or specifications without notice. Revision:A
Page 10
tm
V
IH
RAS
V
IL
V
IH
CAS
V
IL
V
IH
ADDR
V
IL
V
IH
WE
V
IL
V
IOH
I/O
V
IOL
V
IH
OE
V
IL
TE
CH
T2316160A
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t
RASC
t
t
CRP
t
ASRtRAH
t
RAD
CSH
t
RCD
t
AR
t
ASC
COLUMN(A) COLUMN(B) COLUMN(N)
t
RCS
t
RAC
OPEN
t
PC
t
CAS
t
CAH
t
AA
t
CAC
t
OAC
t
OFF1
VALID
DATA (A)
t
CP
t
ASCtCAH
t
ACP
t
CLZ
t
AA
t
CAC
t
CAS
t
RCH
t
PC
t
OFF1
VALID
DATA ( B)
t
CP
t
WCS
NOTE1
t
ASCtCAH
tDSt
VALID
DATA IN
t
WCH
DH
t
RSH
t
CAS
t
RAL
t
RP
t
CP
ROWROW
RAS
(ADDR=A0-A9;
V
IH
RAS
V
IL
V
IH
CAS
V
IL
V
IH
ADDR
V
IL
V
OH
I/O
V
OL
Note1:Do not drive data prior to tristate.
t
CRP
t
ASR
t
RAH
ONLY REFRESH CYCLE
OE,WE
=DON‘T CARE)
t
t
RAS
RC
OPEN
t
RPC
t
RP
ROWROW
DON'T CARE
UNDEFINED
Taiwan Memory Technology, Inc. reserves the right P. 10 Publication Date: APR. 2002
to change products or specifications without notice. Revision:A
Page 11
tm
TE
CH
T2316160A
CBR REFRESH CYCLE
(A0-A9;
=DON‘T CARE)
OE
RAS
CASH,CASL
Note: 1. t
t
RP
V
IH
V
I/O
WE
IL
V
IH
V
IL
V
IH
V
IL
t
RPC
t
CPN
t
CSR
HIDDEN REFRESH CYCLE
V
IH
RAS
V
IL
V
IH
CAS
V
IL
V
IH
ADDR
V
IL
V
OH
I/O
V
OL
V
IH
OE
V
IL
is referenced from the rising edge of
OFF1
t
CRP
t
ASRtRAH
ROW
t
RAD
OPEN VALID DATA
t
CHR
t
t
AR
(
RCD
WE
(R E A D )
t
t
RAS
=HIGH;
RAS
t
ASCtCAH
COLUMN
t
t
RAC
t
RAL
AA
t
RSH
t
t
CLZ
RAS
t
RPCtCSR
OE
CAC
t
OAC
t
ORD
or
t
RP
t
CHR
OPEN
=LOW)
(REFRESH)
t
RP
, whichever occurs last.
CAS
t
RAS
t
CHR
t
RAS
t
OFF2
NO TE1
t
OFF1
OPEN
Taiwan Memory Technology, Inc. reserves the right P. 11
Publication Date: APR. 2002
to change products or specifications without notice. Revision:A
Page 12
TE
tm
PACKAGE DIMENSIONS
42-LEAD SOJ DRAM (400 mil)
CH
T2316160A
SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM
A 0.128~0.148 3.251~3.759
A1 0.025(MIN) 0.635(MIN)
A2 0.105~0.115 2.657~2.920
B 0.026~0.032 0.660~0.813
b 0.015~0.020 0.381~0.508
c 0.007~0.013 0.178~0.330
D 1.070~1.080 27.178~27.432
E 0.395~0.405 10.033~10.287
e 0.050 1.270
E1 0.435~0.445 11.049~11.303
L 0.082(MIN) 2.083(MIN)
y 0.004(MAX) 0.102(MAX)
Taiwan Memory Technology, Inc. reserves the right P. 12
to change products or specifications without notice. Revision:A
Publication Date: APR. 2002
Page 13
TE
tm
PACKAGE DIMENSIONS
44/50L LEAD TSOPII DRAM (400 mil)
CH
T2316160A
"
"
SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM
A 0.047 1.200(MAX)
A1 0.002~0.006 0.050~0.150
A2 0.037~0.041 0.950~1.050
b 0.012~0.018 0.300~0.450
c 0.005~0.008 0.120~0.210
D 0.820~0.830 20.820~21.080
E 0.455~0.471 11.560~11.960
e 0.031 0.800
E1 0.395~0.405 10.030~10.290
L 0.016~0.024 0.400~0.600
L1 0.031 0.800
θ
Taiwan Memory Technology, Inc. reserves the right P. 13
to change products or specifications without notice. Revision:A
0°~5° 0°~5°
Publication Date: APR. 2002
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