Page 1
TE
C
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RAS
CAS
CASL
T224162B
DRAM
FEATURES
•
Industry-standard x 16 pinouts and timing
functions.
•
Single 5V (±10%) power supply.
•
All device pins are TTL- compatible.
•
512-cycle refresh in 8ms.
•
Refresh modes:
RAS
only,
CAS
BEFORE
(CBR) and HIDDEN.
•
Extended data-out (EDO) PAGE MODE
access cycle.
•
BYTE WRITE and BYTE READ access
cycles.
OPTION
TIMING EDO MARKING
22ns 125 MHz -22
25ns 100 MHz -25
28ns 100 MHz -28
35ns 83 MHz -35
45ns 60 MHz -45
50ns 50 MHz -50
PACKAGE MARKING
SOJ J
TSOP(II) S
GENERAL DESCRIPTION
The T224162B is a randomly accessed solid state
memory containing 4,194,304 bits organized in a x16
configuration. The T224162B has both BYTE
WRITE and WORD WRITE access cycles via two
CAS
pins. It offers Fast Page mode with Extended
Data Output.
The T224162B
determined by the first
by the last to transition back high. Use only one of
the two
CAS
and leave the other staying high during
WRITE will result in a BYTE WRITE.
transiting low in a WRITE cycle will write data into
the lower byte (IO1~IO8), and
will write data into the upper byte (IO9~16).
function and timing are
CAS
to transition low and
CASH
transiting low
256K x 16 DYNAMIC
EDO PAGE MODE
PIN ASSIGNMENT ( Top View )
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
Vcc
I/01
I/02
I/03
I/04
Vcc
I/05
I/06
I/07
I/08
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
TSOP(II)
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
SOJ
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RAM
Vss
I/016
I/015
I/014
I/013
Vss
I/012
I/011
I/010
I/09
NC
CASL
CASH
OE
A8
A7
A6
A5
A4
VSS
Vss
I/016
I/015
I/014
I/013
Vss
I/012
I/011
I/010
I/09
NC
CASL
CASH
OE
A8
A7
A6
A5
A4
VSS
Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: AUG. 2000
to change products or specifications without notice. Revision:L
Page 2
TE
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CASH
FUNCTIONAL BLOCK DIAGRAM
WE
T224162B
RAS
CASL
CASH
NO.2 CLOCK
GENERATOR
COLUMN.
ADDRESS
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
REFRESH
CONTROLLER
REFRESH
COUNTER
ADDRESS
9
BUFFERS(9)
NO.1 CLOCK
GENERATOR
CAS
BUFFER
9
ROW.
CONTROL
LOGIC
9
ROW
DECODER
9
512
COLUMN
DECODER
DATA-IN BUFFER
512
SENSE AMPLIFIERS
VO GATING
512 x 16
512 x 512 x 16
MEMORY
ARRAY
8
8
DATA-OUT
BUFFER
16
16
OE
Vcc
Vss
DQ01
.
.
DQ16
PIN DESCRIPTIONS
PIN NO. SYM. TYPE DESCRIPTION
16~19,22~26 A0-A8 Input Address Input
14 RAS
28
29 CASL
13 WE
27 OE
2~5,6~10,31~34,36~39 I/O1 - I/O16 Input/ Output Data Input/ Output
1,6,20 Vcc Supply Power, 5V
21,35,40 Vss Ground Ground
11,12,15,30 NC - No Connect
Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date:AUG. 2000
to change products or specifications without notice. Revision:L
Input Row Address Strobe
Input Column Address Strobe /Upper Byte Control
Input Column Address Strobe /Lower Byte Control
Input Write Enable
Input Output Enable
Page 3
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RAS
RAS
CAS
>
CAS
RAS
CAS
T224162B
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS..... -1V to +7V
Operating Temperature, Ta (ambient) ..0°C to +70°C
Storage Temperature (plastic)........ -55°C to +150°C
Power Dissipation ............................…...........
1.0W
Short Circuit Output Current.......…............... 50mA
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other
conditions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED
OPERATING CONDITIONS
(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)
DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES
Supply Voltage
Supply Voltage
Input High (Logic) voltage
Input Low (Logic) voltage
Input Leakage Current 0V ≤ VIN ≤ 7V ILI -10 10 uA
Output Leakage Current
Output High Voltage IOH = -5 mA VOH 2.4 Vcc V
Output Low Voltage IOL = 4.2 mA VOL 0 0.4 V
0V ≤ V
Output(s) disabled
OUT
≤
7V
Vcc 4.5 5.5 V 1
Vss 0 0 V
VIH 2.4 Vcc+1 V 1
VIL -1.0 0.8 V 1
ILO -10 10 uA
Note: 1.All Voltages referenced to Vss
MAX
DESCRIPTION CONDITIONS
Operating Current
Standby Current
RAS
-only refresh
Current
Standby Current
Before
Refresh Current
EDO Page Mode Current tPC = min Icc7 190 180 170 150 130 110 mA 1,3
1. Icc depends on output load condition when the device is selected.
Note:
Icc max is specified at the output open condition.
2. Address can be changed twice or less while
3. Address can be changed once or less while
RAS,CAS
TTL interface,
CAS
CMOS interface,
Vcc-0.2V
t
RC = min I
RAS
t
RC = min Icc6 190 180 170 150 130 110 mA
cycling , tRC = min
=VIH, D
=V
IH,
OUT
CAS
,
=High-Z
,
=VIL
RAS
= VIH.
-22 -25 -28 -35 -45 -50
Icc1 190 180 170 150 130 110 mA
4 4 4 4 4 4 mA
I
cc2
2 2 2 2 2 2 mA
190 180 170 150 130 110 mA
cc3
I
5 5 5 5 5 5 mA
cc5
= VIL.
1,2
2
1
Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: AUG. 2000
to change products or specifications without notice. Revision:L
Page 4
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MAX
MAX
CAS
Access Time From Column
RAS
K
RAS
CAS
TE
RAS
- 10 pF 1
I/O
(note 14)
Output Load: 2TTL gate + CL (50pF)
SYM
tRC 42 45 48 65 85 100
RWC
tPC 8 10 10 12 16 20 ns 22
t
PCM
t
RAC
t
CAC
t
OAC
-22 -25 -28 -35 -45 -50
MIN MAX MIN MAX MIN MAX MIN MAX MIN
62 65 70 95 115 135 ns
30 32 34 40 46 57 ns 22
22 25 28 35 45 50 ns 4
7 7 7 9 11 13 ns 5,20
8 8 8 9 11 13 ns 13,20
CAPACITANCE
(Ta =25°C, Vcc =5V ±10 %)
Parameter Symbol Typ Max Unit Notes
Input Capacitance (address) CI1 - 5 pF 1
Input Capacitance (clocks) CI2 - 7 pF 1
Output Capacitance (data-in, data-out) C
1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
Note:
AC ELECTRICAL CHARACTERISTICS
(Ta =0 to 70°C, Vcc=5V ±10 %, Vss=0V) Input timing reference levels: 0.8V, 2.4V
Test Conditions
AC CHARACTERISTICS
PARAMETER
Read or Write Cycle Time
Read Write Cycle Time t
EDO-Page -Mode Read or
Write Cycle Time
EDO-Page -Mode Read-
Write Cycle Time
Access Time From
Access Time From
Access Time From OE
(note 29)
T224162B
MIN
UNIT
ns
Notes
Address
Access Time From
Precharge
Pulse Width
RAS
Pulse Width
(EDO Page Mode)
RAS
Hold Time
RAS
Precharge Time
CAS
Pulse Width
CAS
Hold Time
CAS
Precharge Time
(EDO Page Mode)
to
CAS
to
Time
Taiwan Memory Technology, Inc. reserves the right P. 4 Publication Date:AUG. 2000
to change products or specifications without notice. Revision:L
Delay Time
RAS
Precharge
CAS
tAA 11 12 13 15 19 23 ns
t
13 14 15 18 22 26 ns 20
ACP
t
22 10K 25 10K 28 10K 35 10K 45 10K 50 10K ns
RAS
t
t
tRP 15 15 17 25 35 37 ns
t
t
tCP 3 3 3 3 5 6
t
t
22 100K 25 100K 28 100K 35 100K 45 100K 50 100
RASC
7 7 7 9 11 13 ns 27
RSH
4 10K 4 10K 4 10K 4 10K 6 10K 8 10K ns 26
CAS
19 20 22 30 40 50 ns 19
CSH
9 15 10 17 10 19 10 26 10 34 19 37 ns 7,18
RCD
3 3 3 3 5 5 ns 19
CRP
ns
ns 23
Page 5
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RAS
CAS
RAS
AC ELECTRICAL CHARACTERISTICS
(continued)
T224162B
AC CHARACTERISTICS
SYM
PARAMETER
Row Address Setup Time
Row Address Hold Time
to Column Address
Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time
(Reference to
Column Address to
RAS
)
RAS
Lead Time
Read Command Setup Time
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
tAR 17 19 21 30 40 45 ns
t
RAL
t
RCS
Read Command Hold Time
t
Reference to
CAS
Read Command Hold Time
Reference to
RAS
to Output in Low -Z
Output Buffer Turn-off
Delay From
CAS
or
RAS
Output Buffer Turn-off to
OE
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time
(Reference to
RAS
)
Write Command Pulse
Width
Write Command to
RAS
Lead Time
Write Command to
CAS
Lead Time
Data -in Setup Time
Data -in Hold Time
Data -in Hold Time
(Reference to
RAS
to
WE
)
Delay Time
RCH
t
RRH
t
CLZ
t
OFF1
t
OFF2
t
WCS
t
WCH
t
WCR
tWP 4 4 4 4 6 8 ns
t
RWL
t
CWL
tDS 0 0 0 0 0 0 ns
tDH 4 4 4 4 6 7 ns
t
DHR
t
RWD
AC ELECTRICAL CHARACTERISTICS
-22 -25 -28 -35 -45 - 50
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
0 0 0 0 0 0 ns
5 5 5 5 5 5 ns
8 11 8 12 8 13 8 20 8 26 10 29 ns
0 0 0 0 0 0 ns
4 4 4 4 6 7 ns
11 12 13 15 19 23 ns
0 0 0 0 0 0 ns
0 0 0 0 0 0 ns
0 0 0 0 0 0 ns
3 3 3 3 3 3 ns
3 3 3 3 15 3 15 3 15 ns
8 8 8 8 8 8 ns
0 0 0 0 0 0 ns
4 4 4 4 6 7 ns
19 19 21 30 46 51 ns
6 6 6 7 9 10 ns
5 5 5 7 9 11 ns
19 19 21 30 40 45 ns
31 34 37 51 61 70 ns
continued
(
)
UNIT
Notes
8
18
18
15,18
9,15,
19
9
20
10,17,
20
17,28
11,15,
18
15,27
15
15
15
15,19
12,20
12,20
11
Taiwan Memory Technology, Inc. reserves the right
P. 5
Publication Date:AUG. 2000
to change products or specifications without notice. Revision:L
Page 6
TE
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OE
WE
OE
CAS
-22
AC CHARACTERISTICS
SYM
PARAMETER
Column Address to
Delay Time
CAS
to
WE
Transition Time (rise or fall)
Refresh Period (512 cycles)
RAS
to
CAS
Time
CAS
Setup Time (CBR
REFRESH)
CAS
Hold Time (CBR
REFRESH)
Hold Time From
During Read -Modify-Write
WE
Delay Time
Precharge
t
21 21 24 31 35 43 ns 11
AWD
t
17 17 18 25 27 33 ns 11,18
CWD
tT 1.5 50 1.5 50 1.5 50 2.5 50 2.5 50 2.5 50 ns 2,3
t
8 8 8 8 8
REF
t
10 10 10 10 10 10 ns
RPC
t
5 5 5 10 10 10 ns 1,18
CSR
t
7 7 7 10 10 10
CHR
t
4 4 4 4 6 8 ns 16
OEH
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
-25
-28
-35
-45 -50
T224162B
UNIT
8 ms
ns
Cycle
OE
Low to
Setup Time
OE
High Hold Time From
CAS
High Pulse Width
OE
Setup Prior to
During Hidden Refresh
High
CAS
High
CAS
t
4 4 4 4 5 5 ns
OES
t
2 2 2 2 2 2 ns
OEHC
t
2 2 2 2 2 2
OEP
ns
t
0 0 0 0 0 0 ns
ORD
Cycle
Last
First
Data Output Hold After
Returning Low
Output Disable Delay From
WE
Going Low to
CAS
Returning High
CAS
t
4 4 4 4 6 8 ns 21
CLCH
t
3 3 3 3 4 5 ns
COH
t
3 6 3 7 3 7 3 7 3 7 3
WHZ
9 ns
Notes
1,19
Taiwan Memory Technology, Inc. reserves the right
P. 6
Publication Date:AUG. 2000
to change products or specifications without notice. Revision:L
Page 7
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≥
≥
≥
≥
OE
CAS
WE
OE
RAS
WE
CAS
CASL
CAS
CAS
CAS
Notes:
1. Enables on-chip refresh and address counters.
2. VIH(2.4V) and VIL(0.8V) are reference
levels for measuring timing of input signals.
Transition times are measured between V
and V
(2.4V)
3. In addition to meet the transition rate
specification, all input signals must transit
between VIH and VIL in a monotonic manner.
4. Assume that t
greater than the maximum recommended value
shown in this table, t
amount that t
5. Assume that t
CAS
6. If
data-out will be maintained from the previous
cycle. To initiate a new cycle and clear the
data-out buffer,
pulsed high.
7. Operation within the t
that t
RAC
specified as a reference point only; if t
greater than the specified t
access time is controlled by t
8. Operation within the t
t
(max) can be met. t
RAC
specified as a reference point only; if t
greater than the specified t
access time is controlled by tAA.
9. Either t
READ cycle.
10. t
OFF1
output achieves the open circuit condition; it is
not a reference to VOH or VOL.
11. t
WCS
restrictive operating parameters in LATE
WRITE and READ-MODIFY-WRITE cycles
only. If t
EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle. If t
t
AWD
cycle is READ-WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of I/O (at access time and until
RAS
or OE go back to VIH) is indeterminate.
held high and WE taken low after
IL (0.8V)
RCD
RCD
RCD
is low at the falling edge of
(max) can be met. t
or t
RCH
(max) defines the time at which the
, t
RWD
≥ t
WCS
RWD
(min) and t
.
< t
RAC
exceeds the value shown.
CAS
RRH
, t
AWD
WCS
CWD
(max). If t
RCD
will increase by the
t
(max) .
RCD
RAS
and
(max) limit ensures
RCD
RCD
(max) limit,
RCD
.
CAC
limit ensures that
RAD
RAD
(max) limit,
RAD
must be satisfied for a
and t
(min), the cycle is an
t
RWD
CWD
(min), t
t
CWD
(min), the
IH
is
RCD
RAS
must be
(max) is
is
RCD
(max) is
is
RAD
are
AWD
CAS
and
T224162B
goes low result in a LATE WRITE(
controlled) cycle.
12. These parameters are referenced to
leading edge in EARLY WRITE cycles and
leading edge in LATE WRITE or READ -
MODIFY-WRITE cycles.
13. During a READ cycle, if OE is low then taken
HIGH before
if
WRITE or READ-MODIFY-WRITE
operation is not possible.
14. An initial pause of 100ms is required after
,
power-up followed by eight
cycles (
device operation is assured. The eight
cycle wake-ups should be repeated any time
the t
REF
15. WRITE command is defined as
16. LATE WRITE and READ-MODIFY-WRITE
cycles must have both t
(OE high during WRITE cycle) in order to
ensure that the output buffers will be open
during the WRITE cycles.
17. The I/Os open during READ cycles once
t
or t
OFF1
18. The first
19. The last
20. Output parameter (I/O) is referenced to
corresponding
and IO9~16 by
21. Last falling
22. Last rising
CAS
edge.
23. Last rising
24. First IOs controlled by the first
25. Last IOs controlled by the last
26. Each
27. Last
28. All IOs controlled, regardless
29. Data outputs are measured with a load of 50pF.
CAS
CASH
.
The output reference levels are VOH/VOL
=2.0V/0.8V; The input levels are VIH/VIL=
3.0V/0V.
CAS
goes high, I/O goes open,
is tied permanently low, a LATE
only or CBR) before proper
refresh requirement is exceeded.
and t
OFF2
occur.
OFF2
CAS
edge to transition low.
CAS
edge to transition high.
input, IO1~8 by
CASH
.
CAS
edge to first rising
edge to next cycle's last rising
CAS
edge to first falling
CAS
must meet minimum pulse width.
to go low.
RAS
refresh
going low.
OEH
CAS
CAS
to go low.
to go high.
CASL
OE
-
CAS
RAS
met
edge.
edge.
and
Taiwan Memory Technology, Inc. reserves the right P. 7 Publication Date:AUG. 2000
to change products or specifications without notice. Revision:L
Page 8
C
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tm
TE
RAS
CAS L, CA SH
ADD R
WE
I/O
OE
T224162B
READ CYCLE
t
RC
t
R A S
V
IH
V
IL
t
C R P
V
IH
V
IL
t
t
A S R
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
R A D
R A H
t
t
t
t
R C D
A R
AS C
RC S
C O L U MN R O WR O W
t
C S H
t
R SH
t
C A S tC L C H
t
R A L
t
C A H
t
A A
t
R A C
t
C A C
t
C L Z
t
O A C
EARLY WRITE CYCLE
t
t
R R H
t
N O T E 1
t
OF F 1
V A L ID D A T A
t
OF F 2
R P
R C H
O P E NO P E N
Note: 1. t
V
IH
RAS
V
IL
t
C R P
V
CAS L,C AS H
OFF1
IH
V
IL
t
A S R
V
IH
ADD R
V
IL
V
IH
WE
V
IL
V
IOH
I/O
V
IOL
V
IH
OE
V
IL
is referenced from the rising edge of
t
t
R AD
R A H
t
t
t
R C D
t
A R
t
AS C
t
WC S
t
D S
V A L ID D A T A
RAS
R C
R A S
C O L U MN R O WRO W
t
C S H
t
R SH
t
C A S tC L C H
t
R A L
t
C A H
t
C WL
t
R WL
t
WC R
t
WC H
t
WP
t
D H R
t
D H
CAS
or
t
R P
DON'T CARE
UNDEFINED
, whichever occurs last.
Taiwan Memory Technology, Inc. reserves the right
P. 8
Publication Date: AUG. 2000
to change products or specifications without notice. Revision:L
Page 9
C
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TE
RAS
CAS L,C ASH
ADD R
WE
I/O
T224162B
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
t
R WC
t
R A S
V
IH
V
IL
t
C R P
V
IH
V
IL
t
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
OE
V
IL
A SR
t
A R
t
R A D
t
R A H
t
t
t
AS C
RC S
R CD
t
C O L U M N RO WR O W
CL Z
t
C S H
t
R SH
t
C A S tC L C H
t
R A L
t
C A H
t
R WD
t
C WD
t
A WD
t
A A
t
R A C
t
C A C
t
OA C
VAL ID D
t
OF F 2
OUT
D S
V A L ID D
t
t
t
tDHt
C WL
R WL
WP
IN
t
OE H
t
R P
O P E NO P E N
CAS L,CA SH
Note: 1. t
2. t
EDO-PAGE-MODE READ CYCLE
V
IH
RAS
V
IL
t
C R P
V
IH
V
IL
t
A S RtR A H
V
IH
ADD R
V
IL
V
IH
WE
V
IL
V
OH
I/O
V
OL
V
IH
OE
V
IL
is referenced from the rising edge of
OFF1
can be measured from falling edge of
PC
CAS
to rising edge of
t
R A D
t
C S H
t
R C D
t
A R
t
A S C
C O L U M N R O WRO W
t
R C S
t
C L Z
RAS
. Both measurements must meet the t
t
C A S ,tC L C H
t
C A H
t
A A
t
R A C
t
C A C
t
O A C
t
O E S
t
R A S C
t
P C ( N O T E 2 )
t
C P
t
A S CtC A H
C O L U M N
t
C O H
V AL ID
D A T A
RAS
CAS
CAS
or
to falling edge of
t
t
C AS ,tC L C H
t
A A
t
A C P
t
C A C
VAL ID
D A T A
t
O FF 2
C P
t
A S CtC A H
C O L U M N
t
C L Z
t
O E H C
t
O E P
t
C AS ,tC L C H
t
t
A C P
t
C A C
t
, whichever occurs last.
CAS
, or from rising edge of
specification.
PC
t
A A
O A C
R S H
t
O E S
t
R A L
t
R C H
VA L ID
D A T A
t
R P
t
C P N
t
R R H
N O T E 1
t
O F F 1
O P E NO P E N
t
O F F 2
DON'T CARE
UNDEF I NE D
Taiwan Memory Technology, Inc. reserves the right
P. 9
Publication Date: AUG. 2000
to change products or specifications without notice. Revision:L
Page 10
TE
C
H
tm
T224162B
EDO-PAGE-MODE EARLY-WRITE CYCLE
RAS
CASL ,CASH
ADDR
WE
I/O
t
R A S C
V
IH
V
IL
t
C R P
V
IH
V
IL
t
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
OE
V
IL
A S RtR A H
t
t
C S H
R A D
t
R C D
t
A R
t
A S CtC A H
t
W C S
t
D S
V AL ID D A T A
t
t
CA S ,tC L C H
C O L U M N C O L U M N C O L U M N R O WRO W
t
C W L
t
W C H
t
W P
t
W C R
t
D H R
t
D H
P C
t
t
C P
C A S ,tC L C H
t
A S CtC A H
t
t
C W L
t
W C S
W C H
t
W P
t
D StD H
VA L ID D A T A V A L ID D A T A
t
C P
t
t
t
A S CtC A H
t
W C S
D S
t
R S H
C A S ,tC LC H
t
R A L
t
C W L
t
W C H
t
W P
t
t
D H
R W L
t
R P
t
C P N
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE CYCLES)
VAL I D
D
I N
t
O F F 2
t
O E H
t
t
t
W P
D H
t
t
C W L
O PE NO P E N
R P
t
C P N
R W L
RAS
CAS L ,C ASH
ADDR
OE
WE
I/O
t
R A S C
V
IH
V
IL
t
C R P
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
V
IL
t
t
t
A S RtR A H
A R
R A D
t
R A C
t
R C D
t
A S CtC A H
C O L U M N RO WR O W
t
R C S
t
A A
t
C A C
t
C L Z
t
t
C S H
O A C
t
C A S , tC L C H
t
R W D
t
C W L
t
W P
t
A W D
t
C W D
t
D H
t
D S
VA LI D
VAL I D
D
D
OU T
t
C PtC A S , tC L C H
t
A S CtC A H
C O L U M N
t
A A
t
A C P
t
C A C
t
C L Z
I N
t
O F F 2
t
O A C
t
t
t
P C M
A W D
C W D
t
t
VAL I D
D
C W L
t
W P
t
D H
D S
O U T
VA LI D
D
I N
t
O F F 2
t
C P
t
A S CtC A H
C O L U M N
t
A A
t
A C P
t
C A C
t
C L Z
t
O A C
t
R S H
t
C A S , tC LC H
t
R A L
t
A W D
t
C W D
t
D S
VAL I D
D
O U T
DON'T CAR E
Note: 1. t
UNDEF I NE D
can be measured from falling edge to falling edge of CAS, or from rising edge to rising edge of
PC
CAS. Both measurements must meet the tPC specification.
Taiwan Memory Technology, Inc. reserves the right P. 10 Publication Date: AUG. 2000
to change products or specifications without notice. Revision:L
Page 11
TE
C
H
tm
RAS
OE,WE
T224162B
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ -MODIFY-WRITE)
t
R A SC
V
IH
RAS
V
CAS
ADD R
WE
I/O
OE
IL
t
C R P
V
IH
V
IL
t
R AD
t
A S RtR A H
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
V
IL
t
C S H
t
R C D
t
A R
t
A S C
C O L U M N ( A ) C O L U M N ( B ) C O L U M N ( N )
t
R C S
t
R A C
O P E N
t
P C
t
C A S
t
C A H
t
A A
t
C A C
t
OA C
t
C P
t
A SCtC A H
t
AC P
V A L I D D A T A ( A )
t
A A
t
C A C
t
C O H
t
C A S
t
R C H
t
P C
t
t
WH Z
V A L ID
D A T A ( B )
C P
t
A S CtC A H
t
WC S
t
D StD H
VALID DATA
t
R S H
t
C A S
t
R A L
t
WC H
IN
t
R P
t
C P
RO WR O W
CAS L,C ASH
RAS
AD DR
I/O
ONLY REFRESH CYCLE
(ADDR=A0-A8 ;
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
t
C R P
t
A SR
t
R A H
=DON‘T CARE)
t
t
R A S
R C
O P E N
t
RP C
t
R P
R O WRO W
DON'T CARE
UNDEFINED
Taiwan Memory Technology, Inc. reserves the right P. 11 Publication Date: AUG. 2000
to change products or specifications without notice. Revision:L
Page 12
TE
C
H
tm
WE
T224162B
CBR REFRESH CYCLE
(A0 -A8 ; OE =DON‘T CARE)
CA SH,CA S L
CAS L ,C ASH
RAS
RAS
ADD R
I/O
OE
I/O
WE
t
C H R
t
R A S
t
R P
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
R P C
t
C P N
t
C S R
t
R P
t
RP CtC S R
O P E N
t
C H R
t
R A S
HIDDEN REFRESH CYCLE
=HIGH ; OE=LOW)
(
( R E A D )
t
R A S
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
t
C R P
t
A SRtR A H
R OW
C OL U MN
R A C
t
R SH
t
R A L
t
A A
t
C A C
t
C L Z
t
R C D
t
A R
t
R A D
O P EN V AL ID D A T A
t
A S CtC A H
t
t
OA C
t
ORD
t
R P
(R E F R E S H )
t
R A S
t
C H R
t
O F F 2
N O T E 1
t
O F F 1
O P EN
DON'T CARE
UNDEFINED
Note: 1. t
is referenced from the rising edge of
OFF1
Taiwan Memory Technology, Inc. reserves the right
RAS
P. 12
or
CAS
, whichever occurs last.
Publication Da te: AUG. 2000
to change products or specifications without notice. Revision:L
Page 13
TE
C
H
tm
PACKAGE DIMENSIONS
40-LEAD SOJ DRAM (400 mil)
T224162B
SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM
A 1.025±0.010 26.035±0.254
B 0.400±0.005 10.160±0.127
C 0.045(MAX) 1.143(MAX)
D 0.050±0.006 1.27±0.152
E 0.019±0.003 0.483±0.08
F 0.026±0.003 0.661±0.080
G 0.440±0.010 11.176±0.254
H 0.011±0.003 0.280±0.080
I 0.025(MIN) 0.635(MIN)
J 0.364±0.020 9.246±0.508
K 0.047±0.006 1.194±0.152
L 0.150(MAX) 3.810(MAX)
y 0.004(MAX) 0.102(MAX)
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice. Revision:L
P. 13
Publication Da te: AUG. 2000
Page 14
TE
C
H
tm
PACKAGE DIMENSIONS
40-LEAD TSOP II DRAM (400 mil)
T224162B
"A"
SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM
A 0.047(max) 1.20(max)
A1 0.004±0.002 0.10±0.05
A2 0.039±0.002 1.00±0.05
b 0.014(typ.) 0.35(typ.)
e 0.030(typ.) 0.80(typ.)
D 0.725±0.004 18.41±0.10
E 0.463±0.008 11.76±0.20
E1 0.400±0.004 10.16±0.10
L1' 0.031 0.80
L' 0.020±0.004 0.500±0.10
y 0.004(max) 0.10(max)
θ
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice. Revision:L
0°~5° 0°~5°
P. 14
Publication Da te: AUG. 2000
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