Datasheet T224160B Datasheet (Taiwan Memory Technology)

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CAS

T224160B

DRAM

FEATURES

•

Industry-standard x 16 pinouts and timing

functions.

•

Single 5V (±10%) power supply.

•

All device pins are TTL- compatible.

•

512-cycle refresh in 8ms.

•

Refresh modes:

RAS

(CBR) and HIDDEN.

•

Conventional FAST PAGE MODE access cycle.

•

BYTE WRITE and BYTE READ access

RAS

only,

CAS

BEFORE

cycles.

OPTION

TIMING MARKING

30ns -30 35ns -35 45ns -45 60ns -60

PACKAGE MARKING

SOJ J TSOP(II) S

GENERAL DESCRIPTION

The T224160B is a randomly accessed solid state memory containing 4,194,304 bits organized in a x16 configuration. The T224160B has both BYTE WRITE and WORD WRITE access cycles via two

CAS

pins. It offers Fast Page mode operation The T224160B determined by the first by the last to transition back high. Use only one of the two WRITE will result in a BYTE WRITE. transiting low in a WRITE cycle will write data into the lower byte (IO1~IO8), and

CAS

function and timing are

CAS

to transition low and

and leave the other staying high during

CASH

CASL

transiting low

256K x 16 DYNAMIC RAM

FAST PAGE MODE

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vss I/016 I/015 I/014 I/013 Vss I/012 I/011 I/010 I/09 NC CASL CASH OE A8 A7 A6 A5 A4 VSS

40

Vss

39

I/016

38

I/015

37

I/014

36

I/013

35

Vss

34

I/012

33

I/011

32

I/010

31

I/09

30

NC

29

CASL

28

CASH

27

OE

26

A8

25

A7

24

A6

23

A5

22

A4

21

VSS

will write data into the upper byte (IO9~16).

PIN ASSIGNMENT ( Top View )

Vcc I/01 I/02 I/03 I/04 Vcc I/05 I/06 I/07 I/08

NC NC

WE

RAS

NC

A0 A1 A2 A3

Vcc

10 11 12 13 14 15 16 17 18 19 20

1 2 3 4 5 6 7 8 9

SOJ

Vcc I/01 I/02 I/03 I/04 Vcc I/05 I/06 I/07 I/08

NC NC

WE

RAS

NC

A0 A1 A2 A3

Vcc

1 2 3 4 5 6 7 8 9

10

TSOP(II)

11 12 13 14 15 16 17 18 19 20

Taiwan Memory Technology, Inc. reserves the right P. 1 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

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CASH

FUNCTIONAL BLOCK DIAGRAM

WE

T224160B

RAS

CASL

CASH

NO.2 CLOCK

GENERATOR

COLUMN.

ADDRESS

9

A0 A1 A2

A3 A4

A5 A6 A7 A8

REFRESH

CONTROLLER

REFRESH COUNTER

ADDRESS

9

BUFFERS(9)

NO.1 CLOCK

GENERATOR

CAS

BUFFER

9

ROW.

CONTROL

LOGIC

9

ROW

DECODER

9

512

COLUMN

DECODER

DATA-IN BUFFER

512

SENSE AMPLIFIERS

VO GATING

512 x 16

512 x 512 x 16

MEMORY

ARRAY

8

DATA-OUT

BUFFER

16

OE

Vcc

Vss

DQ01

. .

DQ16

PIN DESCRIPTIONS

PIN NO. SYM. TYPE DESCRIPTION

16~19,22~26 A0-A8 Input Address Input

14 RAS 28 29 CASL 13 WE 27 OE

2~5,6~10,31~34,36~39 I/O1 - I/O16 Input/ Output Data Input/ Output

1,6,20 Vcc Supply Power, 5V

21,35,40 Vss Ground Ground

11,12,15,30 NC - No Connect

Taiwan Memory Technology, Inc. reserves the right P. 2 Publication Date: MAR. 2001 to change pr oducts or specifications without notice. Revision:B

Input Row Address Strobe Input Column Address Strobe /Upper Byte Control Input Column Address Strobe /Lower Byte Control Input Write Enable Input Output Enable

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T224160B

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any pin Relative to VSS… … -1V to 7V Operating Temperature, Ta (ambient)..0°C to +70°C

Storage Temperature (plastic)….... -55°C to +150°C

Power Dissipation ...............................….........

1.2W

Short Circuit Output Current...................…....

50mA

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)

DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES

Supply Voltage Supply Voltage Input High (Logic) voltage Input Low (Logic) voltage Input Leakage Current

Output Leakage Current Output High Voltage IOH = -5 mA VOH 2.4 - V

Output Low Voltage IOL = 4.2 mA VOL - 0.4 V

0V ≤ VIN ≤ 7V 0V ≤ V Output(s) disabled

OUT

≤

7V

Vcc 4.5 5.5 V 1

Vss 0 0 V

VIH 2.4 Vcc+1 V 1

VIL -1.0 0.8 V 1

ILI -10 10 uA

ILO -10 10 uA

Note: 1.All Voltages referenced to Vss

Taiwan Memory Technology, Inc. reserves the right P. 3 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

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RAS

CAS

DC CHARACTERISTICS

(Ta = 0 to 70°C, Vcc = 5V ±10%, Vss = 0V)

T224160B

Parameter Symbol

Operating Current

Standby Current

Fast Page Mode Current

RAS

-only refresh

Current

CAS

Before

Refresh Current

RAS

Icc1 - 200 - 180 - 160 - 140 mA

Icc2 - 4 - 4 - 4 - 4 mA

Icc3 - 2 - 2 - 2 - 2 mA

Icc4 - 200 - 180 - 160 - 140 mA

Icc5 - 200 - 180 - 160 - 140 mA

Icc6 - 200 - 180 - 160 - 140 mA

-30 -35 -45 -60

Min Max Min Max Min Max Min Max

Unit Test Condition

RAS, CAS

tRC=min TTL interface,

RAS,CAS

D

OUT

CMOS interface,

RAS, CAS RAS

cycling, tPC= min

CAS

cycling, tRC= min

RAS,CAS

tRC= min

=High-Z

=VIL,

=VIH,

cycling

=VIH,

> Vcc-0.2V

CAS

RAS

cycling,

Note: Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition, Icc is specified as an average current.

CAPACITANCE

(Ta =25°C, Vcc =5V, f = 1M HZ)

Parameter Symbol Typ Max Unit

Input Capacitance

(address)

Input Capacitance

(

,

,WE,OE)

Output Capacitance

(data-in/out)

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CI1 - 5 pF

CI2 - 7 pF

C

- 10 pF

I/O

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CAS

RAS

AC CHARACTERISTICS

AC TEST CONDITIONS: Vcc=5V ±10%, input pulse level = 0 to 3V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (50pF)

(note 1,2,3) (Ta = 0 to 70°C)

T224160B

-30 -35 -45 -60 AC CHARACTERISTICS

MIN MAX MIN MAX MIN MAX MIN MAX

PARAMETER

SYM

Read or Write Cycle Time tRC 55 65 85 110 ns Read-Modify -Write Cycle Time t

85 95 115 155 ns

RWC

Fast-Page-Mode Read or Write Cycle Time tPC 19 21 25 40 ns Fast-Page-Mode Read-Write Cycle Time t

Access Time From Access Time From

RAS CAS

Access Time From OE

56 58 65 80 ns

PCM

t

30 35 45 60

RAC

t

8 9 11 15

CAC

t

8 9 11 15

OAC

Access Time From Column Address tAA 13 15 19 30 ns

t

Access Time From

RAS

Pulse Width

RAS

Pulse Width

RAS

Hold Time

RAS

Precharge Time

Precharge

Pulse Width

CAS

Hold Time

Precharge Time RAS CAS

to

CAS

Delay Time

RAS

Precharge Time Row Address Setup Time t Row Address Hold Time t

RAS

to Column Address Delay Time Column Address Setup Time t Column Address Hold Time t Column Address Hold Time (Reference to

RAS

) Column Address to

RAS

Lead Time

Read Command Setup Time t Read Command Hold Time Reference to

Read Command Hold Time Reference to

RAS t

to Output in Low-Z Output Buffer Turn-off Delay From

CAS

or

15 18 22 35

ACP

t

30 10K 35 10K 45 10K 60 10K

RAS

t

RASC

t

8 9 11 15

RSH

30

100K

35

100K

45

100K

60

tRP 25 30 35 40 t

5 10K 6 10K 7 10K 15 10K

CAS

t

30 35 45 60

CSH

3 3 5 10

tCP t

10 24 10 28 10 37 20 45

RCD

t

3 3 5 5

CRP

0 0 0 0 ns

ASR

5 5 5 5 ns

RAH

t

8 17 8 20 8 26 15 30

RAD

0 0 0 0 ns

ASC

4 4 6 15 ns

CAH

tAR 26 30 40 50 t

13 15 19 30

RAL

0 0 0 0 ns

RCS

t

0 0 0 0

RCH

0 0 0 0

RRH

t

3 3 3 3

CLZ

t

3 15 3 15 3 15 3 15

OFF1

100K

UNIT

ns ns ns

ns ns ns ns ns ns ns ns ns ns

ns

ns ns

Note

s

4 5 13 8

7

8

14 9,14

9

10,16

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RAS

CAS

AC CHARACTERISTICS

(continued)

T224160B

AC CHARACTERISTICS

PARAMETER

Output Buffer Turn-off OEto Write Command Setup Time t

Write Command Hold Time t Write Command Hold Time (Reference

to

)

SYM

t

OFF2 WCS WCH

t

WCR

Write Command Pulse Width tWP 4 4 6 10 Write Command to Write Command to

RAS CAS

Lead Time Lead Time

t

RWL

t

CWL

Data-in Setup Time tDS 0 0 0 0 Data-in Hold Time tDH 4 4 6 15

Data-in Hold Time (Reference to

RAS

to

WE

Delay Time

RAS

Column Address to WE Delay Time

CAS

Transition Time (rise or fall) tT 1.5 50 2.5 50 2.5 50 3 50

to

WE

Delay Time

Refresh Period (512 cycles) t

RAS

to

CAS

Precharge Time

Setup Time (CBR REFRESH)

CAS

Hold Time (CBR REFRESH)

OE

Hold Time From WEDuring Read-

t

)

DHR

t

RWD

t

AWD

t

CWD

REF

t

RPC

t

CSR

t

CHR

t

OEH

-30 -35 -45 -60

MIN MAX MIN MAX MIN MAX MIN MAX

- 8 - 8 - 8 - 15

0 0 0 0

4 4 6 10

26 30 46 50

6 7 9 15 6 7 9 15

26 30 40 50

46 51 61 85 29 31 35 55

24 25 27 40

8 8 8 8

10 10 10 10

10 10 10 10 4 4 6 15

UNIT

ns ns ns ns

ns ns ns

ns ns ns ns ns ns ns

ms

ns ns ns ns

16 11,14

14

14 14

14 12

12

11

11 11 2,3

6 6 15

Note

s

Modify -Write Cycle

OE

Setup Prior to

RAS

During Hidden

t

0 0 0 0

ORD

ns

Refresh Cycle Write Command Hold Time (Test Mode in) t

Write Command Setup Time (Test Mode in) t

10 10 10 10

WTH

10 10 10 10

WTS

ns ns

Taiwan Memory Technology, Inc. reserves the right P. 6 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

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RAS

≥

WE

Notes:

1. An initial pause of 200us is required after power-up followed by eight cycles ( device operation is assured. The eight cycle wake-ups should be repeated any time the t

REF

2. VIH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between V

IH(2.4V)

3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner.

4. Assume that t greater than the maximum recommended value shown in this table, t amount that t

5. Assume that t

6. Enables on-chip refresh and address counters.

7. Operation within the t that t

RAC

specified as a reference point only; if t greater than the specified t access time is controlled by t

8. Operation within the t t

(max) can be met. t

RAC

specified as a reference point only; if t greater than the specified t access time is controlled by tAA.

9. Either t READ cycle.

10. t output achieves the open circuit condition; it is not a reference to V

RCH

(max) defines the time at which the

OFF1

only or CBR) before proper

refresh requirement is exceeded.

and V

IL(0.8V)

< t

RCD

(max) can be met. t

or t

RCD

RAC

exceeds the value shown.

t

RCD

RAD

must be satisfied for a

RRH

or VOL.

OH

RAS

refresh

RAS

.

(max). If t

will increase by the

(max) .

(max) limit ensures

RCD

(max) limit,

RCD

.

CAC

limit ensures that

RAD

(max) limit,

RAD

is

RCD

(max) is

is

RCD

(max) is

is

RAD

T224160B

11. t

12. These parameters are referenced to

13. During a READ cycle, if OE is low then taken

14. WRITE command is defined as

15. LATE WRITE and READ-MODIFY-WRITE

16. The I/Os open during READ cycles once

, t

WCS

restrictive operating parameters in LATE WRITE and READ -MODIFY-WRITE cycles only. If t

EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If t t

(min) and t

AWD

cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until

RAS

or OE go back to VIH) is indeterminate.

OE

held high and WE taken low after goes low result in a LATE WRITE (OEcontrolled) cycle.

leading edge in EARLY WRITE cycles and

WE

leading edge in LATE WRITE or READ-

MODIFY-WRITE cycles.

HIGH before

OE

if WRITE or READ-MODIFY-WRITE operation is not possible.

cycles must have both t (OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles.

t

OFF1

is tied permanently low, a LATE

or t

RWD

WCS

RWD

OFF2

, t

≥ t

CAS

occur.

and t

AWD

(min), the cycle is an

WCS

t

(min), t

RWD

OFF2

t

CWD

and t

CWD

goes high, I/O goes open,

are

CWD

AWD

(min), the

CAS

and

CAS

going low.

met

OEH

Taiwan Memory Technology, Inc. reserves the right P. 7 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

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T224160B

READ CYCLE

t

R C

t

R A S

V

IH

RAS

V

CAS

ADD R

WE

I/O

OE

IL

t

C R P

V

IH

V

IL

t

A S R

V

IH

V

IL

V

IH

V

IL

V

OH

V

OL

V

IH

V

IL

t

R A D R A H

t

R C D

t

A R

t

A S C

t

R C S

t

C SH

t

R SH

t

C A S

t

R AL

t

C A H

C O L U M N R O WRO W

t

A A

t

R AC

t

C AC

t

C L Z

t

O A C

EARLY WRITE CYCLE

t

R P

t

R R H

t

RC H

N O T E 1 t

OF F 1

V A L ID D A T A

t

O F F 2

O P E NO P E N

Note: t

V

IH

RAS

V

IL

t

C R P

V

IH

CAS

V

IL

t

A S R

V

IH

ADD R

V

IL

V

IH

WE

V

IL

V

IOH

I/O

V

IOL

V

IH

OE

V

IL

is referenced from the rising edge of

OFF1

R A D

t

R A H

t t

t

RC D

t

A R

t

A S C

t

WC S

t

D S

V A L ID D A T A

RAS

R C R A S

C O L U M N R O WR O W

or

t

C S H

t

R S H

t

C A S

t

R A L

t

C A H

t

C W L

t

R W L

t

W C R

t

W C H

t

W P

t

D H R

t

D H

CAS

, whichever occurs last.

R P

DON'T CARE

UNDEFINED

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t

Note: 1. t

2. t

TE

READ WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE CYCLES)

V

IH

RAS

V

IL

t

C R P

V

IH

CAS

V

IL

t

V

IH

ADDR

V

IL

V

IH

WE

V

IL

V

IOH

I/O

V

IOL

V

IH

OE

V

IL

V

IH

RAS

V

IL

t

CRP

V

IH

CAS

V

IL

t

ASRtRAH

V

IH

ADDR

V

IL

V

IH

WE

V

IL

V

OH

I/O

V

OL

V

IH

OE

V

IL

is referenced from the rising edge of

OFF1

can be measured from falling edge of

PC

CAS

to rising edge of

t

A R

t

R AD

t

A SR

R A H

FAST-PAGE-MODE READ CYCLE

t

CSH

t

RCD

t

RAD

AR

t

ASC

COLUMN ROWROW

t

RCS

t

CLZ

OPEN OPEN

CAS

. Both measurements must meet the t

t

CAH

t t t

t

AA RAC CAC

t

CAS

OAC

t

A SC

R C S

t

R WC

t

R A S

RC D

t

C L Z

t

C S H

t

R SH

t

C A S

t

R AL

t

C A H

C O L U M N RO WRO W

t

R WD

t

C WD

t

A WD

t

A A

t

R A C

t

C AC

t

OA C

RASC

t

PC

t

CP

t

ASCtCAH

COLUMN

t

OFF 1

t

CLZ

VALID

DATA

t

OFF 2

RAS

or

CAS

to falling edge of

t

C WL

t

R WL

t

WP

tDHt

D S

VALID D

t

CAS

t

AA

t

ACP

t

CAC

t

OAC

CAS

V A LID D

t

OF F 2

OUT

VALID

DATA

t

OFF 1

OFF 2

t

CP

IN

t

ASCtCAH

COLUMN

t

CLZ

t

OE H

t

AA

t

ACP

t

CAC

OAC

, whichever occurs last.

CAS

PC

T224160B

t

R P

O P E NO P E N

RP

t

RSH

t

CAS

t

RAL

VALID

DATA

, or from rising edge of

specification.

t

O FF2

t

RCH

t

OFF 1

DON'T CARE

UNDEF INE D

CPN

t

RRH

Taiwan Memory Technology, Inc. reserves the right P. 9 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

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CAS

T224160B

V

IH

RAS

V

IL

V

IH

CAS

V

IL

V

IH

ADDR

V

IL

V

IH

WE

V

IL

V

IOH

I/O

V

IOL

V

IH

OE

V

IL

V

IH

RAS

V

IL

V

IH

CAS

V

IL

V

IH

ADDR

V

IL

V

IH

WE

V

IL

V

IOH

I/O

V

IOL

V

IH

OE

V

IL

FAST-PAGE-MODE EARLY-WRITE CYCLE

t

R A S C

t

C R P

t

A S RtR A H

t

C S H

R A D

t

R C D

t

A R

t

A S CtC A H

t

W C S

t

DS

V AL ID D A T A

t

C O L U M N C O L U M N C O L U M N RO WRO W

t t t

t

W C R

t

D H R

t

D H

C A S

C W L W C H W P

t

P C

t

C P

t

A S CtC A H

t

W C S

t

D StD H

VA L ID D A T A

t t t

t

C A S

C W L W C H W P

t

C P

t

A S CtC A H

t

W C S

t

D S

VALID DATA

t

R A L

t

C W L

t

W C H

t

t t

W P

D H

R S H C A S

t

R W L

FAST-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE CYCLES)

t

R A S C

t

C R P

t

A S RtR A H

t t

A R R A D

t

R A C

t

R C D

t

A S CtC A H

C O L U M N RO WRO W

t

R C S

t

A A

t

C A C

t

C L Z

t

C S H

O A C

t

A W D

t

C W D

t

R W D

t

VALI D

D

C A S

C W L

t

W P

t

D H

D S

O UT

VAL ID

D

I N

t

O F F 2

t

C PtC A S

t

A S CtC A H

C O L U M N

t

A A

t

A C P

t

C A C

t

C L Z

t

O A C

t

P C M

t t

t

A W D C W D

C W L t

t

DS

V ALI D

D

OUT

t

C P

t

A S CtC A H

C O L U M N

W P

t

A A

DH

VALI D

D

I N

t

O F F 2

t t

t

C A C C L Z

t

A C P

O A C

t

A W D

t

C W D

t

D S

VALI D

D

OUT

t

R S H

t

C A S

R A L

V ALI D

D

I N

t

O F F 2

t

O E H

t

C P N

t

C W L

W P

D H

t

R P

t

R W L

O P E NO P E N

C P N

D ON 'T CAR E

Note:

t

can be measured from falling edge to falling edge of

PC

CAS

. Both measurements must meet the tPC specification.

UNDEF I NE D

, or from rising edge to rising edge of

Taiwan Memory Technology, Inc. reserves the right P. 10 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

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RAS

OE,WE

t

T224160B

FAST-PAGE-MODE READ-EARLY-WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

RASC

V

IH

RA S

V

CA S

A D D R

WE

I/O

OE

IL

t

CRP

V

IH

V

IL

t

RAD

t

ASRtRAH

V

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

t

CSH

t

RCD

t

AR

t

ASC

COLUMN(A) COLUMN(B) COLUMN(N)

t

RCS

t

RAC

OPEN

t

PC

t

CAS

t

CAH

t

AA

t

CAC

t

OAC

t

OFF1

VAL ID

DAT A (A)

t

CP

t

ASCtCAH

t

ACP

t

CLZ

t

CAC

t

PC

t

CAS

t

RCH

AA

t

O FF1

VALID

DATA (B)

t

CP

t

WCS

NOTE1

t

ASCtCAH

t

tDSt

DH

VALID

DATA IN

WCH

t

t t

RAL

RSH CAS

RP

t

CP

ROWROW

(ADDR=A0 -A8 ;

V

IH

RAS

V

IL

V

IH

CAS

V

IL

V

IH

ADDR

V

IL

V

OH

I/O

V

OL

Note1:Do not drive data prior to tristate.

t

C R P

A S R

t

R A H

ONLY REFRESH CYCLE

=DON‘T CARE)

t

R A S

RC

O P E N

t

R P C

t

R P

RO WR O W

DON'T CARE

UNDEFINED

Taiwan Memory Technology, Inc. reserves the right P. 11 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

TE

C

H

tm

T224160B

CBR REFRESH CYCLE

(A0-A8 ;

=DON‘T CARE)

OE

RAS

CA SH,CA S L

Note: 1. t

t

R P

V

IH

V

I/O

WE

IL

V

IH

V

IL

V

IH

V

IL

t

R P C

t

C P N

t

C S R

HIDDEN REFRESH CYCLE

V

IH

R A S

V

IL

V

IH

C A S

V

IL

V

IH

A D D R

V

IL

V

OH

I /O

V

OL

V

IH

OE

V

IL

is referenced from the rising edge of

OFF1

t

C R P

t

A S RtR A H

R O W

t

R A D

O P E N V A L I D D A T A

t

R A S

t

C H R

=HIGH ; OE=LOW)

WE

(

t

R C D

t

A R

(R E A D)

t

R A S

t

A S CtC A H

C O L U M N

t

R A C

t

R S H

t

R A L

t

A A

t

C A C

t

C L Z

t

O A C t

ORD

RAS

t

R P

t

RP CtC S R

O P E N

t

R P

CAS

or

t

R A S

t

C H R

(R E F R E S H )

t

R A S

t

C H R

, whichever occurs last.

t

O F F 2

N O T E 1

t

O FF 1

O P E N

Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

TE

C

H

tm

T224160B

PACKAGE DIMENSIONS 40-LEAD SOJ DRAM (400 mil)

SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM

A 1.025±0.010 26.035±0.254

B 0.400±0.005 10.160±0.127 C 0.045(MAX) 1.143(MAX)

D 0.050±0.00 6 1.27±0.152

E 0.019±0.003 0.483±0.08

F 0.026±0.003 0.661±0.080

G 0.440±0.010 11.176±0.254

H 0.011±0.003 0.280±0.080

I 0.025(MIN) 0.635(MIN) J 0.364±0.020 9.246±0.508

K 0.047±0.006 1.194±0.152

L 0.150(MAX) 3.810(MAX)

y 0.004(MAX) 0.102(MAX)

Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B

TE

C

H

tm

T224160B

PACKAGE DIMENSIONS 40-LEAD TSOP II DRAM (400 mil)

"A"

SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM

A 0.047(max) 1.20(max) A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05

b 0.014(typ.) 0.35(typ.) c 0.005(typ.) 0.127(typ.)

D 0.725±0.004 18.41±0.10

E 0.463±0.008 11.76±0.20

E1 0.400±0.004 10.16±0.10

L1' 0.031 0.80

L' 0.020±0.004 0.500±0.10

y 0.004(max) 0.10(max)

θ

0°~5° 0°~5°

Taiwan Memory Technology, Inc. reserves the right P. 14 Publication Date: MAR. 2001 to change products or specifications without notice. Revision:B