Datasheet T221160A-30J, T221160A-35S, T221160A-35J, T221160A-30S Datasheet (Taiwan Memory Technology)

tm

TE

CH

T221160A

DRAM

FEATURES

High speed access time : 25/30/35/40 ns

•

Industry-standard x 16 pinouts and tim ing

•

functions.

Single 5V (±10%) power supply.

•

All device pins are TTL- compatible.

•

256-cycle refresh in 4ms.

•

Refresh modes:

•

RAS

(CBR) and HIDDEN.

Conventional FAST PAGE MODE access cycle.

•

BYTE WRITE and BYTE READ access cycles.

•

RAS

only,

CAS

BEFORE

PART NUMBER EXAMPLES

PART NUMBER

T221160A-30J T221160A-30S

T221160A-35J T221160A-35S

ACCESS TIME PACKAGE

30ns SOJ 30ns TSOP-II

35ns SOJ 35ns TSOP-II

64K x 16 DYNAMIC RAM

FAST PAGE MODE

PIN ASSIGNMENT ( Top View )

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vss I/016 I/015 I/014 I/013 Vss I/012 I/011 I/010 I/09 NC CASL CASH OE NC A7 A6 A5 A4 VSS

Vc c I/01 I/02 I/03 I/04 Vc c I/05 I/06 I/07 I/08

NC NC

W E

R A S

NC

A0 A1 A2 A3

Vc c

10 11 12 13 14 15 16 17 18 19 20

1 2 3 4 5 6 7 8 9

SOJ

GENERAL DESCRIPTION

The T221160A is a randomly accessed solid state memory containing 1,048,551 bits organized in a x16 configuration. The T221160A has both BYTE WRITE and WORD WRITE access cycles via two

CAS

pins. It offers Fast Page mode operation

CAS

The T221160A determined by the first by the last to transition back high. Use only one of

CAS

the two

and leave the other staying high

during WRITE will result in a BYTE WRITE.

CASL

transiting low in a WRITE cycle will write data into the lower byte (IO1~IO8), and transiting low will write data into the upper byte (IO9~16).

function and timing are

CAS

to transition low and

CASH

Vcc I/01 I/02 I/03 I/04 Vcc I/05 I/06 I/07 I/08

NC NC

W E

RA S

NC A0 A1 A2 A3

Vcc

1 2 3 4 5 6 7 8 9

10

TSO P (II)

11 12 13 14 15 16 17 18 19 20

40

Vss

39

I/016

38

I/015

37

I/014

36

I/013

35

Vss

34

I/012

33

I/011

32

I/010

31

I/09

30

NC

29

CASL CASH

28

OE

27 26

NC

25

A7

24

A6

23

A5

22

A4

21

VSS

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FUNCTIONAL BLOCK DIAGRAM

CH

T221160A

WE

RAS

A0 A1 A2 A3 A4 A5 A6 A7

CASL CASH

NO.2 CLOCK

GENERATOR

COLUMN.

ADDRESS

8

REFRESH

CONTROLLER

REFRESH

COUNTER

ADDRESS

8

BUFFERS(8)

NO.1 CLOCK

GENERATOR

BUFFER

8

ROW.

CAS

CONTROL

LOGIC

8

DATA-IN BUFFER

DQ01

OE

Vcc

Vss

. .

DQ16

16

DATA-

OUT

BUFFER

COLUMN

8

DECODER

256

SENSE AMPLIFIERS

256

ROW

DECODER

8

VO GATING

256 x 16

256 x 256 x 16

MEMORY

ARRA

Y

8

16

PIN DESCRIPTIONS

PIN NO. SYM. TYPE DESCRIPTION

16~19,22~25 A0-A7 Input Address Input

14 28 29 13 27

2~5,6~10,31~34,36~39 I/O1 - I/O16 Input/ Output Data Input/ Output

1,6,20 Vcc Supply Power, 5V

21,35,40 Vss Ground Ground

11,12,15,30 NC - No Connect

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RAS CASH CASL

WE

OE

Input Row Address Strobe Input Column Address Strobe /Upper Byte Control Input Column Address Strobe /Lower Byte Control Input Write Enable Input Output Enable

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ABSOLUTE MAXIMUM RATINGS*

Voltage on Any pin Relative to VSS… … -1V to 7V Operating Temperature, Ta (ambient)..0°C to +70°C

Storage Temperature (plastic)….... -55°C to +150°C

Power Dissipation ...............................…......... 1.0W

Short Circuit Output Current...................….... 50mA

*Stresses greater than those listed under "Absolute Maxi mum Rat ings" ma y caus e per manent damag e

DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS

(0°C ≤ Ta ≤ 70°C; VCC = 5V ± 10 % unless otherwise noted)

DESCRIPTION CONDITIONS SYM. MIN MAX UNITS NOTES

Supply Voltage Vcc 4.5 5.5 V 1 Supply Voltage Vss 0 0 V Input High (Logic) voltage VIH 2.4 Vcc+1 V 1 Input Low (Logic) voltage VIL -1.0 0.8 V 1 Input Leakage Current

Output Leakage Current Output High Voltage IOH = -5 mA VOH 2.4 - V

Output Low Voltage IOL = 4.2 mA VOL - 0.4 V

CH

T221160A

to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

0V ≤ VIN ≤ 7V 0V ≤ V

Output(s) disabled

OUT

≤ 7V

ILI -10 10 uA

ILO -10 10 uA

Note: 1.All Voltages referenced to Vss

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DC CHARACTERISTICS

(Ta = 0 to 70°C, Vcc = 5V ±10%, Vss = 0V)

CH

T221160A

Parameter

Operating Current

Standby Current

Fast Page Mode Current

RAS

-only refresh

Current

CAS

Before

Refresh Current

RAS

-25 -30 -35 -40

Symbol

Min Max Min Max Min Max Min Max

Icc1 - 170 - 150 - 130 - 120 mA

Icc2 - 4 - 4 - 4 - 4 mA

Icc3 - 2 - 2 - 2 - 2 mA

Icc4 -

Icc5 -

Icc6 -

170

-

150

-

150

-

150

-

130

-

130

-

130

-

120

Unit

mA

Test Condition

RAS, CAS

tRC=min TTL interface,

RAS,CAS

D

OUT

CMOS interface,

RAS, CAS RAS

=VIL,

cycling, tPC= min

CAS

=VIH,

cycling, tRC= min

RAS,CAS

tRC= min

cycling

=VIH,

=High-Z

> Vcc-0.2V

CAS

RAS

cycling,

Note: Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition, Icc is specified as an average current.

CAPACITANCE

(Ta =25°C, Vcc =5V, f = 1M HZ)

Parameter Symbol Typ Max Unit

Input Capacitance

(address)

Input Capacitance

RAS,CAS,WE,OE

(

Output Capacitance

(data-in/out)

)

CI1 - 5 pF

CI2 - 7 pF

C

- 10 pF

I/O

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T221160A

AC CHARACTERISTICS

(note 1,2,3) (Ta = 0 to 70°C)

AC TEST CONDITIONS: Vcc=5V ±10%, input pulse level = 0 to 3V Input rise and fall times: 2ns Output Load: 2TTL gate + CL (50pF)

PARAMETER

SYM

-25 -30 -35 -40 AC CHARACTERISTICS

MIN MAX MIN MAX MIN MAX MIN MAX

Read or Write Cycle Time tRC 43 55 65 75 ns Read-Modify-Write Cycle Time t

65 85 95 105 ns

RWC

Fast-Page-Mode Read or Write Cycle Time tPC 15 20 23 25 ns Fast-Page-Mode Read-Write Cycle Time t

Access Time From Access Time From Access Time From

RAS CAS OE

37 42 49 52 ns

PCM

t

25 30 35 40

RAC

t

7 8 9 10

CAC

t

7 8 9 10

OAC

Access Time From Column Address tAA 12 16 18 20 ns

t

CAS

Access Time From

RAS

Pulse Width

RAS

Pulse Width

RAS

Hold Time

RAS

Precharge Time

CAS

Pulse Width

CAS

Hold Time

CAS

Precharge Time RAS CAS

to

CAS

Delay Time

RAS

Precharge Time

Precharge

Row Address Setup Time t Row Address Hold Time t

RAS

to Column Address Delay Time

Column Address Setup Time t Column Address Hold Time t Column Address Hold Time (Reference to

RAS

)

RAS

Column Address to

Lead Time

Read Command Setup Time t

CAS RAS

or

Read Command Hold Time Reference to Read Command Hold Time Reference to

CAS

to Output in Low-Z

Output Buffer Turn-off Delay From

RAS

CAS

14 18 20 22

ACP

t

25 10K 30 10K 35 10K 40 10K

RAS

t

RASC

t

7 8 9 10

RSH

25

100K

30

100K

35

100K

40

tRP 15 20 23 25 t

4 10K 6 10K 8 10K 10 10K

CAS

t

21 26 30 35

CSH

3 3 4 5

tCP t

10 17 10 21 10 25 10 29

RCD

t

3 3 3 5

CRP

0 0 0 0 ns

ASR

5 5 5 5 ns

RAH

t

8 13 8 14 8 16 8 18

RAD

0 0 0 0 ns

ASC

4 4 4 5 ns

CAH

tAR 22 26 30 34 t

12 14 16 18

RAL

0 0 0 0 ns

RCS

t

0 0 0 0

RCH

t

0 0 0 0

RRH

t

3 3 3 3

CLZ

t

3 15 3 15 3 15 3 15

OFF1

100K

UNIT

ns ns ns

ns ns ns ns ns ns ns ns ns ns

ns

ns ns

Notes

4 5 13 8

7

8

14 9,14

9

10,16

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T221160A

AC CHARACTERISTICS

PARAMETER

Output Buffer Turn-off OE to Write Command Setup Time

Write Command Hold Time Write Command Hold Time (Reference

RAS

to Write Command Pulse Width tWP 4 4 4 6

Write Command to Write Command to

Data-in Setup Time tDS 0 0 0 0 Data-in Hold Time tDH 4 4 4 5

Data-in Hold Time (Reference to

RAS

Column Address to

CAS

Transition Time (rise or fall) tT 1.5 50 1.5 50 2.5 50 2.5 50 Refresh Period (256 cycles) t

RAS CAS CAS OE

Modify-Write Cycle

OE

Refresh Cycle

)

RAS CAS

WE

to

to Setup Time (CBR REFRESH) Hold Time (CBR REFRESH)

Hold Time From

Setup Prior to

Delay Time

WE

Delay Time

CAS

Precharge Time

WE

RAS

Lead Time Lead Time

Delay Time

WE

During Read-

During Hidden

(continued)

RAS

-25 -30 -35 -40

SYM

t

OFF2

t

WCS

t

WCH

t

WCR

t

RWL

t

CWL

t

)

DHR

t

RWD

t

AWD

t

CWD

REF

t

RPC

t

CSR

t

CHR

t

OEH

t

ORD

MIN MAX MIN MAX MIN MAX MIN MAX

- 6 - 8 - 8 - 8

0 0 0 0

4 4 4 6

22 26 30 34

5 6 7 9 5 6 7 8

22 26 30 34

34 46 51 56 21 29 31 35

17 24 25 27

4 4 4 4 10 10 10 10 5 10 10 10

7 10 10 10 4 4 4 5

0 0 0 0

UNIT

ns ns ns ns

ns ns ns ns ns ns ns ns ns ns

ms

ns ns ns ns

ns

Notes

16 11,14

14

14 14 14 12 12

11 11 11 2,3

6 6 15

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Notes:

1. An initial pause of 200us is required after power-up followed by eight cycles ( device operation is assured. The eight cycle wake-ups should be repeated any time the t

2. VIH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between V

IH(2.4V)

3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner.

4. Assume that t greater than the maximum recommended value shown in this table, t amount that t

5. Assume that t

6. Enables on-chip refresh and address counters.

7. Operation within the t that t specified as a reference point only; if t greater than the specified t access time is controlled by t

8. Operation within the t t

RAC

specified as a reference point only; if t greater than the specified t access time is controlled by tAA.

9. Either t READ cycle.

10. t

OFF1

output achieves the open circuit condition; it is not a reference to V

CH

T221160A

RAS

refresh

RAS

only or CBR) before proper

RAS

refresh requirement is exceeded.

REF

and V

IL(0.8V)

< t

RCD

exceeds the value shown.

RCD

≥

RCD

(max) can be met. t

RAC

(max) can be met. t

or t

RCH

(max) defines the time at which the

RRH

.

(max). If t

RCD

will increase by the

RAC

t

(max) .

RCD

(max) limit ensures

RCD

CAC

limit ensures that

RAD

must be satisfied for a

or VOL.

OH

RCD

(max) is

RCD

(max) limit,

.

(max) is

RAD

(max) limit,

is

11. t

12. These parameters are referenced to

13. During a READ cycle, if

14. WRITE command is defined as

15. LATE WRITE and READ-MODIFY-WRITE

16. The I/Os open during READ cycles once

, t

WCS

restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycles only. If t EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If t t

(min) and t

AWD cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until

RAS

or OE go back to VIH) is indeterminate.

OE

held high and goes low result in a LATE WRITE ( controlled) cycle.

leading edge in EARLY WRITE cycles and

WE

leading edge in LATE WRITE or READ-

MODIFY-WRITE cycles.

taken HIGH before open, if WRITE or READ-MODIFY-WRITE operation is not possible.

low.

cycles must have both t

OE

( ensure that the output buffers will be open during the WRITE cycles.

t

OFF1

OE

high during WRITE cycle) in order to

or t

, t

RWD

t

≥

WCS

RWD

is tied permanently low, a LATE

occur.

OFF2

and t

AWD

(min), the cycle is an

WCS

t

≥

CWD

WE

CAS

(min), t

RWD

t

≥

CWD

taken low after

OE

is low then

goes high, I/O goes

and t

OFF2

CWD

AWD

(min), the

CAS

WE

OEH

are

≥

and

CAS

OE

-

CAS

going

met

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Publication Date: FEB. 2002

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V

RAS

V

CAS

V

WE

I/O

OE

RAS

WE

I/O

OE

V V

V

IOH

V

IOL

V

V V

ADDR

IH IL

IH

IH IL

IH

IOH

IOL

IH

TE

CH

T221160A

READ CYCLE

t

RC

t

RAS

t

t t

RAL

CAH

t t

t

RAC CAC

CLZ

AA

CSH RSH

t

CAS

VAILD DATA

t

OAC

t

CRP

ASR

t t

RAD RAH

t

RCD

t

AR

t

ASC

COLUMNROW ROW

t

RCS

EARLY WRITE CYCLE

t

RC

t

RAS

t

CSH

t

RSH

t

t t

t

DHR

DH

t

CAS

t

RAL

t

CSH

CWL RWL

WCR

WCH

t

WP

t

CRP

IL

t

ASR

IL

t t

RAD RAH

t

RCD

t

AR

t

ASC

COLUMNROW ROW

t

WCS

t

DS

VAILD DATA

t

OFF2

t

RP

t

CRP

t

RRH

t

RCH

NOTE1

t

OFF1

OPENOPEN

t

RP

t

CRP

DON'T CARE

UNDEFINED

Note: t

is referenced from the rising edge of

OFF1

RAS

or

, whichever occurs last.

CAS

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V

RAS

V

WE

I/O

OE

RAS

CAS

V V

V V IL

V V

V V IL

CAS

ADDR

IH IL

IOH

IOL

IH IL

IH

IH IL

IH

TE

CH

T221160A

READ WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE CYCLES)

t

RWC

t

RAS

t

CSH

t

RSH

t

CRP

t

AR

t

ASR

RAD

t

RAH

t

RCD

t

ASC

t

RCS

t

CAS

t

RAL

t

CAH

t

RWD

t

CWD

t

AWD

t

AA

t

RAC

t

CAC

t

CLZ

VAILD D

OUT

t

OAC

t

OFF2

FAST-PAGE-MODE READ CYCLE

t

RASC

t

CRP

t

ASRtRAHtASC

RAD

t

RCD

AR

CSH

t

CAH

t

CAS

ROW COLUMN COLUMN COLUMN ROW

t

RCS

t

PC

t

CP

t

ASCtCAH

t

CAS

t

CP

t

ASC

t

DS

t

VAILD D

CAH

t

RAL

t

CWL

t

RWL

t

RSH

t

CAS

WP

t

DH

IN

t

OEH

t

RCH

t

RP

t

CRP

ROWCOLUMNROW

t

RP

t

CRP

t

CPN

t

RRH

IH

WE

I/O

OE

V V

V

IO H

V IO L

V V IL

t

CLZ

t

AA

t

ACP

t

CAC

t

OAC

t

OFF1

VAILD

DATA

t

OFF2

t

CLZ

AA

t

RAC

t

CAC

t

OAC

t

VAILD

DATA

OFF1

t

OFF2

IL

OPEN OPEN

IH

t

CLZ

t

AA

t

ACP

t

CAC

t

OAC

VAILD

DATA

t

OFF2

t

OFF1

DON'T CARE

UNDEFINED

Note: 1. t

2. t

is referenced from the rising edge of RAS or CAS , whichever occurs last.

OFF1

can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of

PC

CAS to rising edge of CAS . Both measurements must meet the t

specification.

PC

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T221160A

CAS

ADDR

CAS

ADDR

RAS

WE

I/O

OE

RAS

WE

I/O

OE

FAST-PAGE-MODE EARLY-WRITE CYCLE

t

RASC

IH

V

IL

V

t

CRP

IH

V

IL

V

t

ASRtRAH

IH

V

IL

V

IH

V

IL

V

IOH

V

IOL

V

IH

V

IL

V

ROW COLUMN COLUMN COLUMN ROW

RAD

t

CSH

t

RCD

t

AR

t

ASC

t

WCS

t

DS

t

CAS,tCLCH

t

CAH

t

CWL

t

WCH

t

WP

t

WCR

t

DHR

t

DH

t

CP

t

ASCtCAH

t

WCS

t

DS

t

PC

t

CAS,tCLCH

t

CWL

t

WCH

t

WP

t

DH

VALID DATA VALID DATA VALID DATA

t

CAH

t

CAS,tCLCH

RAL

t

CWL

t

WCH

t

WP

t

RWL

t

DH

RSH

t

CP

t

ASC

t

WCS

t

DS

t

RP

t

CRP

t

CPN

FAST-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE CYCLES)

t

RASC

IH

V

IL

V

t

CRP

IH

V

IL

V

t

ASRtRAH

IH

V

IL

V

IH

V

IL

IOH

V

IOL

V

IH

V

IL

ROW COLUMN COLUMN COLUMN ROW

t

AR

RAD

t

RCD

t

RAC

t

CSH

t

CAS,tCLCH

t

ASC

t

RCS

t

AA

t

CAC

t

CLZ

t

AWD

OAC

t

CAH

t

CWL

RWD

t t

WP CWD

t

DH

t

DS

VAILD D OUT

t

CAC

t

CLZ

VAILD

D IN

t

OFF2

t

OAC

t

CP

t

ASCtCAH

t

AWD

t

AA

t

ACP

t

PCM

t

CAS,tCLCH

t

CWL

t

WP

t

CWD

t

DS

VAILD D OUT

t

CP

t

ASC

t

OFF2

t t

CAC

CLZ

AA

t

ACP

t

OAC

t

DH

VAILD

D IN

t

CAS,tCLCH

t

RAL

t

CAH

t

CWD

RSH

t

DH

t

DS

VAILD

D OUT

D IN

DON'T CARE

t t

OFF2 OEH

t

RP

t

CRP

t

CPN

t

RWL

t

CWL

t

WP

UNDEFINED

CAS

Note:

can be measured from falling edge to falling edge of

t

PC

CAS

. Both measurements must meet the t

specification.

PC

, or from rising edge to rising edge of

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V

RAS

V

WE

I/O

V V

V

IO H

V

IO L

CAS

ADDR

IH

IL

IH

IL

IH

IL

IH

IL

TE

CH

T221160A

FAST-PAGE-MODE READ-EARLY-WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

t

CSH

t

CRP

t

ASRtRAH

ROW COLUMN COLUMN COLUMN ROW

t

RAD

t

OPE

t

AR

RCD

N

t

ASC

t

RAC

t

RCS

t

CAS

t

CAH

t

AA

t

CAC

t

OAC

t

PC

t

OFF1

VAILD

DATA(A)

t

RASC

t

CP

t

ASCtCAH

t

ACP

t

CAC

t

CLZ

t

RCH

AA

t

CAS

t

PC

t

OFF1

VAILD

DATA(B)

t

WCS

t

CP

t

ASC

t

DS

VAILD

D A T A IN

t

DH

t

CAH

t

WCH

RAL

t

RSH

t

CAS

t

RP

t

CRP

t

CP

OE

RAS

CAS

ADDR

I/O

V

IH

V

IL

ONLY REFRESH CYCLE

RAS

(ADDR=A0-A7 ;

IH

V V

IL

t

CRP

IH

V

IL

V

t

ASR

IH

V

IL

V

OH

V V

OL

t

RAH

ROW ROW

t

OFF

t

RAS

OE,WE

=DON‘T CARE)

t

RC

t

RPC

OPEN

t

RP

DON'T CARE

UNDEFINED

Note1:Do not drive data prior to tristate.

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IH

V

RAS

CAS

IL

V

IH

V

IL

V

TE

CH

T221160A

CBR REFRESH CYCLE

t

CPN

t

OFF

t

RPC

(A0-A7 ;

t

RP

t

CSR

t

CHR

t

RAS

=DON‘T CARE)

OE

t

RC

t

RPC

t

RP

t

CSR

t

CHR

t

RAS

WE

CAS

ADDR

I/O

RAS

I/O

OE

OPEN

IH

V

IL

V

HIDDEN REFRESH CYCLE

=HIGH ;

(

WE

(R EA D )

t

RC

t

RAS

V

IH

V

IL

t

RAH

t

RAD

t

RCD

t

AR

t

ASCtCAH

t

RAC

t

CRP

IH

V V

IL

t

ASR

IH

V V

IL

V

IO H

V

IO L

V

IH

V

IL

ROW COLUM N

t

RAL

t

OE

t

CAC

CLZ

RSH

AA

=LOW)

t

OAC

t

ORD

(R EF R E SH )

t

RP

VAILD DATA

t

RAS

t

CHR

RC

t

OFF2

t

RP

NOTE1

t

OFF1

OPENOPEN

DON'T CARE

UNDEFINED

Note: 1. t

is referenced from the rising edge of

OFF1

RAS

or

, whichever occurs last.

CAS

Taiwan Memory Technology, Inc. reserves the right P. 12 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A

TE

tm

PACKAGE DIMENSIONS 40-LEAD SOJ DRAM (400 mil)

B

CH

T221160A

A

2140

1

D

F

C

Seating

Plane

y

10¢X(MAX

E

20

G

K

L

J

)

SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM

A 1.025±0.010 26.035±0.254

B 0.400±0.005 10.160±0.127 C 0.045(MAX) 1.143(MAX)

D 0.050±0.006 1.27±0.152

E 0.019±0.003 0.483±0.08

F 0.026±0.003 0.661±0.080 G 0.440±0.010 11.176±0.254 H 0.011±0.003 0.280±0.080

I 0.025(MIN) 0.635(MIN)

J 0.364±0.020 9.246±0.508

K 0.047±0.006 1.194±0.152

L 0.150(MAX) 3.810(MAX)

y 0.004(MAX) 0.102(MAX)

H

I

Taiwan Memory Technology, Inc. reserves the right P. 13 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A

TE

tm

PACKAGE DIMENSIONS 40-LEAD TSOP II DRAM (400 mil)

EE1

CH

T221160A

D

120

2140

be

y

SEATING PLANE

A

A2 A1

SYMBOL DIMENSIONS IN INCHES DIMENSIONS IN MM

A 0.047(max) 1.20(max)

A1 0.004±0.002 0.10±0.05 A2 0.039±0.002 1.00±0.05

b 0.014(typ.) 0.35(typ.) e 0.0315(typ.) 0.80typ.)

D 0.725±0.004 18.41±0.10

E 0.463±0.008 11.76±0.20

E1 0.400±0.004 10.16±0.10 L1 0.031 0.80

L 0.020±0.004 0.500±0.10

y 0.004(max) 0.10(max)

θ

0°~5° 0°~5°

L

L1

θ

Taiwan Memory Technology, Inc. reserves the right P. 14 Publication Date: FEB. 2002 to change products or specifications without notice. Revision:A

Datasheet T221160A-30J, T221160A-35S, T221160A-35J, T221160A-30S Datasheet (Taiwan Memory Technology)

Specifications and Main Features

Frequently Asked Questions

User Manual

DRAM

FAST PAGE MODE

GENERAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS*

DC CHARACTERISTICS