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6-BIT 2:1
MUX-LATCH
SY10E155
SY100E155
FEATURES
■ 750ps max. LEN to output
■ Extended 100E VEE range of –4.2V to –5.5V
■ 700ps max. D to output
■ Single-ended outputs
■ Asynchronous Master Reset
■ Dual latch-enables
■ Fully compatible with industry standard 10KH,
100K ECL levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E155
■ Available in 28-pin PLCC package
BLOCK DIAGRAM
D
0a
MUX
D
0b
D
1a
SEL
MUX
D
1b
D
2a
SEL
MUX
D
2b
SEL
Q
D
E
N
R
Q
D
E
N
R
Q
D
E
N
R
Q
0
Q
1
Q
2
DESCRIPTION
The SY10/100E155 offer six 2:1 multiplexers followed
by latches with single-ended outputs, designed for use in
new, high-performance ECL systems. The two external
latch-enable signals (LEN1 and LEN2) are gated through a
logical OR operation before use as control for the six
latches. When both LEN1 and LEN2 are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN1 or LEN2 (or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL (Select)
signal which selects one of the two bits of input data at each
mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
PIN CONFIGURATION
5a
D
LEN
LEN
V
MR
SEL
D
EE
4b
D
D
25 24 23 22 21 20 19
5b
26
1
27
2
28
1
2
3
0b
4
TOP VIEW
567891011
4a
D3bD
PLCC
J28-1
3a
CCO
NC
D
V
18
Q
5
17
Q
4
16
V
CC
Q
Q
V
Q
3
2
CCO
1
15
14
13
12
D
D
D
D
D
D
SEL
LEN
LEN
MR
Q
3a
MUX
3b
4a
SEL
MUX
4b
5a
SEL
MUX
5b
SEL
Q
D
E
N
R
Q
D
E
N
R
Q
D
E
N
R
3
Q
4
1a
1b
0b
D
D
D2aD
0
2b
Q
D
CCO
V
PIN NAMES
Q
5
Pin Function
D0a–D5a Input Data a
D0b–D5b Input Data b
SEL Data Select Input
1
2
LEN1, LEN2 Latch Enables
MR Master Reset
Q0–Q5 Outputs
CCO VCC to Output
V
Rev.: C Amendment: /1
1
Issue Date: February, 1998
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Micrel
TRUTH TABLES
SY10E155
SY100E155
SEL Data
Ha
Lb
LEN1 LEN2 Latch
L L Transparent
H X Latched
X H Latched
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
IIH Input HIGH Current ——150 ——150 ——150 µA —
EE Power Supply Current mA —
I
10E — 85 102 — 85 102 — 85 102
100E — 85 102 — 85 102 — 98 117
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
PLH Propagation Delay to Output ps —
t
tPHL D 325 500 700 325 500 700 325 500 700
SEL 475 675 925 475 675 925 475 675 925
LEN 350 500 750 350 500 750 350 500 750
MR 450 600 850 450 600 850 450 600 850
S Set-up Time ps —
t
D 300 100 — 300 100 — 300 100 —
SEL 500 250 — 500 250 — 500 250 —
t
H Hold Time ps —
D300–100 — 300 –100 — 300 –100 —
SEL 0 –250 — 0 –250 — 0 –250 —
tRR Reset Recovery Time 800 650 — 800 650 — 800 650 — ps —
tPW Minimum Pulse Width, MR 400 ——400 ——400 ——ps —
tskew Within-Device Skew — 75 ——75 ——75 — ps 1
r Rise/Fall Time 300 450 800 300 450 800 300 450 800 ps —
t
tf 20% to 80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths through a device.
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E155JC J28-1 Commercial
SY10E155JCTR J28-1 Commercial
SY100E155JC J28-1 Commercial
SY100E155JCTR J28-1 Commercial
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Micrel
28 LEAD PLCC (J28-1)
SY10E155
SY100E155
Rev. 03
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Micrel
SY10E155
SY100E155
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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