Page 1
QUINT
D
2d
D2cD
1c
V
EE
D2bD
1b
D
1a
O
a
O
a
O
b
O
b
D
1e
O
d
O
e
17
16
15
14
13
1
2
3
4
5
6
7248239221021112012
19
Top View
Flatpack
F24-1
V
CC
V
CCA
F
O
c
O
d
O
c
AND/NAND GATE
SY100S304
FEATURES
■ Max. propagation delay of 1050ps
■ IEE min. of –60mA
■ Extended supply voltage option:
VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved
noise immunity
■ Internal 75KΩ input pull-down resistors
■ 40% faster than Fairchild 300K at lower power
■ Function and pinout compatible with Fairchild F100K
■ Available in 24-pin CERPACK and 28-pin PLCC
packages
BLOCK DIAGRAM
F
O
D
1a
a
DESCRIPTION
The SY100S304 is an ultra-fast quint AND/NAND gate
designed for use in high-performance ECL systems. This
device also features a Function (F) output which is the wireNOR of the AND gate outputs. The inputs on the device
have 75KΩ pull-down resistors.
PIN CONFIGURATIONS
D2a
D1a
Oa
OaObOb
VEES
5
6
D1b
D2b
VEE
VEES
D1c
D2c
12
13
14
15
16
17
Top View
PLCC
J28-1
1911201021922823724
D2e
D1d
D1e
VEES
25
Oe
Oe
Oc
4
3
Oc
VCCA
2
1
VCC
28
CC
V
27
F
2618
Od
dD2d
O
D
2a
D
1b
D
2b
D
1c
D
2c
D
1d
D
2d
D
1e
D
2e
O
a
18
D
D
1d
O
b
D
O
b
O
c
O
c
O
d
O
d
O
e
O
e
2e
O
e
2a
PIN NAMES
Pin Function
Dna – Dne Data Inputs (n-1...5)
E Enable Input
Oa – Oe Data Outputs
Oa – Oe Complementary Data Outputs
VEES VEE Substrate
CCA VCCO for ECL Outputs
V
Rev.: G Amendment: /0
1
Issue Date: July, 1999
Page 2
Micrel
SY100S304
DC ELECTRICAL CHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
Symbol Parameter Min. Typ. Max. Unit Condition
IH Input HIGH Current µAVIN = VIH (Max.)
I
2a — D2e ——250
D
D1a — D1e ——250
I
EE Power Supply Current –60 –40 –30 mA Inputs Open
AC ELECTRICAL CHARACTERISTICS
CERPACK
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
A = 0°CTA = +25°CTA = +85°C
T
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
PLH Propagation Delay 300 1150 300 1150 300 1150 ps
t
tPHL Dna — Dne to O, O
PLH Propagation Delay 600 1650 600 1650 600 1650 ps
t
tPHL Data to F
t
TLH Transition Time 300 900 300 900 300 900 ps
tTHL 20% to 80%, 80% to 20%
PLCC
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Condition
PLH Propagation Delay 300 1050 300 1050 300 1050 ps
t
tPHL Dna — Dne to O, O
PLH Propagation Delay 600 1550 600 1550 600 1550 ps
t
tPHL Data to F
TLH Transition Time 300 900 300 900 300 900 ps
t
tTHL 20% to 80%, 80% to 20%
2
Page 3
Micrel
TIMING DIAGRAM
SY100S304
INPUT
t
TRUE
OUTPUT
COMPLEMENT
NOTE:
VEE = –4.2V to –5.5V unless otherwise specified, VCC = VCCA = GND
PHL
t
PLH
t
TLH
Propagation Delay and Transition Times
20%
50%
80%
0.7 ± 0.1 ns0.7 ± 0.1 ns
50%
80%
50%
t
PLH
t
PHL
20%
t
–0.95V
–1.69V
THL
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY100S304FC F24-1 Commercial
SY100S304JC J28-1 Commercial
SY100S304JCTR J28-1 Commercial
3
Page 4
Micrel
24 LEAD CERPACK (F24-1)
SY100S304
Rev. 03
4
Page 5
Micrel
28 LEAD PLCC (J28-1)
SY100S304
Rev. 03
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
5
Loading...