The SY10/100EL52 are differential data, differential
clock D flip-flops. These devices are functionally
equivalent to the E452 devices, with higher performance
capabilities. With propagation delays and output transition
times significantly faster than the E452, the EL52 is ideally
suited for those applications which require the ultimate
in AC performance.
Data enters the master portion of the flip-flop when
the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock.
The differential clock inputs also allow the EL52 to be
used as a negative edge triggered device.
The EL52 employs input clamping circuitry so that,
under open input conditions (pulled down to VEE), the
outputs of the device will remain stable.
CLK (100EL)–0.8—
trOutput Rise/Fall Times Q 100225350100225350100225350100225350ps
tf(20% to 80%)
(1)
150——150——150——150——mV
(2)
(3)
(3)
–0.6—
–0.8—
(3)
(3)
–0.6—
–0.8—
(3)
(3)
–0.6—
–0.8—
(3)
(3)
V
NOTES:
1. Minimum input swing for which AC parameters are guaranteed.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified
range and the peak-to-peak voltage lies between VPP min. and 1V.
3. The lower end of the CMR range is dependent on VEE and is equal to VEE + 3.0V.
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