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3-BIT 4:1
MUX-LATCH
SY10E156
SY100E156
FEATURES
■ 900ps max. D to output
■ Extended 100E VEE range of –4.2V to –5.5V
■ 800ps max. LEN to output
■ Differential outputs
■ Asynchronous Master Reset
■ Dual latch enables
■ Fully compatible with industry standard 10KH,
100K ECL levels
■ Internal 75KΩ input pulldown resistors
■ Fully compatible with Motorola MC10E/100E156
■ Available in 28-pin PLCC package
BLOCK DIAGRAM
D
0a
D
0b
D
0c
D
0d
D
1a
D
1b
D
1c
D
1d
4:1
MUX
4:1
MUX
D
E
N
R
D
E
N
R
Q
Q
Q
Q
DESCRIPTION
The SY10/100E156 offer three 4:1 multiplexers followed
by latches with differential outputs, designed for use in
new, high-performance ECL systems. The two external
latch enable signals (LEN
1 and LEN2) are gated through a
logical OR operation before use as control for the three
latches. When both LEN1 and LEN2 are at a logic LOW, the
latches are transparent, thus presenting the data from the
multiplexers at the output pins. If either LEN1 or LEN2 (or
both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the Select
(SEL0, SEL1) signals which select one of the four bits of
input data at each mux to be passed through.
The MR (Master Reset) signal operates asynchronously
to take all outputs to a logic LOW.
PIN CONFIGURATION
1b
1a
2d
D
0
0
SEL
0
26
SEL
1
27
MR
1
V
LEN
1
LEN
D
EE
28
1
1
2
2
3
1c
4
D
25 24 23 22 21 20 19
PLCC
TOP VIEW
J28-1
567891011
2a
2b
CCO
D
D
D2cD
V
18
Q
2
17
Q
2
16
V
CC
Q
Q
V
Q
1
1
CCO
0
15
14
13
12
D
D
D
D
SEL
SEL
LEN
LEN
MR
2a
2b
2c
2d
0
1
1
2
4:1
MUX
D
E
N
R
Q
2
Q
2
PIN NAMES
Pin Function
D0x–D2x Input Data
1d
D
0c
0a
0b
D
D
D
0
0d
Q
D
CCO
V
SEL0, SEL1 Select Inputs
LEN1, LEN2 Latch Enables
MR Master Reset
Q0–Q2 True Outputs
Q0–Q2 Inverted Outputs
CCO VCC to Output
V
Rev.: C Amendment: /1
1
Issue Date: February, 1998
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Micrel
TRUTH TABLES
SY10E156
SY100E156
LEN1 LEN2 Latch
L L Transparent
H X Latched
X H Latched
SEL0 SEL1 Data
LL a
HL b
LH c
HH d
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
IIH Input HIGH Current ——150 ——150 ——150 µA —
EE Power Supply Current mA —
I
10E — 75 90 — 75 90 — 75 90
100E — 75 90 — 75 90 — 86 103
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = 0°CTA = +25°CTA = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Condition
PLH Propagation Delay to Output ps —
t
tPHL D 400 600 900 400 600 900 400 600 900
SEL0 550 775 1050 550 775 1050 550 775 1050
SEL1 450 650 900 450 650 900 450 650 900
LEN 350 500 800 350 500 800 350 500 800
MR 350 600 825 350 600 825 350 600 825
t
S Set-up Time ps —
D 400 275 — 400 275 — 400 275 —
SEL0 700 300 — 700 300 — 700 300 —
SEL1 600 400 — 600 400 — 600 400 —
tH Hold Time ps —
D300–275 — 300 –275 — 300 –275 —
SEL0 100 –300 — 100 –300 — 100 –300 —
SEL1 200 –400 — 200 –400 — 200 –400 —
tRR Reset Recovery Time 800 600 — 800 600 — 800 600 — ps —
tPW Minimum Pulse Width, MR 400 ——400 ——400 ——ps —
tskew Within-Device Skew — 50 ——50 ——50 — ps 1
t
r Rise/Fall Time 275 475 700 275 475 700 275 475 700 ps —
tf 20% to 80%
NOTE:
1. Within-device skew is defined as identical transitions on similar paths
through a device.
PRODUCT ORDERING CODE
Ordering Package Operating
Code Type Range
SY10E156JC J28-1 Commercial
SY10E156JCTR J28-1 Commercial
SY100E156JC J28-1 Commercial
SY100E156JCTR J28-1 Commercial
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Micrel
28 LEAD PLCC (J28-1)
SY10E156
SY100E156
Rev. 03
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Micrel
SY10E156
SY100E156
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
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