Page 1
STW80NF55-08
N-CHANNEL 55V - 0.0065Ω - 80A TO-247
STripFET™ POWER MOSFET
TYPE V
DSS
R
DS(on)
I
D
STW80NF55-08 55 V < 0.008 Ω 80 A
■ TYPICAL R
■ EXCEPTIONA L dv/dt CAPABILI TY
■ 100% AVALANCHE TESTED
■ LOW THRESHOLD DRIVE
(on) = 0.0065Ω
DS
DESCRIPTION
This Power MOSFET is t he latest development of
STMicroelectronics unique "Single Feature Size™"
strip-based process. The resulting transistor shows
extremely high packing density for low on-resistance, rugged avalanche charac teristics and less
critical alignment steps therefore a remarkable
manufacturing reproducibility.
APPLICATIONS
■ DC-AC & DC-DC CONVERTERS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SOLENOID AND RELAY DRIVERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
3
2
1
TO-247
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
(*) Drain Current (continuous) at TC = 25°C
D
I
D
I
DM
P
TOT
E
AS
T
stg
T
j
(●) Pulse width limited by safe operating area
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
55 V
55 V
Gate- source Voltage ±20 V
80 A
Drain Current (continuous) at TC = 100°C
(l)
Drain Current (pulsed) 320 A
Total Dissipation at TC = 25°C
80 A
300 W
Derating Factor 2 W/°C
(1)
Single Pulse Avalanche Energy 870 mJ
Storage Temperature –65 to 175 °C
Max. Operating Junction Temperature 175 °C
(1) Starting Tj = 25°C, ID = 40A, VDD = 40V
(*) Curren t Li m i ted by wire bonding
1/8September 2002
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STW80NF55-08
THERMA L D ATA
Rthj-case Thermal Resistance Junction-case Max 0.5 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
Maximum Lead Temperature For Soldering Purpose 300 °C
ELECTRICAL CHARACTERISTICS (T
= 25 °C UNLESS OTHERWISE SPECIFIED)
CASE
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
Drain-source
ID = 250 µA, VGS = 0 55 V
Breakdown Voltage
V
= Max Rating
DS
V
= Max Rating, TC = 125 °C
DS
V
= ±20V ±100 nA
GS
1µA
10 µA
ON
I
I
GSS
(1)
DSS
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
= VGS, ID = 250µA
DS
VGS = 10V, ID = 40 A
234V
0.0065 0.008 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > 2.5 V, ID=18 A 20 S
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 800 pF
Reverse Transfer
Capacitance
V
= 25V, f = 1 MHz, VGS = 0
DS
3850 pF
250 pF
2/8
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STW80NF55-08
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time 85 ns
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
d(off)
t
f
t
f
t
c
Turn-off-Delay Time
Fall Time
Off-voltage Rise Time
Fall Time
Cross-over Time
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (2)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µs, duty c ycle 1.5 %.
2. Pulse width li mited by safe operating area.
Source-drain Current 80 A
(1)
Source-drain Current (pulsed) 320 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
= 27V, ID = 40A
DD
R
= 4.7Ω VGS = 10V
G
(see test circuit, Figure 3)
VDD = 80V, ID = 80A,
VGS = 10V
VDD = 27V, ID = 40A,
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 3)
GS
=80A
D
= 10V
Vclamp =44V, I
R
=4.7Ω, V
G
(see test circuit, Figure 5)
ISD = 80A, VGS = 0
= 80A, di/dt = 100A/µs,
I
SD
VDD = 50V, Tj = 150°C
(see test circuit, Figure 5)
25 ns
115
150
24
46
70
25
85
75
110
1.5 V
80
250
6.4
nC
nC
nC
ns
ns
ns
ns
ns
ns
nC
A
Ther m al Impeda n c eSafe Operating Area
3/8
Page 4
STW80NF55-08
Output Characteristics
Tranconductance
Tranfer Characteristics
Static Drain-Source On Resistance
Gate Charge vs Gate-source Voltage
4/8
Capacitance Variations
Page 5
STW80NF55-08
Normalized On Resistance vs Temperatur eNormalized Gate Thereshold Voltage vs Temp.
Source-drain Diode Forward Characteristics
Normalized Breakdown Voltage vs Temperature
5/8
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STW80NF55-08
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
6/8
Page 7
TO-247 MECHANICAL DATA
STW80NF55-08
DIM.
A 4.85 5.15 0.19 0.20
D 2.20 2.60 0.08 0.10
E 0.40 0.80 0.015 0.03
F 1 1.40 0.04 0.05
F1 3 0.11
F2 2 0.07
F3 2 2.40 0.07 0.09
F4 3 3.40 0.11 0.13
G 10.90 0.43
H 15.45 15.75 0.60 0.62
L 19.85 20.15 0.78 0.79
L1 3.70 4.30 0.14 0.17
L2 18.50 0.72
L3 14.20 14.80 0.56 0.58
L4 34.60 1.36
L5 5.50 0.21
M 2 3 0.07 0.11
V
V2
Dia 3.55 3.65 0.14 0.143
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
5º5º
60º 60º
7/8
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STW80NF55-08
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for t he
consequences of use of su ch in formation nor for any in fringement of paten ts or o ther rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as c ritical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.
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