TheSTV160NF02Lrepresents thesecond
generationofApplicationSpecific
STMicroelectronics well established STripFET
process based on a very unique strip layout
design. The resulting MOSFET shows unrivalled
high packing density with ultra low on-resistance
and superior switching charactestics. Process
simplificationalsotranslatesintoimproved
manufacturing reproducibility. This device is
particularly suitable for high current, low voltage
switchingapplicationwhere efficiency is crucial.
10
1
PowerSO-10
INTERNAL SCHEMATIC DIAGRAM
CONNECTIONDIAGRAM (TOP VIEW)
APPLICATIONS
■ BUCK CONVERTERSIN HIGH
PERFORMACETELECOMAND VRMs
DC-DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUni t
V
V
V
I
D
I
DM
P
T
(•) Pulse width limited by safe operating area(**) Limited only maximumjunction temperature allowed by PowerSO-10
June 1999
Drain-source Voltage (VGS=0)20V
DS
Drain- gate Voltage (RGS=20kΩ)20V
DGR
Gate - source V o lt age
GS
20V
±
(**)Drain Current (cont inu ous) at Tc=25oC160A
I
Drain Current (cont inu ous) at Tc=100oC113A
D
(•)Drain Current (pulsed)640A
Tota l Dissipati on at Tc=25oC160W
tot
Derat ing F ac t or1.07W/
Stor age Tem perature-65 to 175
stg
Max. Operating Junct ion Tem perature175
T
j
o
C
o
C
o
C
1/8
Page 2
STV160NF02L
THERMAL DATA
R
thj-case
R
thj-amb
T
Ther mal Resistance J unction- cas eMax
Ther mal Resistance J unction- ambientMax
Maximum Lead Temperatu re F or So lder ing Purpos e
l
0.9375
50
300
o
C/W
o
C/W
o
C
ELECTRICAL CHARACTERISTICS
=25oC unlessotherwisespecified)
(T
J
OFF
SymbolParameterTest ConditionsMin.Typ.M ax.Unit
V
(BR)DSS
Drain-source
ID=250µAVGS=020V
Break dow n Volt age
I
DSS
I
GSS
Zero Gate Voltage
Drain Cur rent ( V
GS
Gat e- bod y L eak ag e
Current (V
DS
=0)
=0)
V
=MaxRating
DS
=MaxRatingTc=25oC
V
DS
V
=± 15 V
GS
1
10
100nA
±
ON(∗)
SymbolParameterTest ConditionsMin.Typ.Max.U nit
V
GS(th)
R
DS(on)
I
D(on)
Gate Threshold Voltage VDS=VGSID= 250 µATc=25oC11.72.5V
Sta t ic Drain -s ource On
Resistance
VGS=10V ID=80A
=8VID=80A
V
GS
V
=4.5V ID=40A
GS
=10V ID=80ATj=175oC
V
GS
V
=8VID=80ATj=175oC
GS
=4.5V ID=40ATj= 175oC
V
GS
On State Drain Current VDS>I
D(on)xRDS(on )max
1.6
1.7
3.5
160A
2.5
3.5
6
5.7
7
11.4
VGS=10V
µA
µA
m
mΩ
m
mΩ
m
mΩ
Ω
Ω
Ω
DYNAMIC
SymbolParameterTest ConditionsMin.Typ.Max.U nit
gfs(∗)Forward
Tr ansc on duc tance
R
C
C
C
Gate re sistanceVDS=15V f=1MHz VGS=00.9Ω
g
Input Capac i t ance
iss
Out put Capacitanc e
oss
Reverse Tr ansfer
rss
Capacit a nc e
C
C
C
Input Capac i t ance
iss
Out put Capacitanc e
oss
Reverse Tr ansfer
rss
Capacit a nc e
2/8
VDS>I
D(on)xRDS(on )maxID
= 80 A210S
VDS=15V f=1MHz VGS= 04900
2950
565
VDS=0V f=1MHz VGS= 07200
13000
4220
pF
pF
pF
pF
pF
pF
Page 3
STV160NF02L
ELECTRICAL CHARACTERISTICS
(continued)
SWITCHING ON
SymbolParameterTest ConditionsMin.Typ.Max.U nit
t
d(on)
Tur n-on Delay Time
Rise Ti m e
t
r
VDD=15VID=40A
R
=4.7
G
Ω
VGS=10V
23
350
(Resis t iv e Loa d, see fig. 3)
Q
Q
Q
Tot al Gat e Charge
g
Gat e- Source Charg e
gs
Gate-Drain Charge
gd
VDD=16V ID= 160 A VGS= 10 V103
38
9
SWITCHING OFF
SymbolParameterTest ConditionsMin.Typ.Max.U nit
t
d(off)
Tur n-of f D ela y Time
t
Fall T ime
f
VDD=15VID=40A
R
G
=4.7
Ω
VGS=10V
105
120
(Resis t iv e Loa d, see fig. 3)
t
d(off)
t
r(Voff)
t
t
Tur n-of f D ela y Time
Off-volt ag e Rise T ime
Fall T ime
f
Cross-over T im e
c
V
=16VID=80A
clamp
R
=4.7
G
Ω
VGS=10V
(Indu ct iv e Load , see f ig . 5)
85
46
335
404
SOURCEDRAINDIODE
SymbolParameterTest ConditionsMin.Typ.Max.U nit
I
SD
I
SDM
V
SD
t
Q
I
RRM
(∗) Pulsed:Pulse duration= 300 µs, duty cycle 1.5%
(•) Pulse width limited by safe operating area
Source-drain Current
(•)
Source-drain Current
160
640
(pulsed)
(∗)ForwardOnVoltage ISD= 160 AVGS=01.5V
Reverse Recovery
rr
Time
Reverse Recovery
rr
ISD= 80 Adi/dt = 10 0 A/µs
=15V
V
DD
(see test circuit, fig. 5)
100
0.25
Charge
Reverse Recovery
5
Current
ns
ns
nC
nC
nC
ns
ns
ns
ns
ns
ns
A
A
ns
µ
A
C
SafeOperating AreaThermalImpedance
3/8
Page 4
STV160NF02L
OutputCharacteristics
Transconductance
TransferCharacteristics
Static Drain-sourceOn Resistance
Gate Charge vs Gate-sourceVoltage
4/8
CapacitanceVariations
Page 5
STV160NF02L
NormalizedGate ThresholdVoltage vs
Temperature
Source-drainDiode Forward Characteristics
NormalizedOn Resistancevs Temperature
BasicSchematic For MotherboardVRM Whith
SynchronousRectification
BasicSchematic Mosfet Switch Used In
SecondarySideOf a FowardConvert
5/8
Page 6
STV160NF02L
Fig. 1
: UnclampedInductiveLoadTest Circuit
Fig. 3: SwitchingTimes Test Circuits For
ResistiveLoad
Information furnishedis believed tobeaccurate and reliable.However, STMicroelectronics assumes no responsibilityfor the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationmentioned in this publication are
subjecttochange without notice. Thispublication supersedes and replaces all information previouslysupplied. STMicroelectronics products
are not authorized for use as critical components in lifesupport devicesor systemswithout express written approval of STMicroelectronics.
The STlogo is a trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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8/8
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