Datasheet STSR2P, STSR2PM Datasheet (ST)

■ SUPPLY VOLTAGE RANGE: 4.5V TO 5.5V

■ TYPICAL PEAK OUTPUT CURRENT:

SOURCE -2A, SINK 3.5A

■ OPERATING FREQUENCY: 20 TO 750 KHZ

■ SMART TURN-OFF ANTICIPATION TIMING

■ OPERATION INDEPENDENT F ROM THE

FORWARD MAGNETIC RESET TECHNIQUE

■ POSSIBILITY TO OPERATEIN

DISCONTINUOUS MODE

STSR2P/

STSR2PM

FORWARD SYNCHRONOUS

RECTIFIERS SMART DRIVER

SO-8

DESCRIPTION

STSR2P Smart Driver IC provides two
complementary high current outputs to drive
Power Mosfets. The IC is dedicated to properly
drive secondary Synchronous Rectifiers in
medium power, low output voltage, high efficiency
Forward Converters. F rom a synchronizing clock
input, STSR2P generates two driving signals with
the self-setting of dead time between
complementary pulses. The IC operation prevents
secondary side shoot-through conditions
providing proper timing at the outputs turn-off
transition. This sm art function operates through a
fast cycle-after-cycle control logic mechanism
based on an internal high frequency oscillator,
synchronized by the clock signal. A fixed

SCHEMATIC DIAGRAM

anticipation in turning-off the OUT
respect to the clock signal transition is provided,
while the anticipation in turning off the OUT
can be set through external components. The
adopted transitions revela tion mechanism makes
circuit operation ind ependent by the forward
magnetic reset t ec hnique used, avoiding most of
the common problems inherent in self-driven
synchronous rectifiers. A special Inhibit function
allows the shut-off of OUT

GATE2

makes discontinuous conduction m ode possible
and prevents the freewheeling mosfet from
sinking current from the output.
STSR2P automat ically turns off the outputs when
duty-cycle is lower than 13%, while STSR2PM
works even at very low duty-cycle values.

Vcc

2

BIAS

UVLO

+

5.7V

GATE1

with

GATE2

. This feature

CK

INHIBIT

PEAK

4

DETECTOR

+

HIGH

5

FREQUENCY
OSCILLATOR

­+

25mV

DIGITAL

CONTROL

6

SGLGND

ANTICIPATION

SET

OUTPUT

BUFFERS

8

PWRGND

+

SETANT2

3

1 OUTGate1

OUTGate2

7

1/12September 2003

STSR2P/STSR2PM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V

OUTGATE

V

INHIBIT

V

I

LX

P

TOT

ESD Human Body Model Pins 1,2, 4, 5, 6, 7, 8 ±1KV

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
(*) A higher positive voltage level can be applied to the pin with a resistor which limits the current flowing into the pin to 10mA maximum

THERMAL DATA

Symbol Parameter SO-8 Unit

R

thj-amb

R

thj-amb

(*) This value is referred to one layer pcb board with minimum copper connections for the leads. a minimum value of 120 °C/W can be
obtained improving thermal conductivity of the board

DC Input Voltage

CC

Max Gate Drive Output Voltage -0.3 to V
Max INHIBIT Voltage (*) -0.6 to V
Clock Input Voltage Range (*) -0.3 to V

CK

Switching Peak Current

-0.3 to 6 V

CC
CC
CC

2A

Continuous Power Dissipation at TA=105°C without heatsink 270 mW

Pin 3 ±0.9 KV

Storage Temperature Range

stg

Operating Junction Temperature Range -40 to +125 °C

op

Thermal Resistance Junction-case
Thermal Resistance Junction-ambient (*)

-55 to +150 °C

40 °C/W

160 °C/W

V
V
V

ORDERING CODES

TYPE SO-8 SO-8 (T&R)

STSR2P STSR2PCD STSR2PCD-TR

STSR2PM STSR2PMCD STSR2PMCD-TR

CONNECTION DIAGRAM (top view)

2/12

PIN DESCRIPTION

Pin N° Symbol Name and Function

1OUT

2V

3 SET

GATE1

CC

ANT2

4 CK This input provides synchronization for IC’s operations, being the transitions

5 INHIBIT This input enables OUT

6 SGLGND Reference for all the control logic signals. This pin is completely separated from

7OUT

GATE2

8 PWRGND Reference for power signals, this pin carries the full peak currents for the two

Gate Drive signal for Rectifier MOSFET.Anticipation (t
OUT

is provided when the clock input goes to low level.

GATE1

The supply voltage range from 4.5V to 5.5V allows applications with logic gate
threshold mosfets. UVLO feature guarantees proper start-up while it avoids
undesirable driving during eventual dropping of the supply voltage.

The voltage on this pin sets the anticipation (t
is possible to choose among three different anticipation times by discrete

partitioning of the supply voltage.

between the two output conditions based on a positive threshold, equal for the
two slopes. A smart internal control logic mechanism using a 15MHz internal
oscillator generates proper anticipation timing at the turn-off of each output. This
feature allows safe turn-off of Synchronous Rectifiers avoiding any eventual
shoot-through situation on secondary side at both transitions. Smart clock
revelation mechanism makes these operations independent by false triggering
pulses generated in light load conditions and by particular demagnetization
techniques.Absolute maximum voltage rating of the pin can be exceeded limiting
the current flowing into the pin to 10mA max.

to work when its voltage is lower than the negative
threshold voltage (V
minimum conduction time (t

GATE2

INHIBIT<VH

ON(GATE2)

). If V

INHIBIT>VH

). In typical forward converter application, it

is possible to turn off the freewheeling MOSFET when the current through it tends
to reverse, allowing discontinuous conduction mode and providing protection to
the converter from eventual sinking current from the load.Absolute maximum
voltage rating of the pin can be exceeded limiting the current flowing into the pin
to 10mA max.

the PWRGND to prevent eventual disturbances to affect the control logic.
Gate Drive signal for Freewheeling MOSFET. Anticipation [t
OUT

is provided when the clock input goes to high level.

GATE2

outputs.

STSR2P/STSR2PM

) in turning off

ANT1

) in turning off the OUT

ANT1

the OUT

GATE2

ANT2

GATE2

will be high for a

] in turning off

.It

3/12

STSR2P/STSR2PM

ELECTRICAL CHARACTERISTICS(VCC=5V, CK= 250kHz, V

INHIBIT

=-200mV, TJ=-40 to 125°C, unless

otherwise specified.)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

SUPPLY INPUT AND UNDER VOLTAGE LOCK OUT

V

CCON

V

CCOFF

V

I

GATE DRIVER OUTPUTS

V
V

I

OUT

R

OUT

t

t

TURN-OFF ANTICIPATION TIME

t

ANT1

t

ANT2

I

SETANT2

INHIBIT OUT

V

t

ON(GATE2)

V

I

D

t

PW

Note1:tRis measured between 10% and 90% of the final voltage; tFis measured between 90%and 10%on the initialvoltage
Note2: Parameter guaranteed by design

Start Threshold 3.8 4 V
Turn OFF Threshold After

3.5 3.6 V

Start
Zener Voltage CK=0V IZ= 2mA 5.5 5.8 6 V

Z

Unloaded Supply Current OUT

CC

Output Low Voltage I

OL

Output High Voltage I

OH

Output Source Peak

CK=0V OUT

OUTGATE1,2
OUTGATE1,2

= no load 22 30 mA

GATE1,2

= no load 3 5

GATE1,2

=-200mA 0.10 0.16 V
=200mA 4.70 4.85 V

2A

Current
Output Sink Peak Current 3.5
Output Series Source

Resistance
Output Series Sink

Resistance
OUT

t

R

t

F

P1

P2

GATE1,2

OUT

GATE1,2

Clock Propagation Delay to
Turn ON of OUT

Clock Propagation Delay to
Turn ON of OUT

OUT

GATE1

Rise Time C
Fall Time C

GATE1

GATE2

Turn-off

I

OUTGATE1,2

I

OUTGATE1,2

LOAD
LOAD

=-200mA 0.75 1.5 Ω

=200mA 0.5 0.8

=5nF (Note 1) 40 ns
=5nF (Note 1) 30 ns

No Load 130 ns

No Load 50 ns

No Load 75 ns
Anticipation Time
OUT
Anticipation Time

GATE2

Turn-off

V

= 0 to 1/3VCC; no load 75 ns

ANT2

=1/3VCCto 2/3VCC; no load 150

V

ANT2

=2/3VCCto VCC; no load 225

V

ANT2

Leakage Current (Note 2) -0.1 0.1 µA

ENABLE

GATE2

Threshold Voltage TJ= 25°C -30 -25 mV

H

Leakage Current (Note 2) V

I

H

OUT

GATE1

Turn-off

V

V

= 200mV -400 nA

INHIBIT

= -200mV 1 µA

INHIBIT

= 200mVNo Load 250 ns

INHIBIT

Anticipation Time
Reference Voltage TJ= 25°C 2.6 2.8 V

CK

LX Leakage Current 600 µA

CK

Duty Cycle Shut Down TJ= 25°C for STSR2P 13 14 %

OFF

Duty Cycle Turn ON after
Shut Down

T

= 25°C for STSR2P 18 20

J

Minimum Pulse Width STSR2PM 200 ns

4/12

STSR2P/STSR2PM

TIMING DIAGRAM

APPLICATION INFORMATION: STSR2 IN FORWARD CONVERTER SECONDARY SIDE

NOTES

1) Ceramic Capacitors C1 and C2 must be placed very close to the IC;

2)R1andR2settheanticipationtimebypartitioningtheV

3) R3 and R4 is a resistor divider meant to provide the correct CK voltage range;

4) R5 limits the current flowing through diode D2 when Freewheeling drain voltage is high;

5) D1 could be necessary to protect INHIBIT pin from negative voltages.

6) D2 could be necessary to protect INHIBIT pin from voltages higher than V

7) D3 could be necessary to protect CK pin from voltages higher than VCC.

8) SGLGND layout trace must not include OUT

9) A capacitor in parallel with R4 could be necessary to eliminate turn off voltage spike.

GATE1,2

voltage;

CC

current paths.

CC

5/12

STSR2P/STSR2PM

EXAMPLE OF COMPONENTS SELECTION FOR A FORWARD CONVERTER

Forward Specification:

=36-72V

V

IN

=3.3V

V

OUT

n=Np/Ns=4.5
R

and R4are calculated assuring a minimum voltage of 2.8V at CK pin. At 36V input, the voltag e on the

3

secondary winding is 36/4 .5= 8V. Choosing R

V

×

--------------------------------------------------------------- -

≥ 1kΩ

R

4

V

INICK 2.8()

R

=1kΩ is cho sen. At 72V input the current at CK pin is calculated as:

4

V

IN max()

-----------------------------------------------------

I

CK

CKR3

– R3V

V

– 0.3–

R

3

–×

CC

This value is below the maximum allowable current flowing into the CK pin (10mA). If the 10mA value is
exceeded an external diode connected to V

and R2values set the anticipation time for OUT

R

1

R

=10kΩ,t

1=R2

The RC group composed by R

=150ns; for R1=0 and R2=∞,t

ANT2

and the parasitic capacitance o f Inh ibit pi n (ty pically 5pF) delays the

5

signal on Inhibit comparator. This delay mu st be lower than 200ns. This condition imposes a maximum
value for R

In general a suggested value for R

of about 20kΩ.

5

is 10kΩ. At 72V input, the secondary voltage is 16V, so the max imum

5

current flowing into Inhibit pin is 16V/10kΩ=1.6mA which is below the maximum allowable current for the
pin (10mA). If the 10mA value is exceeded an external diode (D2) connected to V

The maximum negative voltage of –0.6V must be guaranteed for the Inhibit pin. If this negative voltage is
exceeded the current must be limited to 50mA. If necess ary, a diode (D1) connected to S GLGND can be
added to satisfy this specification.

=1.5KΩ,R4results to be:

3

------------------------------------------------------------------------- -

× 862Ω==

CK

16 5– 0.3–

----------------------------- -

1.5kΩ

CC

8V 220µA– 1.5kΩ 2.8V–×

must be added (D3).

GATE2

=225ns.

ANT2

2.8V 1.5kΩ()×

7.13mA===

.ForR1=∞and R2=0, t

ANT2

must be added.

CC

=75ns; for

INHIBIT OPERATION OF OUT

6/12

IN DISCONTINUOUS CONDUCTION MODE

GATE2

STSR2P/STSR2PM

INHIBIT OPERATION OF OUT

NOTE: V

INHIBIT

=+200mV

GATE2

7/12

STSR2P/STSR2PM

TYPICAL P ERFO RMAN CE CHARACTERISTICS (unless otherwise specified Tj=25°C
Figure1 : Zener Characteristics

Figure2 : Rise and Fall Time vs Load Capacitor

Figure4 : Sink-Source ON Resistance vs

Temperature

Figure5 : Clock Threshold Voltage vs
Temperature

Figure3 : OUT

8/12

GATE1,2

vs Characteristics

Figure6 : INHIBIT Threshold Voltage vs
Temperature

STSR2P/STSR2PM

Figure7 : Supply Current vs Load Capacitor

(each output)

Figure8 : Supply Current vs Clock Frequency

Figure10 : Duty Cy c le Shut Down v s

Temperature

Figure11 : Duty Cycle Turn ON After Shut Down
vs Temperature

Figure9 : T

ON(GATE2)

vs Temperature

Figure12 : Clock Leakage Current vs Clock
Voltage

9/12

STSR2P/STSR2PM

SO-8 MECHANICAL DATA

DIM.

A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.04 0.010
A2 1.10 1.65 0.043 0.065

B 0.33 0.51 0.013 0.020

C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197

E 3.80 4.00 0.150 0.157

e 1.27 0.050

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 1.27 0.016 0.050

k ˚ (max.)

ddd 0.1 0.04

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

8

10/12

0016023/C

STSR2P/STSR2PM

Tape & Reel SO-8 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362

T 22.4 0.882
Ao 8.1 8.5 0.319 0.335
Bo 5.5 5.9 0.216 0.232
Ko 2.1 2.3 0.082 0.090
Po 3.9 4.1 0.153 0.161

P 7.9 8.1 0.311 0.319

11/12

STSR2P/STSR2PM

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