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STS8DNH3LL
DUAL N-CHANNEL 30V - 0.018 Ω - 8A SO-8
LOW GATE CHARGE STripFET™ III POWER MOSFET
TYPE
V
DSS
R
DS(on)
I
D
STS8DNH3LL 30 V <0.022 Ω 8 A
■ TYPICAL R
■ OPTIMAL R
■ CONDUCTION LOSSES REDUCED
■ SWITCHING LOSSES REDUCED
(on) = 0.018Ω
DS
(on) x Qg TRADE-OFF @ 4.5V
DS
DESCRIPTION
This application specific MOSFET is the Third generation
of STMicroelectronis unique "Single Feature Size™"
strip-based process. The resulting transistor shows the
best trade-off between on-resistance and gate charge.
When used as high and low side in buck regulators, it
gives the best performance in terms of both conduction
and switching losses. This is extremely important for
motherboards where fast switching and high efficiency
are of paramount importance.
APPLICATIONS
■ SPECIFICALLY DESI GNED AND OPTIMI SED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS FOR MOBILE PC
S
SO-8
INTERNAL SCHEMATIC DIAGRAM
Ordering Information
STS8DNH3LL S8DNH3LL SO-8 TAPE & REEL
SALES TYPE MARKING PACKAGE PACKAGING
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
(•)
DM
P
tot
(•) Pulse width limited by safe operating area.
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
30 V
30 V
Gate- source Voltage ± 16 V
Drain Current (conti nuo us ) at TC = 25°C
Drain Current (conti nuo us ) at TC = 100°C
8A
5A
Drain Current (pulse d) 32 A
Total Dissipation at TC = 25°C
2W
Rev.0.2
1/9June 2004
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STS8DNH3LL
TAB.1 THERMAL DATA
Rthj-amb
T
T
stg
(*)
When mounted on 1 inch2 FR-4 board, 2 oz of Cu, t ≤ 10s
ELECTRICAL CHARACTERISTICS (Tj = 25 °C unless otherwise specified)
TAB.2 OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
(*)
Thermal Resistance Junction-ambient
Maximum Operating Junction Temperature
j
Storage Temperature
Drain-source
Breakdown Voltage
Zero Gate Voltage
Drain Current (V
GS
= 0)
Gate-body Leakage
Current (V
DS
= 0)
I
= 250 µA, VGS = 0
D
= Max Rating
V
DS
= Max Rating TC = 125°C
V
DS
= ± 16 V
V
GS
Max 62.5
150
-55 to 150
30 V
1
10
±100 nA
°C/W
°C
°C
µA
µA
TAB.3 ON
(*)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
Resistance
V
= VGS ID = 250 µA
DS
V
= 10 V ID = 4 A
GS
= 4.5 V ID = 4 A
V
GS
1V
0.018
0.020
0.022
0.025
TAB.4 DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(*)
g
fs
C
iss
C
oss
C
rss
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V
=15 V ID=4 A
DS
V
= 25V, f = 1 MHz, VGS = 0
DS
8.5 S
857
147
20
Ω
Ω
pF
pF
pF
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STS8DNH3LL
ELECTRICAL CHARACTERISTICS (continued)
TAB.5 SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
= 15 V ID = 4 A
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time
To tal Ga te Char ge
Gate-Source Charg e
Gate-Drain Charge
TAB.6 SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(off)
t
f
Turn-off Delay Time
Fall Time
TAB.7 SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
V
SD
t
rr
Q
rr
I
RRM
(*)
Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
(
•)Pulse width limited by safe operating area.
Source-drain Curre nt
(•)
Source-drain Curre nt (pu lse d)
(*)
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
V
DD
=4.7 Ω VGS = 10 V
R
G
(Resistive Load, Figu re 1)
V
= 15 V ID= 8 A VGS= 4.5 V
DD
(see test circuit, Figure 2)
V
= 15 V ID = 4 A
DD
=4.7Ω, V
R
G
GS
(Resistive Load, Figu re 1)
I
= 4 A VGS = 0
SD
I
= 8 A di/dt = 100A/µs
SD
= 15 V Tj = 150°C
V
DD
(see test circuit, Figure 3)
= 10 V
12
14.5
7.0
2.5
2.3
23
8
15
5.7
0.76
10 nC
8
32
1.5 V
ns
ns
nC
nC
ns
ns
A
A
ns
nC
A
Safe Operating Area Thermal Impedance
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STS8DNH3LL
Output Characteristics Transfer Characteristics
Transconductance Static Drain-source On Resistance
Gate Charge vs Gate-so urc e Vol tag e Capacitance Variations
4/9
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STS8DNH3LL
Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature
Source-drain Diode Forward Characteristics Normalized Breakdown Voltage Temperature.
. .
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STS8DNH3LL
Fig. 1: Switching Times Test Circuits For Resistive
Load
Fig. 3: Test Circuit For Diode Re cover y Behavi our
Fig. 2: Gate Charge test Circuit
6/9
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SO-8 MECHANICAL DATA
STS8DNH3LL
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A1.750.068
a1 0.1 0.25 0.003 0.009
a2 1.65 0.064
a3 0.65 0.85 0.025 0.033
b 0.35 0.48 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.019
c1 45 (typ.)
D 4.8 5.0 0.188 0.196
E 5.8 6.2 0.228 0.244
e1.27 0.050
e3 3.81 0.150
F 3.8 4.0 0.14 0.157
L 0.4 1.27 0.015 0.050
M0.60.023
S8 (max.)
mm inch
0016023
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STS8DNH3LL
Revision History
Date Revision Description of Changes
Tuesday 15 June 2004
0.2 FIRST ISSUE
8/9
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STS8DNH3LL
I
s
o
d
b
ct
t
ot
a
nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequence
f use of such information nor for any infrin gement of patents or other rights of third parties which may resul t from its use. No license is grante
y implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subje
o change without notic e. This publication supersedes and replaces all info rmation previously supplied. ST Microelectronics products are n
uthorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners.
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