Datasheet sts7c4f30l Datasheet

TYPE

STS7C4F30L(N-Channel) STS7C4F30L(P-Channel)

■ TYPICAL R

■ STANDARD OUTLI NE FO R EASY

(on) (N-Channel) = 0.018 Ω

DS

(on) (P-Channel) = 0.070 Ω

DS

V

30 V 30 V

DSS

R

DS(on)

<0.022 <0.080

Ω Ω

AUTOMATED SURFACE MOUNT ASSEMBLY

■ LOW THRESHOLD DRIVE

I

D

7 A 4 A

STS7C4F30L

N-CHANNEL 30V - 0.018 Ω - 7A SO-8 P-CHANNEL 30V - 0.070 Ω - 4A SO-8

STripFET™ POW ER MOSFET

DESCRIPTION

SO-8

This Power MOSFET is the latest dev elo pment of

STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remark-

INTERNAL SCHEMATIC DIAGRAM

able manufacturing reproducibility.

APPLICATIONS

■ DC/DC CONVERTERS

■ BATTERY MANAGEMENT IN NOMADIC

EQUIPMENT

■ POWER MANAGEMENT IN CELLULAR

PHONES

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter N-CHANNEL P-CHANNEL Unit

V

DS

V

DGR

V

GS

I

D

I

D

I

(

DM

P

tot

T

stg

T

j

(

Pulse width limited by safe operating area. Note: P-CHANNEL MOSFET actual polarity of voltages and current

•)

.

Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ)

30 30 V 30 30 V

Gate- source Voltage ± 20 ± 20 V

Drain Current (continuos) at TC = 25°C Single Operating

Drain Current (continuos) at TC = 100°C Single Operating

•)

Drain Current (pulsed) 28 16 A Total Dissipation at TC = 25°C Dual Operating

Total Dissipation at T

= 25°C Single Operating

C

74A

4.4 2.5 A

1.6 2

Storage Temperature -60 to 150 °C Max. Operating Junction Temperature 150 °C

has to be reversed

W W

1/10June 2001

STS7C4F30L

THERMA L D ATA

Rthj-amb(1)

T

Thermal Resistance Junction-ambient Single Operation Maximum Lead Temperature For Soldering Purpose

l

Dual Operating

62.5 78

300

°C/W °C/W

°C

(1) when mounted on 0.5 in

ELECTRICAL CHARACTERISTICS (T

2

pad of 2 oz. copper

= 25 °C unless otherwise specified)

case

OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

V

(BR)DSS

I

DSS

I

GSS

Drain-source Breakdown Voltage

Zero Gate Voltage Drain Current (V

GS

Gate-body Leakage Current (V

DS

= 0)

= 250 µA, VGS = 0

D

V

= Max Rating

DS

V

= Max Rating TC = 125°C

DS

V

= ± 20V

GS

V

= ± 20V

GS

n-ch p-ch3030

n-ch p-ch

1

10

±100 ±100nAnA

ON

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

GS(th)

R

DS(on)

Gate Threshold Voltage

Static Drain-source On Resistance

= VGS I

DS

= 10 V ID = 3.5 A

V

GS

V

= 10 V ID = 2 A

GS

V

= 4.5 V ID = 3.5 A

GS

V

= 4.5 V ID = 2 A

GS

= 250 µA

D

n-ch p-ch11

n-ch p-ch n-ch p-ch

1.6

0.018

0.070

0.021

0.085

2.5

0.022

0.080

0.026

0.10

V

µA µA

V V

Ω Ω Ω Ω

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. Unit

(*)

g

fs

C

iss

C

oss

C

rss

Forward Transconductance VDS = 15 V ID= 3.5 A

V

= 15 V ID= 2 A

DS

Input Capacitance

V

Output Capacitance

= 25V, f = 1 MHz, VGS = 0

DS

Reverse Transfer Capacitance

n-ch p-ch

10 10

1050 1350

250 490

85

130

S S

pF pF

2/10

STS7C4F30L

ELECTRICAL CHARACTERISTICS (continued)

SWITCHING ON

Symbol Parameter Test Conditions Min. Typ. Max. Unit

N-CHANNEL

= 15 V ID = 3.5 A

V

t

d(on)

Turn-on Delay Time

DD

R

= 4.7 Ω VGS = 4.5 V

G

P-CHANNEL

t

r

Rise Time

V

= 15 V ID = 2 A

DD

R

= 4.7 Ω VGS = 4.5 V

G

(Resistive Load, Figure 1)

N-CHANNEL

Qg

Total Gate Charge

VDD = 24V ID = 7A VGS = 5V

P-CHANNEL

Q

gs

Q

gd

Gate-Source Charge Gate-Drain Charge

= 24V ID = 4A VGS = 5V

V

DD

(see test circuit, Figure 2)

SWITCHING OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

N-CHANNEL

= 15 V ID = 3.5 A

V

t

d(off)

Turn-off Delay Time

DD

R

= 4.7 Ω VGS = 4.5 V

G

P-CHANNEL

t

f

Fall Time

V

= 15 V ID = 2 A

DD

R

= 4.7 Ω VGS = 4.5 V

G

(Resistive Load, Figure 1)

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

n-ch p-ch

n-ch p-ch n-ch p-ch

n-ch p-ch

22 25

60 35

17.5

12.5 4

5 7 3

42

125

10 35

23 16

ns ns

nC nC

nC nC nC nC

ns ns

I

SD

I

SDM

V

SD

t

rr

Q

rr

I

RRM

(

Pulsed: P ul se duration = 300 µs, dut y c yc l e 1.5 %.

∗)

(

Pulse widt h l i m i ted by safe operating area.

•)

Source-drain Current

(

•)

Source-drain Current (pulsed)

(

∗)

Forward On Voltage

Reverse Recovery Time

Reverse Recovery Charge Reverse Recovery Current

I

= 7 A VGS = 0

SD

I

= 4 A VGS = 0

SD

N-CHANNEL

ISD = 7 A di/dt = 100A/µs V

=15 VTj =150 oC

DD

P-CHANNEL

I

= 4 A di/dt = 100A/µs

SD

=15 V Tj =150 oC

V

DD

(see test circuit, Figure 3)

n-ch p-ch n-ch p-ch

n-ch p-ch

n-ch p-ch n-ch p-ch

50 45

40 36

1.6

7

4 28 16

1.2

A A A

A V

V

ns ns

nC nC

A A

3/10

STS7C4F30L

Safe Operating Area n-ch Thermal Impedance n-ch

Output Characteristics n-ch Transfer Characteristics n-ch

Transconductan ce n- ch Static Drain-source On Resistance n-ch

4/10

STS7C4F30L

Gate Charge vs Gate-source Voltage n-ch Capacitance Variations n-ch

Normalized Gate Threshold Voltage vs Temperature n-ch Normalized on Resistance vs Temperature n-ch

Source-drain Diode Forward Characteristics n-ch

5/10

STS7C4F30L

Safe Operating Area p-ch Thermal Impedance p-ch

Output Characteristics p-ch Transfer Characteristics p-ch

Transconduc tance p-ch Static Drain-source On Resistance p-ch

6/10

STS7C4F30L

Gate Charge vs Gate-source Voltage p-ch Capacitance Variations p-ch

Normalized Gate Threshold Voltage vs Temperature p-ch Normalized on Resistance vs Temperature p-ch

Source-drain Diode Forward Characteristics p-ch

7/10

STS7C4F30L

Fig. 1: Switching Times Test Circuits For Resistive

Load

Fig. 3: Test Circuit For Diode Recovery Behaviour

Fig. 2: Gate Charge test Circuit

8/10

SO-8 MECHANICAL DATA

STS7C4F30L

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A1.750.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033

b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010

C 0.25 0.5 0.010 0.019

c1 45 (typ.)

D 4.8 5.0 0.188 0.196

E 5.8 6.2 0.228 0.244

e1.27 0.050 e3 3.81 0.150

F 3.8 4.0 0.14 0.157

L 0.4 1.27 0.015 0.050

M0.60.023

S 8 (max.)

mm inch

0016023

9/10

STS7C4F30L

Information furnished is believed to be accurate and reliable. However, STMicroelec tronics as sumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implic ation or o th erwise u nder any pat ent or pat ent righ ts of STMicroelectron i cs. Specifications m entioned i n this publication are s ubject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as c ritical components in li f e support dev i ces or systems without express writ t en approval of STMicroel ectronics.

The ST log o i s registered trademark of STMic roelectronics

2001 STMi croelectronics - All Rights Re served

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