The Series STR-F6600 is specifically designed to satisfy the requirements for increased integration and reliability in off-line quasi-resonant
flyback converters. The series incorporates a primary control and drive
circuit with discrete avalanche-rated power MOSFETs.
Covering the power range from below 25 watts up to 300 watts for
100/115/230 VAC inputs, and up to 150 watts for 85 to 265 VAC
universal input, these devices can be used in a range of applications,
from battery chargers and set top boxes, to televisions, monitors, and
industrial power supply units.
Cycle-by-cycle current limiting, under-voltage lockout with hysteresis, over-voltage protection, and thermal shutdown protects the power
supply during the normal overload and fault conditions. Over-voltage
protection and thermal shutdown are latched after a short delay. The
latch may be reset by cycling the input supply. Low-current startup and
a low-power standby mode selected from the secondary circuit completes
a comprehensive suite of features. The series is provided in a five-pin
overmolded TO-3P style package, affording dielectric isolation without
compromising thermal characteristics.
The voltage on the VIN terminal (pin 4) controls startup
and shutdown of the Series STR-F6600 devices.
Figure 1 shows a typical start up circuit. The V
IN
terminal voltage during startup is shown in figure 2.
Figure 1 – Start-Up Circuit
At startup, C2 is charged through the startup resistor RS.
When the V
terminal voltage reaches 16 V (typ.), the
IN
control circuit enables regulator operation. Once the
regulator starts, it draws up to 30 mA from C2 causing the
voltage on C2 to fall momentarily. Once the regulator
output voltage is established, the drive winding D starts to
charge C2 via D2. The voltage on C2 thus recovers to the
nominal drive voltage (18 V).
As shown in figure 3, the input current is below 100 µA
= 25°C) prior to control circuit turn on. The latch
(at T
M
circuit holding current is 400 µA (max.). To ensure latch
operation, the current in RS at the lowest ac input voltage
should be at least 500 µA.
I
30 mA
(MAX.)
IN
I
IN(ON)
INQ
V
V
IN
ON-STATE VOLTAGE (V
16 V
(TYP.)
11 V
(MAX.)
STARTUP
DELAY
INT
)
UNDER-VOLTAGE LOCKOUT (V
OPERATION START
Figure 2 – Waveform of VIN Terminal Voltage
at Startup
INQ
)
DRIVE WINDING
VOLTAGE
TIME
100 µA
(MAX.)
I
IN(OFF)
Figure 3 – Supply Terminal Current, I
The value of R
thus determines the charge time of C2
S
and thus the startup delay. R
11 V
(MAX.)
is typicaly 68 kΩ for wide
S
14.4 V
(MIN.)
INT
V
V
IN
IN
operation (90 V ac to 265 V ac) and 100 kΩ for 220 volt
ac operation.
The choice of C2 is a compromise between an accept-
able startup delay (in conjunction with R
) and a hold-up
S
time sufficient to keep pin 4 above its under-voltage
shutdown threshold of 11 V. Typically C2 is in the range
The drive winding voltage is set such that in normal
operation the C2 voltage is above the specified maximum
shutdown voltage
(11 V) and below the specified mini-
mum over-voltage threshold (20.5 V).
In applications where there is a significant variation in
load current, the VIN terminal voltage may vary, as shown
in figure 4. This is due to peak charging of C2. In this
case, adding a resistor in the range of a few ohms to tens of
ohms in series with the rectifier diode D2 will bring the
voltage variation within limits.
V
IN
I
OUT
Figure 4 – Output Current I
– Terminal Voltage V
OUT
IN
Soft Start, Quasi Resonant and Voltage Regulation
comparator output pre-terminates the oscillator, which
turns off the MOSFET drive signal.
The MOSFET is turned on again when either c
SS
discharges or a quasi-resonance signal is detected on pin 1.
Fixed 50
µs Off-Time: Soft-Start Mode
This is the mode of operation in the absence of a quasi-
resonance signal on pin 1 (see figure 5), and occurs at
Figure 5 – Soft-Start Operation
startup and in overload. It also can be commanded externally to provide low-power standby operation.
Refer to the Functional Block Diagram and the Typical
Application Diagram (figure 6). The internal oscillator
uses the charge/discharge of an internal 4700 pF capacitor
(cSS) to generate the MOSFET drive signals.
The regulator has two modes of operation:
1. fixed 50 µs off time (soft start) and
2. demagnetization sensing quasi-resonant mode —
normal operation.
In both cases, voltage regulation is achieved by taking
the composite optocoupled voltage error and superimposed
drain current ramp (current-mode control) and comparing
this to an internal 0.73 V reference. The FBK/OCP
In the absence of a feedback signal (such as at startup,
or a short circuit) the drain current ramp, sensed across R5
and noise filtered by R4/C5 appears on pin 1. When the
ramp voltage on C5 exceeds the 0.73 V reference signal,
the FBK/OCP comparator changes state, shutting down the
oscillator and turning off the MOSFET. Thus the voltage
is held high (6.5 V) by the comparator. When the
on c
SS
comparator changes state, cSS discharges via rSS; the
voltage on cSS ramps down until it reaches 3.7 V. The
oscillator turns on the MOSFET. This ramp-down time is
internally trimmed to 50 µs. The comparator changes state
again and the cycle repeats. Thus in the absence of
feedback, the current-sense resistor R5 accurately controls
the MOSFET maximum current.
TM
™
Page 7
AC INPUT
RECTIFIER
FULL-BRIDGE
Series STR-F6600
OFF-LINE
QUASI-RESONANT FLYBACK
SWITCHING REGULATORS
Functional Description and Operation (cont’d)
+ OUTPUT
4
DRIVE
REG.
UVLO
+
REF.
OVER-VOLT.
PROTECT
TSD
R
FAULT
LATCH
SQ
OSC
3
2
+
+
VOLTAGE
SENSE
– OUTPUT
Figure 6 – Series STR-F6600 Typical Application
WARNING — These devices are designed to be operated at lethal voltages and energy levels. Circuit
designs that embody these components must conform with applicable safety requirements. Precautions must be taken to prevent accidental contact with power-line potentials. Do not connect
grounded test equipment.
The use of an isolation transformer is recommended during circuit development and breadboarding.
Soft Start with Voltage Feedback (refer to figure 7)
Output voltage control is achieved by sensing the optocoupled feedback current (proportional to the output
voltage error signal) across resistor R4 and summing this
with the drain current ramp on R5. The signal on pin 1 is
therefore the opposite of the output voltage error signal
and the drain current ramp. The dc bias signal across R4 is
thus a function of the load. Consequently at light load, the
bias signal on R4 is closer to the threshold voltage of the
comparator.
–
+
1.45 V
–
+
0.73 V
1
★
To eliminate the possibility of false shutdown at
MOSFET turn on (when there is a current spike due to the
discharge of primary capacitance), a constant-current sink
of 1.35 mA is turned on, effectively lowering the input
impedance on pin 1, and momentarily increasing the
shutdown threshold.
Refer to the Functional Block Diagram, Typical Application diagram (figure 6), and Quasi-Resonance Waveforms (figure 8).
V
V
V
V
P
DS
D
FDBK
t = π√LpC
V
P
V
IN
V
4
f R = 1/2π√LpC
DS
(min)
4
V
OCP
≈
2.8 V
V
th(2)
≈
1.45 V
V
th(1)
≈
0.73 V
Regulation is achieved as in fixed off-time mode but
instead of having a fixed off-time, the demagnetization of
the transformer is sensed by a second comparator. This
comparator threshold, V
is nominally 1.45 V.
th(2)
Quasiresonance sensing makes use of the natural magnetizing
and leakage inductances and self-capacitances of the
power circuit.
Figure 8 shows the drain voltage waveform, (V
DS
), on
pin 3 of the STR-F66xx, as well as VP, the voltage on the
primary of the transformer.
Once the current in the output diode stops flowing, the
primary stored energy ‘rings’ as shown by V
The resonant frequency (f
) is determined by the magne-
r
and VDS.
P
tizing inductance of the transformer and the capacitor C4.
The addition of this capacitor sets the ringing frequency
and reduces the harmonic content in the V
waveform,
DS
lowering EMI. Also since VDS falls to a minimum during
the first half-cycle of the ring this point can be sensed and
used to turn on the MOSFET with minimum voltage
across it. Thus the MOSFET is low voltage and zero
current switched (LVS/ZCS).
TM
™
Page 9
QUASI-RESONANT FLYBACK
SWITCHING REGULATORS
Functional Description and Operation (cont’d)
Series STR-F6600
OFF-LINE
The voltage V
(pin 1) has the same form as the V
OCP
DS
waveform. The condition for quasi-resonant operation is
given by:
2.0 V < V
> 5.5 V for >1 µs
OCP
Transformer design is exactly as for any other discon-
tinuous-mode type flyback.
For optimum EMI/efficiency performance, quasiresonance turn off is achieved when the MOSFET is at
zero voltage and zero current; that is, at one half cycle of
the quasi-resonance frequency, f
.
r
Over-Current Protection (OCP) Functions
Refer to the Functional Block diagram and Typical
Application diagram (figure 6).
The regulator implements pulse-by-pulse over-current
protection, which limits the maximum drain current in the
MOSFET on every pulse by switching off the internal
drive to the MOSFET, and the MOSFET drain current is
detected across R5.
Drive Circuit
Refer to the Functional Block Diagram.
This circuit is driven from the oscillator and provides
the current drive to charge and discharge the MOSFET
gate-source capacitance, thereby switching the device on
and off. The basic circuit configuration is totem-pole type
with an additional limiting resistor in the gate circuit at
turn on. This limits the turn on speed of the MOSFET,
thereby reducing EMI due to the discharge of primary
capacitance. This is possible because of the low-voltage
switching, zero-current switching nature of the turn on.
The value of the turn-off resistance is lower, allowing
the device turn-off current to be increased. This reduces
the turn-off loss in the MOSFET.
Latch Circuit
The latch circuit keeps the oscillator output low to
inhibit operation of the regulator when over-voltage
protection (OVP) and thermal shutdown (TSD) circuits are
in operation. As long as the latch hold-in current is
400 µA (max., supplied via R
) with VIN at 8.5 V (pin 4),
S
the regulator will stay in the off state.
An internal noise filter provides 10 µs of noise immu-
nity to prevent spurious operation of the over-voltage
protection or thermal shutdown.
With the latch ‘on’, the voltage on pin 4 cycles between
16 V and 10 V as shown in figure 9. This is due to the
higher current drawn when the pin 4 is at 16 V compared
to that drawn close to shutdown (10 V).
Pulling V
(pin 4) below 6.5 V will reset the latch
IN
circuit, re-enabling the regulator.
Thermal Shutdown
This internal feature triggers the latch if the internal
frame temperature exceeds 140
°C (typ.).
The temperature is sensed on the control IC, but also
protects against overheating of the MOSFET as the
MOSFET and the control IC are mounted on the same lead
frame. Additionally, protection is provided for other onboard components.
V
IN
16 V
(TYP.)
10 V
(TYP.)
The gate drive voltage (8.3 V) is such that even with
0.73 V across R5 (drain current sense resistor), the
MOSFET is fully enhanced, allowing full use to be made
of its high current handling capacity.
This feature of the STR-F66xx triggers the latch circuit
when the V
voltage (pin 4) exceeds 22.5 V (typ.).
IN
Because the voltage on pin 4 is proportional to the output
voltage (they are linked by the transformer turns ratio), the
regulator protects the output against over-voltage. This
function is entirely independant of the output-voltage
regulation loop and indeed will protect against output
over-voltage should the voltage error signal be lost. The
measure of over-voltage is given by:
where V
V
OUT(OVP)
IN(OVP)
= V
OUT(NOM)
is the drive voltage on pin 4.
x V
IN(OVP)/VIN(NOM)
In an over-voltage sensitive application, the drive
voltage can be set to close to 20 V and thus will protect the
output, if it rises more than 10% above nominal.
ALLOWABLE PACKAGE POWER DISSIPATION
V
OUT
AC LOW
AC HIGH
I
OUT
Figure 10 – Power Supply Output
Overload Characteristics
STR-F665xSTR-F667x
60
40
20
CONTROLLER
0.8 W MAX.
ALLOWABLE PACKAGE POWER DISSIPATION in WATTS
0
2060100
10
MOUNTING SURFACE
TEMPERATURE
STR-F6656, 56 W MAX.
STR-F6654, 55 W MAX.
STR-F6653, 48 W MAX.
STR-F6652, 43 W MAX.
Electrolytic capacitors carrying large switching frequency ripple currents (C1 and the output capacitors)
should be capable of handling the high rms currents
involved. Capacitors with low ESR are suitable. The
quasi-resonance capacitor C4 should be a high-voltage
ceramic type suitable for pulsed current operation.
The safety critical nature of the off-line application
must be considered when selecting both X and Y capacitors for common- and differential-mode noise filtering.
Use of the low-noise quasi-resonant Series STR-F6600
will allow optimization of these capacitor values.
C5, the 470 pF filtering capacitor should be a 50 V
temperature-stable (COG) ceramic type.
Resistors
Resistor R5 carries high-frequency current, and so a low
internal inductance type of 1 W rating should be used.
Resistor R9 (R
) should be 2 W metal oxide.
S
All other resistors can be 1/4 watt or 1/2 watt metal
film.
Error Amplifier
A standard TL431 transconductance amplifier or an
Allegro/Sanken Series SE error-amplifier IC can be used.
The Series SE is particularly well-suited to high-voltage
(70 V to 140 V) power outputs.
If a Series SE error-amplifier IC is used, normally phase
compensation is not required. Should additional high-
frequency attenuation be required, a capacitor (0.022 µF or
less) can be connected across the primary side (collectoremitter) of the optocoupler, a diode to maintain quasiresonant operation should be added in series with the
phototransistor emitter.
Diodes
Diodes carrying the high-frequency flyback currents
(such as the transformer rectifier diodes) should have a fast
or ultrafast reverse-recovery characteristic, adequate
current handing and peak reverse-voltage rating. Allegro/
Sanken supplies a range of suitable diodes, and these are
described in the Allegro/Sanken short-form catalogue
(AMS-127) or latest issue of Bulletin D01EC0.
Optocoupler
Both Toshiba TLP 621 and Siemens SFH 610A2 or
615A2 are suitable. A current-transfer ratio of 50% to
200% is acceptable.
The products described here are manufactured in Japan by Sanken
Electric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken Electric Co., Ltd. and Allegro MicroSystems, Inc. reserve the
right to make, from time to time, such departures from the detail
specifications as may be required to permit improvements in the
performance, reliability, or manufacturability of their products.
Therefore, the user is cautioned to verify that the information in this
publication is current before placing any order.
These products are not authorized for use as critical components in
life-support appliances, devices, or systems without express written
approval.
The information included herein is believed to be accurate and
reliable. However, Sanken Electric Co., Ltd. and Allegro
MicroSystems, Inc. assume no responsibility for its use; nor for any
infringements of patents or other rights of third parties which may
result from its use.