Datasheet STQ2LN60K3-AP Specification

Page 1
STQ2LN60K3-AP
TO-92 ammopack
1
2
3
D(2)
G(1)
S(3)
AM01476v1
N-channel 600 V, 4 Ω typ., 0.6 A SuperMESH3™ Power MOSFET
in TO-92 package
Datasheet — production data
Features
R
Order code V
STQ2LN60K3-AP 600 V < 4.5 Ω 0.6 A 2.5 W
Extremely high dv/dt capability
Very low intrinsic capacitance
Improved diode reverse recovery
DSS
DS(on)
max
characteristics
Zener-protected
Applications
I
P
D
TOT
Switching applications

Figure 1. Internal schematic diagram

Description
This SuperMESH3™ Power MOSFET is the result of improvements applied to STMicroelectronics’ SuperMESH™ technology, combined with a new optimized vertical structure. This device boasts an extremely low on­resistance, superior dynamic performance and high avalanche capability, rendering it suitable for the most demanding applications.

Table 1. Device summary

Order codes Marking Package Packaging
STQ2LN60K3-AP 2LN60K3 TO-92 Ammopack
July 2012 Doc ID 023499 Rev 1 1/14
This is information on a product in full production.
www.st.com
14
Page 2
Contents STQ2LN60K3-AP
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/14 Doc ID 023499 Rev 1
Page 3
STQ2LN60K3-AP Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit
Drain-source voltage 600 V
DS
Gate- source voltage ± 30 V
GS
I
Drain current (continuous) at TC = 25 °C 0.6 A
D
I
Drain current (continuous) at TC = 100 °C 0.38 A
D
(1)
Drain current (pulsed) 2.4 A
Total dissipation at TC = 25 °C 2.5 W
TOT
I
DM
P
V
V
Derating factor 0.02 W/°C
V
ESD(G-S)
dv/dt
T
1. Pulse width limited by safe operating area
2. ISD ≤ 0.6 A, di/dt ≤ 400 A/µs, peak VDS < V

Table 3. Thermal data

Gate source ESD (HBM-C = 100 pF, R = 1.5 kΩ)
(2)
Peak diode recovery voltage slope 12 V/ns
Storage temperature -55 to 150 °C
stg
T
Max. operating junction temperature 150 °C
j
(BR)DSS
2500 V
Symbol Parameter Value Unit
R
thj-case
R
thj-amb
Thermal resistance junction-case max 50 °C/W
Thermal resistance junction-amb max 120 °C/W

Table 4. Avalanche characteristics

Symbol Parameter Max value Unit
I
E
Avalanche current, repetitive or not-repetitive
AR
(pulse width limited by T
max)
j
Single pulse avalanche energy
AS
(starting T
= 25 °C, ID = IAR, VDD = 50 V)
j
2A
80 mJ
Doc ID 023499 Rev 1 3/14
Page 4
Electrical characteristics STQ2LN60K3-AP

2 Electrical characteristics

(TC = 25 °C unless otherwise specified)

Table 5. On /off states

Symbol Parameter Test conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on
Drain-source breakdown voltage
Zero gate voltage drain current (VGS = 0)
Gate-body leakage current (VDS = 0)
ID = 1 mA, VGS = 0 600 V
V
= 600 V
DS
V
= 600 V, TC=125 °C
DS
1
50µAµA
VGS = ± 20 V ± 10 µA
Gate threshold voltage VDS = VGS, ID = 50 µA 3 3.75 4.5 V
Static drain-source on­resistance
VGS = 10 V, ID = 1 A 4 4.5 Ω

Table 6 . D yn am ic

Symbol Parameter Test conditions Min. Typ. Max. Unit
Input capacitance
iss
Output capacitance
oss
Reverse transfer
rss
capacitance
Eq. capacitance time
(1)
related
Eq. capacitance
(2)
energy related
= 50 V, f = 1 MHz, VGS = 0 -
V
DS
= 0, VDS = 0 to 480 V
V
GS
235
22
-
3.5
-14-pF
-10-pF
C
C
C
C
C
o(tr)
o(er)
pF pF pF
R
Q
Q
Q
1. C
oss eq
when VDS increases from 0 to 80% V
2. C
oss eq
C
oss
Intrinsic gate
G
resistance
Total gate charge
g
Gate-source charge
gs
Gate-drain charge
gd
. time related is defined as a constant equivalent capacitance giving the same charging time as C
. energy related is defined as a constant equivalent capacitance giving the same stored energy as
when VDS increases from 0 to 80% V
f = 1 MHz open drain - 7 - Ω
VDD = 480 V, ID = 1 A, V
= 10 V
GS
(see Figure 1 6)
DSS
DSS
4/14 Doc ID 023499 Rev 1
12
-
1.8
7.7
nC
-
nC nC
oss
Page 5
STQ2LN60K3-AP Electrical characteristics

Table 7. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
Turn-on delay time Rise time
t
r
Turn-off-delay time Fall time
t
f
VDD = 300 V, ID =1 A, R
= 4.7 Ω, V
G
GS
= 10 V
(see Figure 15)
10
8.5
-
23.5
-
21

Table 8. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit
I
I
SDM
V
SD
Q
I
RRM
Q
I
RRM
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
Source-drain current
SD
(1)
Source-drain current (pulsed)
(2)
Forward on voltage ISD = 2 A, VGS = 0 - 1.5 V
t
Reverse recovery time
rr
Reverse recovery charge
rr
Reverse recovery current
t
Reverse recovery time
rr
Reverse recovery charge
rr
Reverse recovery current
ISD = 2 A, di/dt = 100 A/µs V
DD
ISD = 2 A, di/dt = 100 A/µs V
DD
(see Figure 20)
= 60 V (see Figure 20)
= 60 V, Tj = 150 °C
-
200
-
800
230
-
950
0.6
2.4AA
8
8.5
ns ns ns ns
ns
nC
A
ns
nC
A

Table 9. Gate-source Zener diode

Symbol Parameter Test conditions Min. Typ. Max. Unit
Gate-source breakdown
(1)
BV
GSO
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the usage of external components.
voltage
Igs= ± 1 mA (open drain) 30 - V
Doc ID 023499 Rev 1 5/14
Page 6
Electrical characteristics STQ2LN60K3-AP
I
D
1
0.1
0.01
0.1
1
100
V
DS
(V)
10
(A)
Operation in this area is
Limited by max R
DS(on)
10µs
100µs 1ms
10ms
Tj=150°C Tc=25°C Single pulse
10
0.001
AM13065v1
I
D
1.5
1.0
0.5
0
0
4
V
DS
(V)
8
(A)
2
6
2.0
5V
6V
V
GS
=10V
AM13054v1
V
GS
6
4
2
0
0
5
Q
g
(nC)
(V)
8
10
10
V
DD
=480V
I
D
=2A
12
300
200
100
0
400
500
V
DS
V
DS
(V)
AM13056v1

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance
Figure 4. Output characteristics Figure 5. Transfer characteristics
I
(A)
2.5
D
DS
=15V
V
AM13055v1
2.0
1.5
1.0
0.5
0
0
Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on-resistance
R
DS(on)
(Ω)
2
4
V
GS
=10V
8
V
6
GS
AM13057v1
4.2
4.0
3.8
3.6
3.4
3.2
3.0
1.0
0.4
0.6
0.2
0
0.8
1.2
I
D
(A)
6/14 Doc ID 023499 Rev 1
(V)
Page 7
STQ2LN60K3-AP Electrical characteristics
C
100
10
1
0.1
10
V
DS
(V)
(pF)
1
100
Ciss
Coss
Crss
AM13058v1
V
GS(th)
1.00
0.90
0.80
0.70
-75
T
J
(°C)
(norm)
-25
1.10
75
25
125
I
D
=50µA
AM13060v1
BV
DSS
-75
T
J
(°C)
(norm)
-25
75
25
125
0.90
0.95
1.00
1.05
1.10
I
D
=1mA
AM13062v1
Figure 8. Capacitance variations Figure 9. Output capacitance stored energy
E
(µJ)
oss
1.5
1
0.5
AM13059v1
Figure 10. Normalized gate threshold voltage
Figure 12. Normalized BV
vs temperature
vs temperature Figure 13. Source-drain diode forward
DSS
Doc ID 023499 Rev 1 7/14
0
0
100
200
300
400
500
600
Figure 11. Normalized on-resistance vs
temperature
R
DS(on)
(norm)
I
D
V
=1.1A
GS
=10V
2.5
2.0
1.5
1.0
0.5
0
-75
-25
25
75
125
characteristics
(V)
V
SD
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
J
=-50°C
T
J
T
J
=150°C
T
1
3
2
4
I
SD
5
V
DS
AM13061v1
T
J
(°C)
AM13063v1
=25°C
(A)
(V)
Page 8
Electrical characteristics STQ2LN60K3-AP
E
AS
0
40
T
J
(°C)
(mJ)
20
100
60
80
0
10
20
30
40
120
140
ID=2 A
V
DD
=50 V
50
60
70
80
90
AM13064v1
Figure 14. Maximum avalanche energy vs
temperature
8/14 Doc ID 023499 Rev 1
Page 9
STQ2LN60K3-AP Test circuits
AM01468v1
VGS
PW
VD
RG
RL
D.U.T.
2200
μF
3.3 μF
V
DD
AM01469v1
VDD
47kΩ
1kΩ
47kΩ
2.7kΩ
1kΩ
12V
V
i=20V=VGMAX
2200 μF
PW
IG=CONST
100Ω
100nF
D.U.T.
V
G
AM01470v1
A
D
D.U. T.
S
B
G
25
Ω
A
A
B
B
R
G
G
FAST DIODE
D
S
L=100μH
μF
3.3
1000
μF
V
DD
AM01472v1
V(BR)DSS
VDD
VDD
VD
IDM
ID

3 Test circuits

Figure 15. Switching times test circuit for
resistive load
Figure 17. Test circuit for inductive load
switching and diode recovery times

Figure 16. Gate charge test circuit

Figure 18. Unclamped Inductive load test
circuit
L
VD
2200
μF
3.3 μF
VDD
ID
Vi
D.U. T.
Pw

Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform

0
0
Doc ID 023499 Rev 1 9/14
10%
tdon
ton
90%
tr
10%
V
GS
VDS
90%
tdoff
AM01471v1
toff
tf
90%
10%
AM01473v1
Page 10
Package mechanical data STQ2LN60K3-AP

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
®
packages, depending on their level of environmental compliance. ECOPACK®
10/14 Doc ID 023499 Rev 1
Page 11
STQ2LN60K3-AP Package mechanical data

Table 10. TO-92 ammopack mechanical data

mm
Dim.
Min. Typ. Max.
A1 4.80
T 3.80
T1 1.60
T2 2.30
d 0.45 0.47 0.48
P0 12.50 12.70 12.90
P2 5.65 6.35 7.05
F1, F2 2.40 2.50 2.94
F3 4.98 5.08 5.48
delta H -2.00 2.00
W 17.50 18.00 19.00
W0 5.50 6.00 6.50
W1 8.50 9.00 9.25
W2 0.50
H 18.50 21.00
H0 15.50 16.00 18.20
H1 25.00 27.00
H3 0.50 1.00 2.00
D0 3.80 4.00 4.20
t 0.90
L 11.00
l1 3.00
delta P -1.00 1.00
Doc ID 023499 Rev 1 11/14
Page 12
Package mechanical data STQ2LN60K3-AP
A
D0
H1
H0
l1
F1 F2
P2
P0
delta H
T2
T1
F3
H3
0050910S_Rev_U

Figure 21. TO-92 ammopack drawing

T
1
H
L
d
W2
W0
W
W1
t
12/14 Doc ID 023499 Rev 1
Page 13
STQ2LN60K3-AP Revision history

5 Revision history

Table 11. Document revision history

Date Revision Changes
19-Jul-2012 1 First release.
Doc ID 023499 Rev 1 13/14
Page 14
STQ2LN60K3-AP
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