The MDmesh™ is a new revolutionary MOSFET
technology that associates the Multiple Drain
process with the Company’s
PowerMESH™horizontal layout. The resulting
product has an outstanding low on-resistance,
impressively high dv/dt and exellent avalanche
characteristics and dynamic performances.
Applications
The MDmesh™ family is very suitable for
increasing power density of high voltage
converters allowing system miniaturization
andhiher efficiencies
Input Capaci tance
Outp u t C a pacita nce
Rev er se Trans fer Ca pa citan ce
Equivalent Ouput Capacitance
D(ON) xRDS(ON)max,
ID = 10A
=25V, f=1 MHz, VGS=0
V
DS
=0, V
V
GS
=0V to 400V
DS
10S
1480
285
34
130pF
µA
µA
pF
pF
pF
RgGate Input Resistance
Q
g
Q
gs
Q
gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
f=1MHz Gate DC Bias=0
Test Signal Level=20mV
Open Drain
=400V, ID = 20A
V
DD
=10V
V
GS
(see Figure 15)
1.6Ω
40
13
19
56nC
nC
nC
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Page 4
2 Electric al characteristicsSTB20N M 50-1 - STB20NM50 - ST P20NM 50 - STP20NM 50FP
Table 6.Switching times
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
=250 V, ID=10A,
t
d(on)
Tur n-o n Delay Time
t
r
Rise Time
DD
=4.7Ω, VGS=10V
R
G
(see Figure 16)
24
16
ns
ns
t
r(Voff)
t
Off-vol tage Rise Time
t
f
c
Fall Ti me
Cross-over T ime
=400 V, ID=20A,
V
DD
=4.7Ω, VGS=10V
R
G
(see Figure 16)
9
8.5
23
Table 7.Source drain diode
SymbolParameterTest ConditionsMin.Typ.Max.Unit
I
SD
I
Note 2
SDM
V
Note 4
SD
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
(1) ISD ≤20A, di/dt ≤400A/µs, VDD ≤ V
(2) Pul s e width limited by safe op erating area
(3) Limited only by maximum temperature allowed
(4) Pulsed: pulse duration = 300µs, duty cycle 1.5%
(5) C
oss eq.
to 80% V
Source-drain Current
Source-drain Current (pulsed)
, Tj ≤ T
JMAX
ISD=20A, VGS=0
=20A, di/dt = 100A/µs,
I
SD
V
=100 V, Tj=25°C
DD
=20A, di/dt = 100A/µs,
I
SD
V
=100 V, Tj=150°C
DD
Forward on Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
(BR)DSS
is defined as a constant equivalent capacitance giving the same charging time as C
3 Test circuitsSTB20N M 50-1 - STB20NM50 - ST P20NM 50 - STP20NM 50FP
3 Test circuits
Figure 14. Switching Times Test Circuit For
Resistive Load
Figure 16. Test Circuit For Indictive Load
Switching and Diode Recovery
Times
Figure 15. Gate Charge Test Circuit
Figure 18. Unclamped Inductive Load Test
Circuit
Figure 17. Unclamped Inductive Waveform
8/16
Page 9
STB20NM 50-1 - STB20NM50 - ST P20NM50 - STP20NM 50FP4 Package mechanical data
4 Package m echanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in compliance
with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are
available at: www.st.com
9/16
Page 10
4 Package mechani cal dataSTB 20NM50-1 - STB20N M 50 - STP20NM50 - ST P20NM50F P
STB20NM 50-1 - STB20NM50 - ST P20NM50 - STP20NM 50FP6 Revision History
6 Revision His tor y
DateRevisionChanges
05-Sep-20052Insert ed Ecopack indication
15/16
Page 16
6 Revision Hist oryST B 20NM50-1 - STB20N M 50 - STP20NM50 - ST P20NM50F P
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