Datasheet STP17NK40ZFP, STP17NK40Z Datasheet (SGS Thomson Microelectronics)

STP17NK40Z - STP17NK40ZFP

N-CHANNEL 400V - 0.23Ω - 15A TO-220/TO-220FP

Zener-Protected SuperMESH™Power MOSFET

TYPE V

STP17NK40 Z
STP17NK40 ZFP

■ TYPICAL R

■ EXTREMELY HIGH dv /d t C APABILITY

■ 100% AVALANCHE TESTED

■ GATE CHARGE MINIMIZED

■ VERY LOW INTRINSIC CAPAC ITANCES

■ VERY GOOD MANUFACTURING

400 V
400 V

(on) = 0.23 Ω

DS

DSS

R

DS(on)

< 0.25 Ω
< 0.25 Ω

I

D

15 A
15 A

Pw

150 W

35 W

REPEATIBILITY

DESCRIPTION

The SuperMESH™ series is obtained through an
extreme optimization of ST ’s well established strip­based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is tak­en to ensure a very good dv/dt capability for the
most demanding applications. Such series c om pl e­ments ST full range of high voltage MOSFE Ts in­cluding revolutionary MDmesh™ products.

TO-220

TO-220FP

INTERNAL SCHEMATIC DIAGRAM

3

2

1

APPLICATIONS

■ HIGH CURRENT, HIGH SPEED SWITCHING

■ IDEAL FOR OFF-LINE POW E R SUPPL I ES,

ADAPTORS AND PFC

■ LIGHTING

ORDERING INFORMATION

SALES TYPE MARKING PACKAGE PACKAGING

STP17NK40Z P17NK40Z TO-220 TUBE

STP17NK40ZFP P17NK40ZFP TO-220FP TUBE

1/10October 2002

STP17NK40Z - STP17NK40ZFP

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

STP17NK40Z STP17NK40ZFP

V

DS

V

DGR

V

GS

I

D

I

D

I

DM

P

TOT

I

GS

V

ESD(G-S)

dv/dt (1) Peak Diode Recovery voltage slope 4.5 V/ns

Viso Insulation Withstand Voltage (DC) -- 2500 V

T

j

T

stg

(l) Pulse wi dth limited by saf e operating area

≤15A, di/dt ≤200A/µs, VDD ≤ V

(1) I

SD

(*) Limited only by maximum temperature allowed

Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)

400 V
400 V

Gate- source Voltage ± 30 V

Drain Current (continuous) at TC = 25°C
Drain Current (continuous) at TC = 100°C

(l)

Drain Current (pulsed) 60 60 (*) A
Total Dissipation at TC = 25°C

15 15 (*) A

9.4 9.4 (*) A

150 35 W
Derating Factor 1.2 0.28 W/°C
Gate-source Current (DC) ± 20 mA
Gate source ESD(HBM-C=100pF, R=1.5KΩ) 4500 V

Operating Junction Temperature
Storage Temperature

, Tj ≤ T

(BR)DSS

JMAX.

-55 to 150

-55 to 150

°C
°C

THERMA L D ATA

TO-220 TO-220FP

Rthj-case Thermal Resistance Junction-case Max 0.83 3.6 °C/W

Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W

T

l

Maximum Lead Temperature For Soldering Purpose

300 °C

AVALANCHE CHARACTERISTICS

Symbol Parameter Max Value Unit

I

AR

E

AS

Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T

max)

j

Single Pulse Avalanche Energy
(starting T

= 25 °C, ID = IAR, VDD = 50 V)

j

15 A

450 mJ

GATE-SOURCE ZENER DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

BV

GSO

Gate-Source Breakdown

Igs=± 1mA (Open Drain) 30 V

Voltage

PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES

The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components.

2/10

STP17NK40Z - STP17NK40ZFP

ELECTRICAL CHARACTERISTICS (T

=25°C UNLESS OTHERWISE SPECIFIED)

CASE

ON/OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

(BR)DSS

Drain-source

ID = 1 mA, VGS = 0 400 V

Breakdown Voltage

I

I

V

R

DS(on)

DSS

GSS

GS(th)

Zero Gate Voltage
Drain Current (V

GS

= 0)

Gate-body Leakage
Current (V

DS

= 0)
Gate Threshold Voltage
Static Drain-source On

V

= Max Rating

DS

VDS = Max Rating, TC = 125 °C

V

= ± 20 V ±10 µA

GS

V

= V

DS

, ID = 100 µA

GS

3 3.75 4.5 V

1

50

VGS = 10 V, ID = 7.5 A 0.23 0.25 Ω

Resistance

DYNAMIC

Symbol Parameter Test Conditions Min. Typ. Max. Unit

g

(1) Forward Transconductance VDS =15 V, ID= 7.5 A 10.6 S

fs

C

oss eq.

C

iss

C

oss

C

rss

Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance

(3) Equivalent Output

= 25 V, f = 1 MHz, VGS = 0 1900

V

DS

271

63

VGS = 0V, VDS = 0V to 400V 175 pF

Capacitance

SWITCHING ON

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

d(on)

Q
Q
Q

Turn-on Delay Time

t

r

g
gs
gd

Rise Time

Total Gate Charge
Gate-Source Charge
Gate-Drain Charge

VDD = 200 V, ID = 7.5 A
RG= 4.7Ω VGS = 10 V
(Resistive Load see, Figure 3)

= 320 V, ID = 15 A,

V

DD

VGS = 10 V

25
23

65
13
35

µA
µA

pF
pF
pF

ns
ns

nC
nC
nC

SWITCHING OFF

Symbol Parameter Test Conditions Min. Typ. Max. Unit

t

d(off)

Turn-off Delay Time

t

f

Fall Time

VDD = 200 V, ID = 7.5 A
RG=4.7Ω VGS = 10 V

55
13

(Resistive Load see, Figure 3)

t

r(Voff)

t
t

= 320 V, ID = 15 A,

Off-voltage Rise Time

f

c

Fall Time
Cross-over Time

V

DD

RG=4.7Ω, V

GS

= 10 V

(Inductive Load see, Figure 5)

12
13
25

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit

I

SD

I

SDM

VSD (1)

t

rr

Q

rr

I

RRM

Note: 1. Pulsed: Pu l se duration = 300 µs, duty c yc l e 1.5 %.

2. Pulse width li mited by safe operating area.

3. C

Source-drain Current

(2)

Source-drain Current (pulsed)
Forward On Voltage
Reverse Recovery Time

Reverse Recovery Charge
Reverse Recovery Current

is defined as a constant equivalent capacitance giving the same charging time as C

oss eq.

V

.

DSS

ISD = 15 A, VGS = 0
I

SD

V

DD

(see test circuit, Figure 5)

= 15 A, di/dt = 100 A/µs

= 100 V, Tj = 150°C

332

2650

16

when VDS increase s fr om 0 to 80%

oss

15
60

1.6 V

ns
ns

ns
ns
ns

A
A

ns

nC

A

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STP17NK40Z - STP17NK40ZFP

Safe Operating Area For TO-220FPSafe Operating Area For TO-220

Thermal Impedance Fo r TO-220

Output Characteristics

Thermal Impedance For TO-220FP

Transfer Characteristics

4/10

STP17NK40Z - STP17NK40ZFP

Static Drain-source On ResistanceTran sc onductance

Gate Charge vs Gate-source Voltage Capacitance Variations

Normalized Gate Threshold Volta ge vs Temp. Normalized On Resistance vs Temperature

5/10

STP17NK40Z - STP17NK40ZFP

Source-drain Diode Forward Characteristics Normalized BVDSS vs Temperature

Maximum Avalanche Energy vs Temperature

6/10

STP17NK40Z - STP17NK40ZFP

Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit

Fig. 3: Switching Times Test Circuit For

Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times

Fig. 4: Gate Charge test Circuit

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STP17NK40Z - STP17NK40ZFP

E

P011C

TO-220 MECHANICAL DATA

DIM.

A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107

D1 1.27 0.050

E 0.49 0.70 0.019 0.027

F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067

G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154

DIA. 3.75 3.85 0.147 0.151

MIN. TYP. MAX. MIN. TYP. MAX.

mm inch

A

C

D

8/10

L5

Dia.

L7

D1

L6

L2

L9

F1

G1

F

H2

G

F2

L4

STP17NK40Z - STP17NK40ZFP

TO-220FP MECHANICAL DATA

DIM.

A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106

D 2.5 2.75 0.098 0.108

E 0.45 0.7 0.017 0.027

F 0.75 1 0.030 0.039
F1 1.15 1.5 0.045 0.067
F2 1.15 1.5 0.045 0.067

G 4.95 5.2 0.195 0.204

G1 2.4 2.7 0.094 0.106

H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 .0385 0.417
L5 2.9 3.6 0.114 0.141
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366

Ø 3 3.2 0.118 0.126

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

E

A

D

B

L3

L6

L7

¯

F1

F

G1

H

G

F2

123

L2

L5

L4

9/10

STP17NK40Z - STP17NK40ZFP

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its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as cr itical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.

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