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STP16N S25
STP16NS25FP
N-CHANNEL 250V - 0.23Ω - 16A TO-220 / TO-220FP
MESH OVERLAY™ MOSFET
TYPE V
STP16NS25
STP16NS25 FP
■ TYPICAL R
■ EXTREMELY HIGH dv /d t CAPABILITY
■ 100% AVALANCHE TESTED
DS
DSS
250 V
250 V
(on) = 0.23 Ω
R
DS(on)
< 0.28 Ω
< 0.28 Ω
I
D
16 A
16 A
DESCRIPTION
Using the latest high voltage MESH OVERLAY™
process, STMicroelectronics has designed an advanced family of power MOSFETs with outstanding
performance. The new patented STrip layout coupled with the Company’s proprietary edge termination structure, makes it suitable in coverters for
lighting applications.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SWITH MODE POWER SUPPLI ES (SMPS)
■ DC-DC CONVERTERS FOR TELECOM,
INDUSTRIAL, AND LIGHTING EQUIPMENT
■ IDEAL FOR MONITOR’s B+ FUNCTION
3
2
1
TO-220
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
3
2
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
STP16NS25 STP16NS25FP
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
P
TOT
dv/dt (1) Peak Diode Recovery voltage slope 5 V/ns
V
ISO
T
stg
T
j
(•)Pu l se width limite d by safe operat i ng area
Drain-source Voltage (VGS = 0)
Drain-gate Voltage (RGS = 20 kΩ)
250 V
250 V
Gate- source Voltage ± 20 V
Drain Current (continuos) at TC = 25°C
Drain Current (continuos) at TC = 100°C
(l)
Drain Current (pulsed) 64 64(*) A
Total Dissipation at TC = 25°C
16 16(*) A
11 11(*) A
140 40 W
Derating Factor 1 0.33 W/°C
Insulation Withstand Voltage (DC) - 2500 V
Storage Temperature
Max. Operating Junction Temperature
(1) ISD≤ 16A, di/dt≤300 A/µs, VDD≤ V
(*) Limite d only by maximum temperat ure allowed
–65 to 150 °C
, Tj≤T
(BR)DSS
jMAX
1/9May 2002
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STP16NS25 - STP16NS25FP
THERMA L D ATA
TO-220 TO-220FP °C/W
Rthj-case Thermal Resistance Junction-case Max 0.9 3 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
T
l
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
I
AR
E
AS
ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)
OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
(BR)DSS
I
DSS
I
GSS
Maximum Lead Temperature For Soldering Purpose 300 °C
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by T
max)
j
Single Pulse Avalanche Energy
(starting T
Drain-source
= 25 °C, ID = IAR, VDD = 50 V)
j
ID = 250 µA, VGS = 0 250 V
16 A
600 mJ
Breakdown Voltage
= Max Rating
Zero Gate Voltage
Drain Current (V
GS
Gate-body Leakage
Current (V
DS
= 0)
= 0)
V
DS
V
= Max Rating, TC = 125 °C
DS
V
= ± 20 V ±100 nA
GS
1µA
10 µA
ON
(1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
V
GS(th)
R
DS(on)
Gate Threshold Voltage
Static Drain-source On
= VGS, ID = 250µA
DS
VGS = 10V, ID = 8 A
234V
0.23 0.28 Ω
Resistance
DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
(1) Forward Transconductance VDS > I
g
fs
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 190 pF
Reverse Transfer
Capacitance
ID=8 A
V
DS
D(on)
x R
DS(on)max,
= 25V, f = 1 MHz, VGS = 0
15 S
1270 pF
74 pF
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STP16NS25 - STP16NS25FP
ELECTRICAL CHARACTERISTICS (CONTINUED)
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V
t
d(on)
Q
Q
Q
t
r
g
gs
gd
Turn-on Delay Time
Rise Time 26 ns
Total Gate Charge
Gate-Source Charge 7.9 nC
Gate-Drain Charge 22.3 nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t
d(Voff)
t
r(Voff)
t
t
f
t
f
c
Turn-off- Delay Time
Fall Time
Off-voltage Rise Time
Fall Time
Cross-over Time
SOURCE DRAIN DIODE
Symbol Parameter Test Conditions Min. Typ. Max. Unit
I
SD
I
SDM
VSD (1)
t
rr
Q
rr
I
RRM
Note: 1. Pulsed: Pu l se duration = 300 µ s, duty cycle 1. 5 %.
2. Pulse width li mited by safe operating area.
Source-drain Current 16 A
(2)
Source-drain Current (pulsed) 64 A
Forward On Voltage
Reverse Recovery Time
Reverse Recovery Charge 1.5 µC
Reverse Recovery Current 11.4 A
= 125 V, ID = 8 A
DD
RG= 4.7Ω VGS = 10 V
(see test circuit, Figure 3)
V
= 200V, ID = 16 A,
DD
VGS = 10V
VDD = 125V, ID = 8 A,
RG=4.7Ω, V
GS
= 10V
(see test circuit, Figure 3)
V
= 200V, ID = 16 A,
clamp
R
=4.7Ω, V
G
GS
= 10V
(see test circuit, Figure 5)
ISD = 16 A, VGS = 0
I
= 16 A, di/dt = 100A/µs
SD
VDD = 30V, Tj = 150°C
(see test circuit, Figure 5)
14.5 ns
59 83 nC
72
32
24
28
56
1.5 V
270 ns
ns
ns
ns
ns
ns
Safe Operating Area for TO-220FPSafe Operating Area for TO-220
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STP16NS25 - STP16NS25FP
Thermal Impedance for TO-220FPThermal Impedance for TO-220
Transfer CharacteristicsOutput Characteristics
Transconductance
4/9
Static Drain-source On Resistance
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STP16NS25 - STP16NS25FP
Gate Charge vs Gate-source Voltage
Capacitance Variations
Normalized On Resistance vs Temperatur eNormalized Gate Thereshold Voltage vs Temp.
Source-drain Diode Forward Characteristics
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STP16NS25 - STP16NS25FP
Fig. 2: Unclamped Inductive WaveformFig. 1: Unclamped Inductive Load Test Circuit
Fig. 3: Switching Times Test Circuit For
Resistive Load
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
Fig. 4: Gate Charge test Circuit
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E
TO-220 MECHANICAL DATA
STP16NS25 - STP16NS25FP
DIM.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
MIN. TYP. MAX. MIN. TYP. MAX.
mm inch
A
C
D
L5
Dia.
L7
D1
L6
L2
L9
F1
G1
F
H2
G
F2
L4
P011C
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STP16NS25 - STP16NS25FP
TO-220FP MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.4 4.6 0.173 0.181
B 2.5 2.7 0.098 0.106
D 2.5 2.75 0.098 0.108
E 0.45 0.7 0.017 0.027
F 0.75 1 0.030 0.039
F1 1.15 1.7 0.045 0.067
F2 1.15 1.7 0.045 0.067
G 4.95 5.2 0.195 0.204
G1 2.4 2.7 0.094 0.106
H 10 10.4 0.393 0.409
L2 16 0.630
L3 28.6 30.6 1.126 1.204
L4 9.8 10.6 0.385 0.417
L6 15.9 16.4 0.626 0.645
L7 9 9.3 0.354 0.366
Ø 3 3.2 0.118 0.126
mm inch
E
A
D
8/9
B
L3
L6
L7
¯
F1
F
G1
H
G
F2
123
L2
L4
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STP16NS25 - STP16NS25FP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or the
consequences of use of su ch in formation nor for any in fringement of paten ts or o ther rights of third parties w hich may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously suppli ed. STMi croelect ronics pr oducts are not author ized for use as c ritical component s in li fe suppo rt devi ces or
systems without express written approval of STMicroelectronics.
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© The ST logo is a registered trademark of STMicroelectronics
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