The STP08CDC596 is a monolithic,
medium-voltage, low current power 8-bit shift
register designed for LED panel display. The
STP08CDC596 contains a 8-bit serial-in,
parallel-out shift register that feeds a 8-bitD-type
storage register. In the output stage, eight
regulated current sources were designed to
provide 15-120mA constant current to drive the
LEDs.
The STP08CDC596 contains the built-IN error
detection feature. The device performs this
additional function wi thout any in crea se of t he pi n
number and any change of the pin function, if
compared to the standard device without error
detection. Consequently, choosing this device
does not mean to change the footprint on the
board. To perform this functionality mode, the
device needs a digital key coming from the
Microprocessor. The STP08CDC596 is able to
detect: open and sho rt on the LED line, short to
SO-16DIP-16
TSSOP16
GND, short to Led voltage supply. The data
mapping of output channels status detection is
provided by a feedbac k from the serial output to
the Microprocessor.
Trough an external resistor, users m ay adjust the
STP08CDC596 output current, controlling the light
intensity of LEDs.
The STP08CDC596 guarantees 16V output
driving capability, allowing users to connect more
LEDs in series. The high clock frequency, 25 MHz,
also satisfies the system requirement of high
volume data transmission.
The device is offered in DIP-16, SO-16 and
TSSOP -16 packages.
The STP08CDC596 is well suitable for traffic
display signs where the detection feature is
strongly required.
Table 1: Order Codes
TypeTemp. RangePackageComments
STP08CDC596B1-40°C to 125°CDIP-1625 part per tube
STP08CDC596M-40°C to 125°CSO-16 (Tube)50 parts per tube
STP08CDC596MTR-40°C to 125°CSO-16 (Tape & Reel)2500 parts per reel
STP08CDC596TTR-40°C to 125°CTSSOP16 (Tape & Reel)2500 parts per reel
13OE/DM2Output enable input terminal (active low)
14SDOSerial data out terminal
15R-EXTConstant Current programming
16V
DD
5V Supply voltage terminal
Table 4: Absolute Maximum Ratings
SymbolParameterValueUnit
V
I
f
T
T
V
I
V
GND
CLK
OPR
STG
Supply Voltage
DD
Output Voltage
O
Output Current
O
Input Voltage-0.4 to VDD+0.4
I
GND Termin al Current
Clock Frequency
Operating Temperature Range
Storage Temperature Range
0 to 7V
-0.5 to 16V
120mA
980mA
25MHz
-40 to +125°C
-55 to +150°C
V
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
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STP08CDC596
Table 5: Thermal Data
SymbolParameterDIP-16SO-16TSSOP16Unit
R
thj-amb
Table 6: Recommended Operating Conditions
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
DD
V
O
I
O
I
OH
I
OL
V
IH
V
IL
t
wLAT
t
wCLK
t
wEN
t
SETUP(D)
t
HOLD(D)
t
SETUP(L)
f
CLK
(1) If the device is connected in cascade, it may not be possible achieve the maximum data transfer. Please considered the timings carefully.
(2) In norm al mode the OE/DM2 must rem ai n l ow at least two c l ock cycles.
V
LE/DM1 Pulse WidthVDD = 3.0 to 3.6V1020ns
CLK Pulse Width1020ns
OE/DM2 Pulse Width (1)120400ns
Setup Time for DATA520ns
Hold Time for DATA415ns
Setup Time for LATCH815ns
Clock Frequency (2)25MHz
SymbolParameterTest ConditionsMin.Typ.Max.Unit
V
V
I
V
V
I
OL1
I
OL2
∆I
∆I
R
SIN(up)
R
SIN(down)
I
DD(OFF1)
I
DD(OFF2)
I
DD(OFF3)
I
DD(ON1)
I
DD(ON2)
Input Voltage High Level0.7V
IH
Input Voltage Low LevelGND0.3V
IL
Output Leakage CurrentVOH = 16 V10µA
OH
Output Voltage (Serial-OUT) IOL = 1mA0.4V
OL
Output Voltage (Serial-OUT) IOH = -1mAVDD-0.4VV
OH
Output CurrentVO = 0.7V R
Output Current Error
OL1
between bit (All Output ON)
OL2
VO = 0.7V R
VO = 0.7V R
VO = 0.7V R
= 910 Ω18.820.924.00mA
EXT
= 360 Ω46.0051.556.5mA
EXT
= 910 Ω± 2± 5%
EXT
= 360 Ω± 1± 4%
EXT
DD
Pull-up Resistor150300600KΩ
Pull-down Resistor100200400KΩ
Supply Current (OFF)R
Supply Current (ON)R
= OPEN OUT 0 to 7 = OFF0.450.7mA
EXT
R
= 910 Ω OUT 0 to 7 = OFF3.06.0
EXT
R
= 360 Ω OUT 0 to 7 = OFF8.212.0
EXT
= 910 Ω OUT 0 to 7 = ON3.16.2
EXT
R
= 360 Ω OUT 0 to 7 = ON8.412.8
EXT
V
DD
DD
V
V
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STP08CDC596
Table 8: Switching Characteristics (VDD=3.3 to 5.5V, T = 25°C, unless otherwise specified.)
SymbolParameterTest ConditionsMin.Typ.Max.Unit
t
PLH1
t
PLH2
t
PLH3
t
PLH
t
PHL1
t
PHL2
t
PHL3
t
PHL
Propagation Delay Time,
OUTn, LE/DM1 = H,
CLKOE/DM2 = L
Propagation Delay Time,
LE/DM1-OUTn, OE/DM2 = L
Propagation Delay Time,
VDD = 3 VVIH = V
DD
VIL = GNDCL = 13pF
IO = 40mAVL = 3 V
R
= 470 ΩRL = 65 Ω
EXT
180280ns
150280ns
140280ns
OE/DM2-OUTn, LE/DM1 = H
Propagation Delay Time,
2535ns
CLK-SDO
Propagation Delay Time,
OUTn, LE/DM1 = H,
CLK-
3060ns
OE/DM2 = L
Propagation Delay Time,
3050ns
LE/DM1-OUTn, OE/DM2 = L
Propagation Delay Time,
3570ns
OE/DM2-OUTn, LE/DM1 = H
Propagation Delay Time,
3040ns
CLK-SDO
t
Output Rise Time220ns
r
t
Output Fall Time20ns
f
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS
Figure 2: OE/DM2 Terminal
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Figure 3: LE/DM1 Ter m i nal
Figure 4: CLK, SDI Terminal
STP08CDC596
Figure 5: SDO Termi nal
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STP08CDC596
Figure 6: Block Diagram
Figure 7: Timing Dia gram
In norma l mode the OE/DM2 must remain low at least two clock cycles.
From the “Normal Mode” condition the device can
switch to the “Error Detection Mode” by a logic
sequence on the OE/DM2 and LE/DM1 pins as
showed in the following Table and Diagram:
Table 9: En te rin g In D et ec tio n Truth Table
CLK1°2°3°4°5°
OE/DM2HLHHH
LE/DM1LLLHL
Figure 13: Enter ing In Detection Timing Diagram
STP08CDC596
After these five CLK cycles the device goes into
the” Error Detection Mode” and at the 6
th
rise front
of CLK the SDI data are ready for the sampling.
Phase Two: “Error Detection”
The eight data bits m ust be set “1” in order to s et
ON all the outputs during the detection. The data
are latched by LE/ DM1 and after that the outputs
are ready for the detection process. When the
Figure 14: Detection Diagram
Micro controller switches the OE/DM2 to LOW, the
device drives the LEDs in order to analyze if an
OPEN or SHORT condition has occurred.
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STP08CDC596
The LEDs status will be detected al least in 2
microseconds and after this time the micro
controller puts OE in HIGH state and the output
data det ec t io n r e s ult w ill g o t o the micropr oc e s s or
The detection dat a format is the same of data i n
normal mode. As soon as all the detection data
bits are available on the serial line, the device may
go back to normal mode operation.
via SDO.
CONDITIONS IN ORDER TO GET A SUCCESSFULLY DETECTION CONDITION
Table 10: Detection Condition (V
SW-1 or SW-3b
SW-2 or SW-3a
where: IO = the output current prog ram m ed by the R
Open Line or Output Short
to GND detected
Short on LED or Short to
V-LED detected
= 3.3 to 5 V Temp. Range -40 to 85°C)
DD
==> I
==> VO ≥ 2.4 V
EXT, IODEC
≤ 0.5 x I
ODEC
= the det e c ted output current in detection mode.
O
No error detected
No error detected
Figure 15: De t ection Mode
==> I
==> VO ≤ 2.2 V
ODEC
≥ 0.5 x I
O
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STP08CDC596
Phase Three: “Resuming to Normal Mode”
The sequence for re-entering in normal mode is showed in the following Table and diagram:
Table 11: Resuming to Normal Mode Timi ng Diagram
CLK1°2°3°4°5°
OE/DM2HLHHH
LE/DM1LLLLL
Figure 16: Resuming to Normal Mode Timing Diagram
For proper device operation the "Entering in detection" sequence must be follow by a "Resume Mode" sequence, isn’t possible to insert consecutive equal sequence.
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STP08CDC596
Figure 17: T ypical Output Current-R
Resistor
EXT
Figure 18: Power Dissipation vs Temperature
Package
Figure 19: T ypical Dropout Voltage vs Output
Current
Figure 20: T ypical Output Current vs ±∆IOL(%)
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Figure 21: Timing example for Open and/or Short detection
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